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|
# IBM_PROLOG_BEGIN_TAG
# This is an automatically generated prolog.
#
# $Source: src/usr/diag/prdf/common/plat/pegasus/Membuf_acts_TP.rule $
#
# IBM CONFIDENTIAL
#
# COPYRIGHT International Business Machines Corp. 2012,2014
#
# p1
#
# Object Code Only (OCO) source materials
# Licensed Internal Code Source Materials
# IBM HostBoot Licensed Internal Code
#
# The source code for this program is not published or otherwise
# divested of its trade secrets, irrespective of what has been
# deposited with the U.S. Copyright Office.
#
# Origin: 30
#
# IBM_PROLOG_END_TAG
################################################################################
# TP Chiplet Registers
################################################################################
rule TpChipletFir
{
CHECK_STOP:
(TP_CHIPLET_CS_FIR & `1000000000000000`) & ~TP_CHIPLET_FIR_MASK;
UNIT_CS:
(TP_CHIPLET_CS_FIR & `1000000000000000`) & ~TP_CHIPLET_FIR_MASK;
RECOVERABLE:
((TP_CHIPLET_RE_FIR >> 2) & `1000000000000000`) & ~TP_CHIPLET_FIR_MASK;
};
group gTpChipletFir filter singlebit
{
/** TP_CHIPLET_FIR[3]
* Attention from LFIR
*/
(TpChipletFir, bit(3)) ? analyze(gTpLFir);
};
################################################################################
# TP Chiplet LFIR
################################################################################
# RAS spreadsheet: p8dd1_mss_FFDC_37_ reviewd.xls
rule TpLFir
{
CHECK_STOP: TP_LFIR & ~TP_LFIR_MASK & ~TP_LFIR_ACT0 & ~TP_LFIR_ACT1;
UNIT_CS: TP_LFIR & ~TP_LFIR_MASK & ~TP_LFIR_ACT0 & ~TP_LFIR_ACT1;
RECOVERABLE: TP_LFIR & ~TP_LFIR_MASK & ~TP_LFIR_ACT0 & TP_LFIR_ACT1;
};
group gTpLFir filter singlebit
{
/** TP_LFIR[0]
* CFIR internal parity error
*/
(TpLFir, bit(0)) ? thresholdAndMask_self;
/** TP_LFIR[1]
* Local errors from GPIO (PCB error)
*/
(TpLFir, bit(1)) ? defaultMaskedError;
/** TP_LFIR[2]
* Local errors from CC (PCB error)
*/
(TpLFir, bit(2)) ? defaultMaskedError;
/** TP_LFIR[3]
* Local errors from CC (OPCG, parity, scan collision, ...)
*/
(TpLFir, bit(3)) ? defaultMaskedError;
/** TP_LFIR[4]
* Local errors from PSC (PCB error)
*/
(TpLFir, bit(4)) ? defaultMaskedError;
/** TP_LFIR[5]
* Local errors from PSC (parity error)
*/
(TpLFir, bit(5)) ? defaultMaskedError;
/** TP_LFIR[6]
* Local errors from Thermal (parity error)
*/
(TpLFir, bit(6)) ? defaultMaskedError;
/** TP_LFIR[7]
* Local errors from Thermal (PCB error)
*/
(TpLFir, bit(7)) ? defaultMaskedError;
/** TP_LFIR[8:10]
* Local errors from Thermal (Trip error)
*/
(TpLFir, bit(8|9|10)) ? defaultMaskedError;
/** TP_LFIR[11:12]
* Local errors from Trace Array ( error)
*/
(TpLFir, bit(11|12)) ? defaultMaskedError;
/** TP_LFIR[13:14]
* Local errors from ITR
*/
(TpLFir, bit(13|14)) ? thresholdAndMask_self;
/** TP_LFIR[15]
* Local errors from ITR ( itr_tc_pcbsl_slave_fir_err )
*/
(TpLFir, bit(15)) ? defaultMaskedError;
/** TP_LFIR[16:18]
* Local errors from PIB
*/
(TpLFir, bit(16|17|18)) ? defaultMaskedError;
/** TP_LFIR[19]
* local errors from nest PLL
*
* These should never trigger directly themselves.
* Should be handled by global PRD PLL code.
*/
(TpLFir, bit(19)) ? threshold32pday;
/** TP_LFIR[20]
* local errors from mem PLL
*
* These should never trigger directly themselves.
* Should be handled by global PRD PLL code.
*/
(TpLFir, bit(20)) ? threshold32pday;
/** TP_LFIR[40]
* local errors from mem PLL
*
* Malfunction alert (local xstop in another chiplet)
*/
(TpLFir, bit(40)) ? defaultMaskedError;
};
################################################################################
# Actions specific to TP chiplet
################################################################################
|
