path: root/src/usr/diag/prdf/common/plat/pegasus/Mba.rule

# IBM_PROLOG_BEGIN_TAG
# This is an automatically generated prolog.
#
# $Source: src/usr/diag/prdf/common/plat/pegasus/Mba.rule $
#
# IBM CONFIDENTIAL
#
# COPYRIGHT International Business Machines Corp. 2012,2014
#
# p1
#
# Object Code Only (OCO) source materials
# Licensed Internal Code Source Materials
# IBM HostBoot Licensed Internal Code
#
# The source code for this program is not published or otherwise
# divested of its trade secrets, irrespective of what has been
# deposited with the U.S. Copyright Office.
#
# Origin: 30
#
# IBM_PROLOG_END_TAG

################################################################################
#
# Scope:
#   Registers and actions for the following chiplets:
#
# Chiplet  Register Addresses       Description
# =======  =======================  ============================================
#   MEM    0x03010400 - 0x0301043F  MBA 01
#   MEM    0x03010600 - 0x0301063F  MBA 01 MCBIST
#   MEM    0x03010C00 - 0x03010C3F  MBA 23
#   MEM    0x03010E00 - 0x03010E3F  MBA 23 MCBIST
#
################################################################################

chip Mba
{
    name        "Centaur MBA Chiplet";
    targettype  TYPE_MBA;
    sigoff      0x8000;
    dump        DUMP_CONTENT_HW;
    scomlen     64;

.include "prdfCenMbaExtraSig.H";

 #############################################################################
 #                                                                           #
 #  ######                                                                   #
 #  #     #  ######   ####     ###    ####    #####  ######  #####    ####   #
 #  #     #  #       #    #     #    #          #    #       #    #  #       #
 #  ######   #####   #          #     ####      #    #####   #    #   ####   #
 #  #   #    #       #  ###     #         #     #    #       #####        #  #
 #  #    #   #       #    #     #    #    #     #    #       #   #   #    #  #
 #  #     #  ######   ####     ###    ####      #    ######  #    #   ####   #
 #                                                                           #
 #############################################################################

    ############################################################################
    # MEM Chiplet MBAFIR
    ############################################################################

    register MBAFIR
    {
        name        "MBU.MBA01.MBA_MCBIST.SCOMFIR.MBAFIRQ";
        scomaddr    0x03010600;
        reset       (&, 0x03010601);
        mask        (|, 0x03010605);
        capture     group FirRegs;
        capture     group MemChipletRegs;
    };

    register MBAFIR_MASK
    {
        name        "MBU.MBA01.MBA_MCBIST.SCOMFIR.MBAFIRMASK";
        scomaddr    0x03010603;
        capture     group FirRegs;
        capture     group MemChipletRegs;
    };

    register MBAFIR_ACT0
    {
        name        "MBU.MBA01.MBA_MCBIST.SCOMFIR.MBAFIRACT0";
        scomaddr    0x03010606;
        capture     group FirRegs;
        capture     group MemChipletRegs;
        capture     req nonzero("MBAFIR");
    };

    register MBAFIR_ACT1
    {
        name        "MBU.MBA01.MBA_MCBIST.SCOMFIR.MBAFIRACT1";
        scomaddr    0x03010607;
        capture     group FirRegs;
        capture     group MemChipletRegs;
        capture     req nonzero("MBAFIR");
    };

    ############################################################################
    # MEM Chiplet MBASECUREFIR
    ############################################################################

    # This register is hardwired to channel failure (checkstop) and we cannot
    # mask or change the state of the action registers.
    register MBASECUREFIR
    {
        name        "MBU.MBA01.MBA_SRQ.MBASIRQ";
        scomaddr    0x0301041b;
        reset       (&, 0x0301041c);
        capture     group FirRegs;
        capture     group MemChipletRegs;
    };

    ############################################################################
    # MEM Chiplet DDRPHYFIR
    ############################################################################

    register MBADDRPHYFIR
    {
        name        "DPHY01.PHY01_DDRPHY_FIR_REG";
        scomaddr    0x800200900301143F;
        reset       (&, 0x800200910301143F);
        mask        (|, 0x800200950301143F);
        capture     group FirRegs;
        capture     group MemChipletRegs;
    };

    register MBADDRPHYFIR_AND
    {
        name        "DPHY01.PHY01_DDRPHY_FIR_REG_AND";
        scomaddr    0x800200910301143F;
        capture     group never;
        access      write_only;
    };

    register MBADDRPHYFIR_MASK
    {
        name        "DPHY01.PHY01_DDRPHY_FIR_MASK_REG";
        scomaddr    0x800200930301143F;
        capture     group FirRegs;
        capture     group MemChipletRegs;
    };

    register MBADDRPHYFIR_ACT0
    {
        name        "DPHY01.PHY01_DDRPHY_FIR_ACTION0_REG";
        scomaddr    0x800200960301143F;
        capture     group FirRegs;
        capture     group MemChipletRegs;
        capture     req nonzero("MBADDRPHYFIR");
    };

    register MBADDRPHYFIR_ACT1
    {
        name        "DPHY01.PHY01_DDRPHY_FIR_ACTION1_REG";
        scomaddr    0x800200970301143F;
        capture     group FirRegs;
        capture     group MemChipletRegs;
        capture     req nonzero("MBADDRPHYFIR");
    };

    ############################################################################
    # MEM Chiplet MBACALFIR
    ############################################################################

    register MBACALFIR
    {
        name        "MBU.MBA01.MBA_SRQ.MBACALFIRQ";
        scomaddr    0x03010400;
        reset       (&, 0x03010401);
        mask        (|, 0x03010405);
        capture     group FirRegs;
        capture     group MemChipletRegs;
    };

    register MBACALFIR_AND
    {
        name        "MBU.MBA01.MBA_SRQ.MBACALFIRQ AND";
        scomaddr    0x03010401;
        capture     group never;
        access      write_only;
    };

    register MBACALFIR_MASK
    {
        name        "MBU.MBA01.MBA_SRQ.MBACALFIR_MASK";
        scomaddr    0x03010403;
        capture     group FirRegs;
        capture     group MemChipletRegs;
    };

    register MBACALFIR_MASK_OR
    {
        name        "MBU.MBA01.MBA_SRQ.MBACALFIR_MASK OR";
        scomaddr    0x03010405;
        capture     group never;
        access      write_only;
    };

    register MBACALFIR_ACT0
    {
        name        "MBU.MBA01.MBA_SRQ.MBACALFIR_ACTION0";
        scomaddr    0x03010406;
        capture     group FirRegs;
        capture     group MemChipletRegs;
        capture     req nonzero("MBACALFIR");
    };

    register MBACALFIR_ACT1
    {
        name        "MBU.MBA01.MBA_SRQ.MBACALFIR_ACTION1";
        scomaddr    0x03010407;
        capture     group FirRegs;
        capture     group MemChipletRegs;
        capture     req nonzero("MBACALFIR");
    };

    ############################################################################
    # MEM Chiplet MBASPA
    ############################################################################

    register MBASPA
    {
        name        "MBU.MBA01.MBA_MCBIST.SCOMFIR.MBSPAQ";
        scomaddr    0x03010611;
        reset       (&, 0x03010612);
        mask        (|, 0x03010614);
        capture     group FirRegs;
        capture     group MemChipletRegs;
    };

    register MBASPA_AND
    {
        name        "MBU.MBA01.MBA_MCBIST.SCOMFIR.MBSPAQ_AND";
        scomaddr    0x03010612;
        capture     group never;
        access      write_only;
    };

    register MBASPA_MASK
    {
        name        "MBU.MBA01.MBA_MCBIST.SCOMFIR.MBSPAMSKQ";
        scomaddr    0x03010614;
        capture     group FirRegs;
        capture     group MemChipletRegs;
    };

    ############################################################################
    # Error Report Registers
    ############################################################################

    register MBA_ERR_REPORT
    {
        name        "MBU.MBA01.MBA_SRQ.MBA_ERR_REPORTQ";
        scomaddr    0x0301041A;
        capture     group CerrRegs;
        capture     group MemChipletRegs;
    };

    register MBA_MCBERRPTQ
    {
        name        "MBU.MBA01.MBA_MCBIST.SCOMFIR.MBA_MCBERRPTQ";
        scomaddr    0x030106E7;
        capture     group CerrRegs;
        capture     group MemChipletRegs;
    };

    register DDRPHY_APB_FIR_ERR0_P0
    {
        name        "DPHY01.DDRPHY_APB_FIR_ERR0_P0";
        scomaddr    0x8000D0060301143F;
        capture     group CerrRegs;
        capture     group MemChipletRegs;
    };

    register DDRPHY_APB_FIR_ERR1_P0
    {
        name        "DPHY01.DDRPHY_APB_FIR_ERR1_P0";
        scomaddr    0x8000D0070301143F;
        capture     group CerrRegs;
        capture     group MemChipletRegs;
    };

    register DDRPHY_APB_FIR_ERR0_P1
    {
        name        "DPHY01.DDRPHY_APB_FIR_ERR0_P1";
        scomaddr    0x8001D0060301143F;
        capture     group CerrRegs;
        capture     group MemChipletRegs;
    };

    register DDRPHY_APB_FIR_ERR1_P1
    {
        name        "DPHY01.DDRPHY_APB_FIR_ERR1_P1";
        scomaddr    0x8001D0070301143F;
        capture     group CerrRegs;
        capture     group MemChipletRegs;
    };

    ############################################################################
    # Maintenance Command Registers
    ############################################################################

    register MBMCT
    {
        name        "MBA Maintenance Command Type Register";
        scomaddr    0x0301060A;
        capture     group default;
    };

    # NOTE: PRD doesn't use MBMCC directly and the bits are cleared by HW so I
    #       see no reason to add it here.

    register MBMSR
    {
        name        "MBA Maintenance Command Status Register";
        scomaddr    0x0301060C;
        capture     group default;
    };

    register MBMACA
    {
        name        "MBA Maintenance Command Start Address Register";
        scomaddr    0x0301060D;
        capture     group default;
    };

    register MBMEA
    {
        name        "MBA Maintenance Command End Address Register";
        scomaddr    0x0301060E;
        capture     group default;
    };

    register MBASCTL
    {
        name        "MBA Memory Scrub/Read Control Register";
        scomaddr    0x0301060F;
        capture     group default;
    };

    register MBAECTL
    {
        name        "MBA Error Control Register";
        scomaddr    0x03010610;
        capture     group default;
    };

};

 ##############################################################################
 #                                                                            #
 # ####                                 #                                     #
 # #   # #   # #    #####  ###      #  # #    ##  ##### ###  ###  #   #  ###  #
 # #   # #   # #    #     #        #  #   #  #  #   #    #  #   # ##  # #     #
 # ####  #   # #    ####   ###    #  ####### #      #    #  #   # # # #  ###  #
 # #  #  #   # #    #         #  #   #     # #  #   #    #  #   # #  ##     # #
 # #   #  ###  #### #####  ###  #    #     #  ##    #   ###  ###  #   #  ###  #
 #                                                                            #
 ##############################################################################

# This group is a layer of indirection. Normally, each rule file will have a
# single global or chiplet FIR which will have group that defines which lower
# level FIRs to analyze. Unfortunately, the MBA target contains only a subset of
# the FIRs in the Centaur's MEM chiplet. So the MEM chiplet FIR's group
# definition must remain in Membuf.rule. This group will serve as a psuedo
# chiplet FIR. This group could contain the bit definitions for all of the MBA
# registers, however, we could not utilize the filter for each register.
# Instead, the bit definitions will simply analyze the respective FIR groups.
# The FIRs in this group will be analyzed in order so if a FIR should be
# analyzed before another then simply change the order of the FIRs in this
# group.

# NOTE: The rule definition for this group must be different than that of the
#       individual FIR groups. Otherwise, it causes hashing collisions in the
#       signatures. In this case, we will add the SPECIAL attention line even
#       though none of these registers will trigger a special attention. This
#       should change the hash enough to make a unique signature.

rule tmpMbaFir
{
  CHECK_STOP:  MBAFIR & ~MBAFIR_MASK & ~MBAFIR_ACT0 & ~MBAFIR_ACT1;
  UNIT_CS:     MBAFIR & ~MBAFIR_MASK & ~MBAFIR_ACT0 & ~MBAFIR_ACT1;
  RECOVERABLE: MBAFIR & ~MBAFIR_MASK & ~MBAFIR_ACT0 &  MBAFIR_ACT1;
  SPECIAL:     MBAFIR; # See note above.
};

rule tmpMbaSecureFir
{
  # NOTE: This secure FIR will only report checkstop attentions.
  CHECK_STOP: MBASECUREFIR;
  UNIT_CS:    MBASECUREFIR;
  SPECIAL:    MBASECUREFIR; # See note above.
};

rule tmpMbaCalFir
{
  CHECK_STOP:  MBACALFIR & ~MBACALFIR_MASK & ~MBACALFIR_ACT0 & ~MBACALFIR_ACT1;
  UNIT_CS:     MBACALFIR & ~MBACALFIR_MASK & ~MBACALFIR_ACT0 & ~MBACALFIR_ACT1;
  RECOVERABLE: MBACALFIR & ~MBACALFIR_MASK & ~MBACALFIR_ACT0 &  MBACALFIR_ACT1;
  SPECIAL:     MBACALFIR; # See note above.
};

rule tmpMbaDdrPhyFir
{
  CHECK_STOP:
    MBADDRPHYFIR & ~MBADDRPHYFIR_MASK & ~MBADDRPHYFIR_ACT0 & ~MBADDRPHYFIR_ACT1;
  UNIT_CS:
    MBADDRPHYFIR & ~MBADDRPHYFIR_MASK & ~MBADDRPHYFIR_ACT0 & ~MBADDRPHYFIR_ACT1;
  RECOVERABLE:
    MBADDRPHYFIR & ~MBADDRPHYFIR_MASK & ~MBADDRPHYFIR_ACT0 &  MBADDRPHYFIR_ACT1;
  SPECIAL:
    MBADDRPHYFIR; # See note above.
};

group gMBA attntype CHECK_STOP, RECOVERABLE, UNIT_CS filter singlebit
{
    (tmpMbaFir,       bit( 0| 1| 2| 3| 4| 5| 6| 7| 8| 9|
                          10|11|12|13|14|15|16|17|18|19|
                          20|21|22|23|24|25|26|27|28|29|
                          30|31|32|33|34|35|36|37|38|39|
                          40|41|42|43|44|45|46|47|48|49|
                          50|51|52|53|54|55|56|57|58|59|
                          60|61|62|63 ))               ? analyze(gMbaFir);

    (tmpMbaSecureFir, bit( 0| 1| 2| 3| 4| 5| 6| 7| 8| 9|
                          10|11|12|13|14|15|16|17|18|19|
                          20|21|22|23|24|25|26|27|28|29|
                          30|31|32|33|34|35|36|37|38|39|
                          40|41|42|43|44|45|46|47|48|49|
                          50|51|52|53|54|55|56|57|58|59|
                          60|61|62|63 ))               ? analyze(gMbaSecureFir);

    (tmpMbaDdrPhyFir, bit( 0| 1| 2| 3| 4| 5| 6| 7| 8| 9|
                          10|11|12|13|14|15|16|17|18|19|
                          20|21|22|23|24|25|26|27|28|29|
                          30|31|32|33|34|35|36|37|38|39|
                          40|41|42|43|44|45|46|47|48|49|
                          50|51|52|53|54|55|56|57|58|59|
                          60|61|62|63 ))               ? analyze(gMbaDdrPhyFir);

    (tmpMbaCalFir,    bit( 0| 1| 2| 3| 4| 5| 6| 7| 8| 9|
                          10|11|12|13|14|15|16|17|18|19|
                          20|21|22|23|24|25|26|27|28|29|
                          30|31|32|33|34|35|36|37|38|39|
                          40|41|42|43|44|45|46|47|48|49|
                          50|51|52|53|54|55|56|57|58|59|
                          60|61|62|63 ))               ? analyze(gMbaCalFir);
};

################################################################################
# MEM Chiplet MBAFIR
################################################################################

# RAS spreadsheet: p8dd1_mss_FFDC_37_ reviewd.xls
# TODO via RTC 23125. In some Fir bits, we may have to callout Centaur
# rather than MBA. Marc will change callout rules as per latest design.
# This is applicable for all FIRs in this file
rule MbaFir
{
    CHECK_STOP:  MBAFIR & ~MBAFIR_MASK & ~MBAFIR_ACT0 & ~MBAFIR_ACT1;
    UNIT_CS:     MBAFIR & ~MBAFIR_MASK & ~MBAFIR_ACT0 & ~MBAFIR_ACT1;
    RECOVERABLE: MBAFIR & ~MBAFIR_MASK & ~MBAFIR_ACT0 &  MBAFIR_ACT1;
};

group gMbaFir filter singlebit
{
    /** MBAFIR[0]
     *  MBAFIRQ_INVALID_MAINT_CMD
     */
    (MbaFir, bit(0)) ? defaultMaskedError;

    /** MBAFIR[1]
     *  MBAFIRQ_INVALID_MAINT_ADDRESS
     */
    (MbaFir, bit(1)) ? defaultMaskedError;

    /** MBAFIR[2]
     *  MBAFIRQ_MULTI_ADDRESS_MAINT_TIMEOUT
     */
    (MbaFir, bit(2)) ? SelfMedThr1;

    /** MBAFIR[3]
     *  MBAFIRQ_INTERNAL_FSM_ERROR
     */
    (MbaFir, bit(3)) ? SelfMedThr1;

    /** MBAFIR[4]
     *  MBAFIRQ_MCBIST_ERROR
     */
    (MbaFir, bit(4)) ? defaultMaskedError;

    /** MBAFIR[5]
     *  MBAFIRQ_SCOM_CMD_REG_PE
     */
    (MbaFir, bit(5)) ? SelfMedThr1;

    /** MBAFIR[6]
     *  MBAFIRQ_CHANNEL_CHKSTP_ERR
     */
    (MbaFir, bit(6)) ? SelfMedThr1;

    /** MBAFIR[7]
     *  MBAFIRQ_WRD_CAW2_DATA_CE_UE_ERR
     */
    (MbaFir, bit(7)) ? SelfMedThr1;

    # This is for DD2 only
    /** MBAFIR[8]
     *  MBAFIRQ_MAINT_1HOT_ST_ERROR_DD2
     */
    (MbaFir, bit(8)) ? SelfMedThr1;

    /** MBAFIR[9:14]
     *  Reserved
     */
    (MbaFir, bit(9|10|11|12|13|14)) ? defaultMaskedError;

    /** MBAFIR[15]
     *  MBAFIRQ_INTERNAL_SCOM_ERROR
     */
    (MbaFir, bit(15)) ? thresholdAndMask_self;

    /** MBAFIR[16]
     *  MBAFIRQ_INTERNAL_SCOM_ERROR_CLONE
     */
    (MbaFir, bit(16)) ? thresholdAndMask_self;
};

################################################################################
# MEM Chiplet MBASECUREFIR
################################################################################

rule MbaSecureFir
{
  # NOTE: This secure FIR will only report checkstop attentions.
  CHECK_STOP: MBASECUREFIR;
  UNIT_CS:    MBASECUREFIR;
};

group gMbaSecureFir filter singlebit
{
    /** MBASECUREFIR[0]
     *  MBASIRQ_INVALID_MBA_CAL0Q_ACCESS
     */
    (MbaSecureFir, bit(0)) ? callout2ndLvlMedThr1dumpSh;

    /** MBASECUREFIR[1]
     *  MBASIRQ_INVALID_MBA_CAL1Q_ACCESS
     */
    (MbaSecureFir, bit(1)) ? callout2ndLvlMedThr1dumpSh;

    /** MBASECUREFIR[2]
     *  MBASIRQ_INVALID_MBA_CAL2Q_ACCESS
     */
    (MbaSecureFir, bit(2)) ? callout2ndLvlMedThr1dumpSh;

    /** MBASECUREFIR[3]
     *  MBASIRQ_INVALID_MBA_CAL3Q_ACCESS
     */
    (MbaSecureFir, bit(3)) ? callout2ndLvlMedThr1dumpSh;

    /** MBASECUREFIR[4]
     *  MBASIRQ_INVALID_DDR_CONFIG_REG_ACCESS
     */
    (MbaSecureFir, bit(4)) ? callout2ndLvlMedThr1dumpSh;

    /** MBASECUREFIR[5]
     *  MBASIRQ_INVALID_SIR_MASK_OR_ACTION_REGISTER_ACCESS
     */
    (MbaSecureFir, bit(5)) ? callout2ndLvlMedThr1dumpSh;
};

################################################################################
# MEM Chiplet DDRPHYFIR
################################################################################
# RAS spreadsheet: p8dd1_mss_FFDC_37_ reviewd.xls
rule MbaDdrPhyFir
{
  CHECK_STOP:
    MBADDRPHYFIR & ~MBADDRPHYFIR_MASK & ~MBADDRPHYFIR_ACT0 & ~MBADDRPHYFIR_ACT1;
  UNIT_CS:
    MBADDRPHYFIR & ~MBADDRPHYFIR_MASK & ~MBADDRPHYFIR_ACT0 & ~MBADDRPHYFIR_ACT1;
  RECOVERABLE:
    MBADDRPHYFIR & ~MBADDRPHYFIR_MASK & ~MBADDRPHYFIR_ACT0 &  MBADDRPHYFIR_ACT1;
};

group gMbaDdrPhyFir filter singlebit
{
    /** MBADDRPHYFIR[48]
     *  PHY01_DDRPHY_FIR_REG_DDR0_FSM_CKSTP
     */
    (MbaDdrPhyFir, bit(48)) ? SelfMedThr1;

    /** MBADDRPHYFIR[49]
     *  PHY01_DDRPHY_FIR_REG_DDR0_PARITY_CKSTP
     */
    (MbaDdrPhyFir, bit(49)) ? SelfMedThr1;

    /** MBADDRPHYFIR[50]
     *  PHY01_DDRPHY_FIR_REG_DDR0_CALIBRATION_ERROR
     */
    (MbaDdrPhyFir, bit(50)) ? defaultMaskedError;

    /** MBADDRPHYFIR[51]
     *  PHY01_DDRPHY_FIR_REG_DDR0_FSM_ERR
     */
    (MbaDdrPhyFir, bit(51)) ? SelfMedThr32PerDay;

    /** MBADDRPHYFIR[52]
     *  PHY01_DDRPHY_FIR_REG_DDR0_PARITY_ERR
     */
    (MbaDdrPhyFir, bit(52)) ? SelfMedThr32PerDay;

    /** MBADDRPHYFIR[53]
     *  PHY01_DDRPHY_FIR_REG_DDR01_FIR_PARITY_ERR
     */
    (MbaDdrPhyFir, bit(53)) ? thresholdAndMask_self;

    /** MBADDRPHYFIR[54:55]
     *  Reserved
     */
    (MbaDdrPhyFir, bit(54|55)) ? defaultMaskedError;

    /** MBADDRPHYFIR[56]
     *  PHY01_DDRPHY_FIR_REG_DDR1_FSM_CKSTP
     */
    (MbaDdrPhyFir, bit(56)) ? SelfMedThr1;

    /** MBADDRPHYFIR[57]
     *  PHY01_DDRPHY_FIR_REG_DDR1_PARITY_CKSTP
     */
    (MbaDdrPhyFir, bit(57)) ? SelfMedThr1;

    /** MBADDRPHYFIR[58]
     *  PHY01_DDRPHY_FIR_REG_DDR1_CALIBRATION_ERROR
     */
    (MbaDdrPhyFir, bit(58)) ? defaultMaskedError;

    /** MBADDRPHYFIR[59]
     *  PHY01_DDRPHY_FIR_REG_DDR1_FSM_ERR
     */
    (MbaDdrPhyFir, bit(59)) ? SelfMedThr32PerDay;

    /** MBADDRPHYFIR[60]
     *  PHY01_DDRPHY_FIR_REG_DDR1_PARITY_ERR
     */
    (MbaDdrPhyFir, bit(60)) ? SelfMedThr32PerDay;
};

################################################################################
# MEM Chiplet MBACALFIR
################################################################################

# RAS spreadsheet: p8dd1_mss_FFDC_37_ reviewd.xls
rule MbaCalFir
{
  CHECK_STOP:  MBACALFIR & ~MBACALFIR_MASK & ~MBACALFIR_ACT0 & ~MBACALFIR_ACT1;
  UNIT_CS:     MBACALFIR & ~MBACALFIR_MASK & ~MBACALFIR_ACT0 & ~MBACALFIR_ACT1;
  RECOVERABLE: MBACALFIR & ~MBACALFIR_MASK & ~MBACALFIR_ACT0 &  MBACALFIR_ACT1;
};

group gMbaCalFir filter singlebit
{
    /** MBACALFIR[0]
     *  MBACALFIRQ_MBA_RECOVERABLE_ERROR
     */
    (MbaCalFir, bit(0)) ? SelfMedThr1;

    /** MBACALFIR[1]
     *  MBACALFIRQ_MBA_NONRECOVERABLE_ERROR
     */
    (MbaCalFir, bit(1)) ? SelfMedThr1;

    /** MBACALFIR[2]
     *  MBACALFIRQ_REFRESH_OVERRUN
     */
    (MbaCalFir, bit(2)) ? SelfMedThr32PerDay;

    /** MBACALFIR[3]
     *  MBACALFIRQ_WAT_ERROR
     */
    (MbaCalFir, bit(3)) ? defaultMaskedError;

    /** MBACALFIR[4]
     *  MBACALFIRQ_RCD_PARITY_ERROR_0
     */
    (MbaCalFir, bit(4)) ? CalloutMbaAndDimmOnPort0;

    /** MBACALFIR[5]
     *  MBACALFIRQ_DDR0_CAL_TIMEOUT_ERR
     */
    (MbaCalFir, bit(5)) ? SelfMedThr1;

    /** MBACALFIR[6]
     *  MBACALFIRQ_DDR1_CAL_TIMEOUT_ERR
     */
    (MbaCalFir, bit(6)) ? SelfMedThr1;

    /** MBACALFIR[7]
     *  MBACALFIRQ_RCD_PARITY_ERROR_1
     */
    (MbaCalFir, bit(7)) ? CalloutMbaAndDimmOnPort1;

    /** MBACALFIR[8]
     *  MBACALFIRQ_MBX_TO_MBA_PAR_ERROR
     */
    (MbaCalFir, bit(8)) ? SelfMedThr1;

    /** MBACALFIR[9]
     *  MBACALFIRQ_MBA_WRD_UE
     */
    (MbaCalFir, bit(9)) ? SelfMedThr1;

    /** MBACALFIR[10]
     *  MBACALFIRQ_MBA_WRD_CE
     */
    (MbaCalFir, bit(10)) ? thresholdAndMask_self;

    /** MBACALFIR[11]
     *  MBACALFIRQ_MBA_MAINT_UE
     */
    (MbaCalFir, bit(11)) ? SelfMedThr1;

    /** MBACALFIR[12]
     *  MBACALFIRQ_MBA_MAINT_CE
     */
    (MbaCalFir, bit(12)) ? SelfMedThr32PerDay;

    /** MBACALFIR[13]
     *  MBACALFIRQ_DDR_CAL_RESET_TIMEOUT
     */
    (MbaCalFir, bit(13)) ? SelfMedThr1;

    /** MBACALFIR[14]
     *  MBACALFIRQ_WRQ_DATA_CE
     */
    (MbaCalFir, bit(14)) ? thresholdAndMask_self;

    /** MBACALFIR[15]
     *  MBACALFIRQ_WRQ_DATA_UE
     */
    (MbaCalFir, bit(15)) ? SelfMedThr1;

    /** MBACALFIR[16]
     *  MBACALFIRQ_WRQ_DATA_SUE
     */
    (MbaCalFir, bit(16)) ? defaultMaskedError;

    /** MBACALFIR[17]
     *  MBACALFIRQ_WRQ_RRQ_HANG_ERR
     */
    (MbaCalFir, bit(17)) ? SelfMedThr1;

    /** MBACALFIR[18]
     *  MBACALFIRQ_SM_1HOT_ERR
     */
    (MbaCalFir, bit(18)) ? SelfMedThr1;

    /** MBACALFIR[19]
     *  MBACALFIRQ_WRD_SCOM_ERROR
     */
    (MbaCalFir, bit(19)) ? thresholdAndMask_self;

    /** MBACALFIR[20]
     *  DD1: MBACALFIRQ_INTERNAL_SCOM_ERROR
     */
    (MbaCalFir, bit(20)) ? thresholdAndMask_self; # DD1 action, masked for DD2+

    /** MBACALFIR[21]
     *  DD1: MBACALFIRQ_INTERNAL_SCOM_ERROR_COPY
     */
    (MbaCalFir, bit(21)) ? thresholdAndMask_self; # DD1 action, masked for DD2+

    # This is for DD2 only
    /** MBACALFIR[22]
     *  MBACALFIRQ_RHMR_SEC_ALREADY_FULL
     */
    (MbaCalFir, bit(22)) ? defaultMaskedError;

    # This is for DD2 only
    /** MBACALFIR[23]
     *  Reserved
     */
    (MbaCalFir, bit(23)) ? defaultMaskedError;

    # This is for DD2 only
    /** MBACALFIR[24]
     *  MBACALFIRQ_INTERNAL_SCOM_ERROR
     */
    (MbaCalFir, bit(24)) ? thresholdAndMask_self;

    # This is for DD2 only
    /** MBACALFIR[25]
     *  MBACALFIRQ_INTERNAL_SCOM_ERROR_COPY
     */
    (MbaCalFir, bit(25)) ? thresholdAndMask_self;
};

###############################################################################
# MEM Chiplet MBASPA
################################################################################

rule MbaSpa
{
    SPECIAL: MBASPA & ~MBASPA_MASK;
};

group gMbaSpa attntype SPECIAL filter singlebit
{
    /** MBASPA[0]
     *  MBSPAQ_COMMAND_COMPLETE_WO_ENA_ERR_ATTN
     */
    (MbaSpa, bit(0)) ? analyzeMaintCmdComplete;

    /** MBASPA[1]
     *  MBSPAQ_HARD_CE_ETE_ATTN
     */
    (MbaSpa, bit(1)) ? TBDDefaultCallout;

    /** MBASPA[2]
     *  MBSPAQ_SOFT_CE_ETE_ATTN
     */
    (MbaSpa, bit(2)) ? TBDDefaultCallout;

    /** MBASPA[3]
     *  MBSPAQ_INTERMITTENT_ETE_ATTN
     */
    (MbaSpa, bit(3)) ? TBDDefaultCallout;

    /** MBASPA[4]
     *  MBSPAQ_RCE_ETE_ATTN
     */
    (MbaSpa, bit(4)) ? TBDDefaultCallout;

    /** MBASPA[5]
     *  MBSPAQ_EMERGENCY_THROTTLE_ATTN
     */
    (MbaSpa, bit(5)) ? TBDDefaultCallout;

    /** MBASPA[6]
     *  MBSPAQ_FIRMWARE_ATTN0
     */
    (MbaSpa, bit(6)) ? TBDDefaultCallout;

    /** MBASPA[7]
     *  MBSPAQ_FIRMWARE_ATTN1
     */
    (MbaSpa, bit(7)) ? TBDDefaultCallout;

    /** MBASPA[8]
     *  MBSPAQ_WAT_DEBUG_ATTN
     */
    # WORKAROUND: HW217608
    # For Centaur DD1.0, the hardware team will utilize the WAT logic to look
    # for a command complete and trigger this bit. Note that the HW will still
    # trigger MBASPA[0], however, that bit should be masked for this
    # workaround.
    (MbaSpa, bit(8)) ? analyzeMaintCmdComplete;

    /** MBASPA[9]
     *  MBSPAQ_SPARE_ATTN1
     */
    (MbaSpa, bit(9)) ? TBDDefaultCallout;

    /** MBASPA[10]
     *  MBSPAQ_MCBIST_DONE
     */
    (MbaSpa, bit(10)) ? TBDDefaultCallout;
};

 ##############################################################################
 #                                                                            #
 #    #                                  ###                                  #
 #   # #    ##  ##### ###  ###  #   #   #   # #     #    ###   ###  ###  ###  #
 #  #   #  #  #   #    #  #   # ##  #   #     #    # #  #     #     #   #     #
 # ####### #      #    #  #   # # # #   #     #   #####  ###   ###  ##   ###  #
 # #     # #  #   #    #  #   # #  ##   #   # #   #   #     #     # #       # #
 # #     #  ##    #   ###  ###  #   #    ###  ### #   #  ###   ###  ###  ###  #
 #                                                                            #
 ##############################################################################

# Include the common action set.
.include "CommonActions.rule";

################################################################################
# Higher level actions
################################################################################

/** Analyze maintenance command complete */
actionclass analyzeMaintCmdComplete
{
    funccall("MaintCmdComplete");  # Must be called last so return code can be
                                   # passed on to rule code.
};

/** Callout MBA and DIMMs on Port 0 */
actionclass CalloutMbaAndDimmOnPort0
{
    funccall("CalloutMbaAndDimmOnPort0");
    threshold1;
};

/** Callout MBA and DIMMs on Port 1 */
actionclass CalloutMbaAndDimmOnPort1
{
    funccall("CalloutMbaAndDimmOnPort1");
    threshold1;
};