path: root/src/usr/diag/prdf/common/plat/p9/p9_xbus.rule

# IBM_PROLOG_BEGIN_TAG
# This is an automatically generated prolog.
#
# $Source: src/usr/diag/prdf/common/plat/p9/p9_xbus.rule $
#
# OpenPOWER HostBoot Project
#
# Contributors Listed Below - COPYRIGHT 2016,2018
# [+] International Business Machines Corp.
#
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
# You may obtain a copy of the License at
#
#     http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS,
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
# implied. See the License for the specific language governing
# permissions and limitations under the License.
#
# IBM_PROLOG_END_TAG

chip p9_xbus
{
    name        "P9 XBUS chiplet";
    targettype  TYPE_XBUS;
    sigoff      0x9000;
    dump        DUMP_CONTENT_HW;
    scomlen     64;

#Import signatures
.include "prdfP9ProcMbCommonExtraSig.H";

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    ############################################################################
    # P9 XBUS target IOXBFIR
    ############################################################################

    register IOXBFIR
    {
        name        "P9 XBUS target IOXBFIR";
        scomaddr    0x06010c00;
        reset       (&, 0x06010c01);
        mask        (|, 0x06010c05);
        capture     group default;
    };

    register IOXBFIR_MASK
    {
        name        "P9 XBUS target IOXBFIR MASK";
        scomaddr    0x06010c03;
        capture     group default;
    };

    register IOXBFIR_ACT0
    {
        name        "P9 XBUS target IOXBFIR ACT0";
        scomaddr    0x06010c06;
        capture     group default;
        capture     req nonzero("IOXBFIR");
    };

    register IOXBFIR_ACT1
    {
        name        "P9 XBUS target IOXBFIR ACT1";
        scomaddr    0x06010c07;
        capture     group default;
        capture     req nonzero("IOXBFIR");
    };

    ############################################################################
    # P9 XBUS target IOELFIR
    ############################################################################

    register IOELFIR
    {
        name        "P9 XBUS target IOELFIR";
        scomaddr    0x06011800;
        reset       (&, 0x06011801);
        mask        (|, 0x06011805);
        capture     group default;
    };

    register IOELFIR_MASK
    {
        name        "P9 XBUS target IOELFIR MASK";
        scomaddr    0x06011803;
        capture     group default;
    };

    register IOELFIR_ACT0
    {
        name        "P9 XBUS target IOELFIR ACT0";
        scomaddr    0x06011806;
        capture     group default;
        capture     req nonzero("IOELFIR");
    };

    register IOELFIR_ACT1
    {
        name        "P9 XBUS target IOELFIR ACT1";
        scomaddr    0x06011807;
        capture     group default;
        capture     req nonzero("IOELFIR");
    };

# Include registers not defined by the xml
.include "p9_xbus_regs.rule";

};

 ##############################################################################
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################################################################################
# Summary for XBUS
################################################################################

rule rXBUS
{
  CHECK_STOP:
    summary( 0, rIOXBFIR ) |
    summary( 1, rIOELFIR );

  RECOVERABLE:
    summary( 0, rIOXBFIR ) |
    summary( 1, rIOELFIR );

  UNIT_CS:
    summary( 0, rIOXBFIR ) |
    summary( 1, rIOELFIR );

};

group gXBUS attntype CHECK_STOP, RECOVERABLE, UNIT_CS filter singlebit
{
    (rXBUS, bit(0)) ? analyze(gIOXBFIR);
    (rXBUS, bit(1)) ? analyze(gIOELFIR);
};

################################################################################
# P9 XBUS target IOXBFIR
################################################################################

rule rIOXBFIR
{
  CHECK_STOP:
    IOXBFIR & ~IOXBFIR_MASK & ~IOXBFIR_ACT0 & ~IOXBFIR_ACT1;
  RECOVERABLE:
    IOXBFIR & ~IOXBFIR_MASK & ~IOXBFIR_ACT0 &  IOXBFIR_ACT1;
  UNIT_CS:
    IOXBFIR & ~IOXBFIR_MASK &  IOXBFIR_ACT0 &  IOXBFIR_ACT1;
};

group gIOXBFIR filter singlebit, cs_root_cause
{
    /** IOXBFIR[0]
     *  RX_INVALID_STATE_OR_PARITY_ERROR
     */
    (rIOXBFIR, bit(0)) ? defaultMaskedError;

    /** IOXBFIR[1]
     *  TX_INVALID_STATE_OR_PARITY_ERROR
     */
    (rIOXBFIR, bit(1)) ? defaultMaskedError;

    /** IOXBFIR[2]
     *  GCR_HANG_ERROR
     */
    (rIOXBFIR, bit(2)) ? self_th_1;

    /** IOXBFIR[3:7]
     *  spare
     */
    (rIOXBFIR, bit(3|4|5|6|7)) ? defaultMaskedError;

    /** IOXBFIR[8]
     *  RX_BUS0_TRAINING_ERROR
     */
    (rIOXBFIR, bit(8)) ? defaultMaskedError;

    /** IOXBFIR[9]
     *  Spare lane deployed on clock group 0
     */
    (rIOXBFIR, bit(9)) ? spareDeployed_xbus_clkgrp0;

    /** IOXBFIR[10]
     *  Max spares exceeded on clock group 0
     */
    (rIOXBFIR, bit(10)) ? maxSparesExceeded_xbus_clkgrp0;

    /** IOXBFIR[11]
     *  RX_BUS0_RECAL_OR_DYN_REPAIR_ERROR
     */
    (rIOXBFIR, bit(11)) ? defaultMaskedError;

    /** IOXBFIR[12]
     *  Too many bus errors on clock group 0
     */
    (rIOXBFIR, bit(12)) ? tooManyBusErrors_xbus_clkgrp0;

    /** IOXBFIR[13:15]
     *  spare
     */
    (rIOXBFIR, bit(13|14|15)) ? defaultMaskedError;

    /** IOXBFIR[16]
     *  RX_BUS1_TRAINING_ERROR
     */
    (rIOXBFIR, bit(16)) ? defaultMaskedError;

    /** IOXBFIR[17]
     *  Spare lane deployed on clock group 1
     */
    (rIOXBFIR, bit(17)) ? spareDeployed_xbus_clkgrp1;

    /** IOXBFIR[18]
     *  Max spares exceeded on clock group 1
     */
    (rIOXBFIR, bit(18)) ? maxSparesExceeded_xbus_clkgrp1;

    /** IOXBFIR[19]
     *  RX_BUS1_RECAL_OR_DYN_REPAIR_ERROR
     */
    (rIOXBFIR, bit(19)) ? defaultMaskedError;

    /** IOXBFIR[20]
     *  Too many bus errors on clock group 1
     */
    (rIOXBFIR, bit(20)) ? tooManyBusErrors_xbus_clkgrp1;

    /** IOXBFIR[21:23]
     *  spare
     */
    (rIOXBFIR, bit(21|22|23)) ? defaultMaskedError;

    /** IOXBFIR[24]
     *  RX_BUS2_TRAINING_ERROR
     */
    (rIOXBFIR, bit(24)) ? defaultMaskedError;

    /** IOXBFIR[25]
     *  RX_BUS2_SPARE_DEPLOYED
     */
    (rIOXBFIR, bit(25)) ? defaultMaskedError;

    /** IOXBFIR[26]
     *  RX_BUS2_MAX_SPARES_EXCEEDED
     */
    (rIOXBFIR, bit(26)) ? defaultMaskedError;

    /** IOXBFIR[27]
     *  RX_BUS2_RECAL_OR_DYN_REPAIR_ERROR
     */
    (rIOXBFIR, bit(27)) ? defaultMaskedError;

    /** IOXBFIR[28]
     *  RX_BUS2_TOO_MANY_BUS_ERRORS
     */
    (rIOXBFIR, bit(28)) ? defaultMaskedError;

    /** IOXBFIR[29:31]
     *  spare
     */
    (rIOXBFIR, bit(29|30|31)) ? defaultMaskedError;

    /** IOXBFIR[32]
     *  RX_BUS3_TRAINING_ERROR
     */
    (rIOXBFIR, bit(32)) ? defaultMaskedError;

    /** IOXBFIR[33]
     *  RX_BUS3_SPARE_DEPLOYED
     */
    (rIOXBFIR, bit(33)) ? defaultMaskedError;

    /** IOXBFIR[34]
     *  RX_BUS3_MAX_SPARES_EXCEEDED
     */
    (rIOXBFIR, bit(34)) ? defaultMaskedError;

    /** IOXBFIR[35]
     *  RX_BUS3_RECAL_OR_DYN_REPAIR_ERROR
     */
    (rIOXBFIR, bit(35)) ? defaultMaskedError;

    /** IOXBFIR[36]
     *  RX_BUS3_TOO_MANY_BUS_ERRORS
     */
    (rIOXBFIR, bit(36)) ? defaultMaskedError;

    /** IOXBFIR[37:39]
     *  spare
     */
    (rIOXBFIR, bit(37|38|39)) ? defaultMaskedError;

    /** IOXBFIR[40]
     *  RX_BUS4_TRAINING_ERROR
     */
    (rIOXBFIR, bit(40)) ? defaultMaskedError;

    /** IOXBFIR[41]
     *  RX_BUS4_SPARE_DEPLOYED
     */
    (rIOXBFIR, bit(41)) ? defaultMaskedError;

    /** IOXBFIR[42]
     *  RX_BUS4_MAX_SPARES_EXCEEDED
     */
    (rIOXBFIR, bit(42)) ? defaultMaskedError;

    /** IOXBFIR[43]
     *  RX_BUS4_RECAL_OR_DYN_REPAIR_ERROR
     */
    (rIOXBFIR, bit(43)) ? defaultMaskedError;

    /** IOXBFIR[44]
     *  RX_BUS4_TOO_MANY_BUS_ERRORS
     */
    (rIOXBFIR, bit(44)) ? defaultMaskedError;

    /** IOXBFIR[45:47]
     *  spare
     */
    (rIOXBFIR, bit(45|46|47)) ? defaultMaskedError;

    /** IOXBFIR[48]
     *  SCOMFIR_ERROR
     */
    (rIOXBFIR, bit(48)) ? defaultMaskedError;

    /** IOXBFIR[49]
     *  SCOMFIR_ERROR_CLONE
     */
    (rIOXBFIR, bit(49)) ? defaultMaskedError;

};

################################################################################
# P9 XBUS target IOELFIR
################################################################################

rule rIOELFIR
{
  CHECK_STOP:
    IOELFIR & ~IOELFIR_MASK & ~IOELFIR_ACT0 & ~IOELFIR_ACT1;
  RECOVERABLE:
    IOELFIR & ~IOELFIR_MASK & ~IOELFIR_ACT0 &  IOELFIR_ACT1;
  UNIT_CS:
    IOELFIR & ~IOELFIR_MASK &  IOELFIR_ACT0 &  IOELFIR_ACT1;
};

group gIOELFIR filter singlebit, cs_root_cause( 54, 55, 56, 57, 58, 59 )
{
    /** IOELFIR[0]
     *  link0 trained
     */
    (rIOELFIR, bit(0)) ? defaultMaskedError;

    /** IOELFIR[1]
     *  link1 trained
     */
    (rIOELFIR, bit(1)) ? defaultMaskedError;

    /** IOELFIR[2:3]
     *  spare
     */
    (rIOELFIR, bit(2|3)) ? defaultMaskedError;

    /** IOELFIR[4]
     *  link0 replay threshold
     */
    (rIOELFIR, bit(4)) ? defaultMaskedError;

    /** IOELFIR[5]
     *  link1 replay threshold
     */
    (rIOELFIR, bit(5)) ? defaultMaskedError;

    /** IOELFIR[6]
     *  link0 crc error
     */
    (rIOELFIR, bit(6)) ? threshold_and_mask_self;

    /** IOELFIR[7]
     *  link1 crc error
     */
    (rIOELFIR, bit(7)) ? threshold_and_mask_self;

    /** IOELFIR[8]
     *  link0 nak received
     */
    (rIOELFIR, bit(8)) ? defaultMaskedError;

    /** IOELFIR[9]
     *  link1 nak received
     */
    (rIOELFIR, bit(9)) ? defaultMaskedError;

    /** IOELFIR[10]
     *  link0 replay buffer full
     */
    (rIOELFIR, bit(10)) ? defaultMaskedError;

    /** IOELFIR[11]
     *  link1 replay buffer full
     */
    (rIOELFIR, bit(11)) ? defaultMaskedError;

    /** IOELFIR[12]
     *  link0 sl ecc threshold
     */
    (rIOELFIR, bit(12)) ? defaultMaskedError;

    /** IOELFIR[13]
     *  link1 sl ecc threshold
     */
    (rIOELFIR, bit(13)) ? defaultMaskedError;

    /** IOELFIR[14]
     *  link0 sl ecc correctable
     */
    (rIOELFIR, bit(14)) ? threshold_and_mask_self;

    /** IOELFIR[15]
     *  link1 sl ecc correctable
     */
    (rIOELFIR, bit(15)) ? threshold_and_mask_self;

    /** IOELFIR[16]
     *  link0 sl ecc ue
     */
    (rIOELFIR, bit(16)) ? threshold_and_mask_self;

    /** IOELFIR[17]
     *  link1 sl ecc ue
     */
    (rIOELFIR, bit(17)) ? threshold_and_mask_self;

    /** IOELFIR[18:39]
     *  spare
     */
    (rIOELFIR, bit(18|19|20|21|22|23|24|25|26|27|28|29|30|31|32|33|34|35|36|37|38|39)) ? defaultMaskedError;

    /** IOELFIR[40]
     *  link0 tcomplete bad
     */
    (rIOELFIR, bit(40)) ? defaultMaskedError;

    /** IOELFIR[41]
     *  link1 tcomplete bad
     */
    (rIOELFIR, bit(41)) ? defaultMaskedError;

    /** IOELFIR[42:43]
     *  spare
     */
    (rIOELFIR, bit(42|43)) ? defaultMaskedError;

    /** IOELFIR[44]
     *  link0 spare done
     */
    (rIOELFIR, bit(44)) ? defaultMaskedError;

    /** IOELFIR[45]
     *  link1 spare done
     */
    (rIOELFIR, bit(45)) ? defaultMaskedError;

    /** IOELFIR[46]
     *  link0 too many crc errors
     */
    (rIOELFIR, bit(46)) ? defaultMaskedError;

    /** IOELFIR[47]
     *  link1 too many crc errors
     */
    (rIOELFIR, bit(47)) ? defaultMaskedError;

    /** IOELFIR[48:50]
     *  spare
     */
    (rIOELFIR, bit(48|49|50)) ? defaultMaskedError;

    /** IOELFIR[51]
     *  psave invalid state (internal error)
     */
    (rIOELFIR, bit(51)) ? self_th_1;

    /** IOELFIR[52]
     *  link0 correctable array error
     */
    (rIOELFIR, bit(52)) ? calloutBusInterface_th_32perDay;

    /** IOELFIR[53]
     *  link1 correctable array error
     */
    (rIOELFIR, bit(53)) ? calloutBusInterface_th_32perDay;

    /** IOELFIR[54]
     *  link0 uncorrectable array error
     */
    (rIOELFIR, bit(54)) ? calloutBusInterface_th_32perDay;

    /** IOELFIR[55]
     *  link1 uncorrectable array error
     */
    (rIOELFIR, bit(55)) ? calloutBusInterface_th_32perDay;

    /** IOELFIR[56]
     *  link0 training failed
     */
    (rIOELFIR, bit(56)) ? calloutBusInterface_th_32perDay;

    /** IOELFIR[57]
     *  link1 training failed
     */
    (rIOELFIR, bit(57)) ? calloutBusInterface_th_32perDay;

    /** IOELFIR[58]
     *  link0 unrecoverable error
     */
    (rIOELFIR, bit(58)) ? calloutBusInterface_th_32perDay;

    /** IOELFIR[59]
     *  link1 unrecoverable error
     */
    (rIOELFIR, bit(59)) ? calloutBusInterface_th_32perDay;

    /** IOELFIR[60]
     *  link0 internal error
     */
    (rIOELFIR, bit(60)) ? self_th_32perDay;

    /** IOELFIR[61]
     *  link1 internal error
     */
    (rIOELFIR, bit(61)) ? self_th_32perDay;

    /** IOELFIR[62]
     *  fir scom err dup
     */
    (rIOELFIR, bit(62)) ? defaultMaskedError;

    /** IOELFIR[63]
     *  fir scom err
     */
    (rIOELFIR, bit(63)) ? defaultMaskedError;

};

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# Include the common action set.
.include "p9_common_actions.rule";
# Include the chip-specific action set.
.include "p9_xbus_actions.rule";