path: root/src/usr/diag/prdf/common/plat/p9/p9_common_proc_actions.rule

# IBM_PROLOG_BEGIN_TAG
# This is an automatically generated prolog.
#
# $Source: src/usr/diag/prdf/common/plat/p9/p9_common_proc_actions.rule $
#
# OpenPOWER HostBoot Project
#
# Contributors Listed Below - COPYRIGHT 2017,2019
# [+] International Business Machines Corp.
#
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
# You may obtain a copy of the License at
#
#     http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS,
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
# implied. See the License for the specific language governing
# permissions and limitations under the License.
#
# IBM_PROLOG_END_TAG

########################################################################
#
#  TOD Rules and Groups
#
########################################################################

rule TodErrors
{
    TOD_ERRORREGISTER & (~TOD_ERRORMASK) & (~TOD_ERRORACTION);
};


group gTodErrors filter singlebit
{
    /** TOD_ERRORREGISTER[0]
     *  M_PATH_CONTROL_REG_DATA_PARITY_ERROR
     */
    (TodErrors,bit(0)) ? defaultMaskedError;

    /** TOD_ERRORREGISTER[1]
     *  M_PATH_0_PARITY_ERROR
     */
    (TodErrors,bit(1)) ? selfCapThr32TopReConfig;

    /** TOD_ERRORREGISTER[2]
     *  M_PATH_1_PARITY_ERROR
     */
    (TodErrors,bit(2)) ? selfCapThr32TopReConfig;

    /** TOD_ERRORREGISTER[3]
     *  PCRP0_DATA_PARITY_ERROR
     */
    (TodErrors,bit(3)) ? defaultMaskedError;

    /** TOD_ERRORREGISTER[4]
     *  PCRP1_DATA_PARITY_ERROR
     */
    (TodErrors,bit(4)) ? defaultMaskedError;

    /** TOD_ERRORREGISTER[5]
     *  SCRP0_DATA_PARITY_ERROR
     */
    (TodErrors,bit(5)) ? defaultMaskedError;

    /** TOD_ERRORREGISTER[6]
     *  SCRP1_DATA_PARITY_ERROR
     */
    (TodErrors,bit(6)) ? defaultMaskedError;

    /** TOD_ERRORREGISTER[7]
     *  SPCR_DATA_PARITY_ERROR
     */
    (TodErrors,bit(7)) ? defaultMaskedError;

    /** TOD_ERRORREGISTER[8]
     *  IPCR_DATA_PARITY_ERROR
     */
    (TodErrors,bit(8)) ? defaultMaskedError;

    /** TOD_ERRORREGISTER[9]
     *  PSMSCR_DATA_PARITY_ERROR
     */
    (TodErrors,bit(9)) ? defaultMaskedError;

    /** TOD_ERRORREGISTER[10]
     *  S_PATH_0_PARITY_ERROr
     */
    (TodErrors,bit(10)) ? selfCapThr32TopReConfig;

    /** TOD_ERRORREGISTER[11]
     *  REG_0X08_DATA_PARITY_ERROR
     */
    (TodErrors,bit(11)) ? selfCaptThr32;


    /** TOD_ERRORREGISTER[12]
     *  M_PATH_STATUS_REG_DATA_PARITY_ERROR
     */
    (TodErrors,bit(12)) ? selfCaptThr32;

    /** TOD_ERRORREGISTER[13]
     *  S_PATH_STATUS_REG_DATA_PARITY_ERROR
     */
    (TodErrors,bit(13)) ? selfCaptThr32;

    /** TOD_ERRORREGISTER[14]
     *  M_PATH_0_STEP_CHECK_ERROR
     */
    (TodErrors,bit(14)) ? analyzeStepCheckErr;

    /** TOD_ERRORREGISTER[15]
     *  M_PATH_1_STEP_CHECK_ERROR
     */
    (TodErrors,bit(15)) ? analyzeStepCheckErr;

    /** TOD_ERRORREGISTER[16]
     *  S_PATH_0_STEP_CHECK_ERROR
     */
    (TodErrors,bit(16)) ? analyzeStepCheckErr;

    /** TOD_ERRORREGISTER[17]
     *  I_PATH_STEP_CHECK_ERROR
     */
    (TodErrors,bit(17)) ? analyzeStepCheckErr;

    /** TOD_ERRORREGISTER[18]
     *  PSS HAMMING DISTANCE
     */
    (TodErrors,bit(18)) ? selfCaptThr32;

    /** TOD_ERRORREGISTER[19]
     *  MISC_RESET_REG_DATA_PARITY_ERROR
     */
    (TodErrors,bit(19)) ? selfCaptThr32;

    /** TOD_ERRORREGISTER[20]
     *  S_PATH_0_PARITY_ERROR
     */
    (TodErrors,bit(20)) ? selfCapThr32TopReConfig;

    /** TOD_ERRORREGISTER[21]
     *  S_PATH_1_STEP_CHECK_ERROR
     */
    (TodErrors,bit(21)) ? analyzeStepCheckErr;

    /** TOD_ERRORREGISTER[22]
     *  I_PATH_DELAY_STEP_CHECK_PARITY_ERROR
     */
    (TodErrors,bit(22)) ? selfCapThr32TopReConfig;

    /** TOD_ERRORREGISTER[23]
     *  REG_0X0C DATA_PARITY ERROR
     */
    (TodErrors,bit(23)) ? selfCaptThr32;

    /** TOD_ERRORREGISTER[24]
     *  REG_0X11_0X12_0X13_0X14_0X15_0X16_DATA_PARITY_ERROR
     */
    (TodErrors,bit(24)) ? selfCaptThr32;

    /** TOD_ERRORREGISTER[25]
     * REG_0X17_0X18_0X21_0X22_DATA_PARITY_ERROR
     */
    (TodErrors,bit(25)) ? selfCaptThr32;

    /** TOD_ERRORREGISTER[26]
     *  REG_0X1D_0X1E_0X1F_DATA_PARITY_ERROR
     */
    (TodErrors,bit(26)) ? selfCaptThr32;

    /** TOD_ERRORREGISTER[27]
     *  TIMER_VALUE_REG_DATA_PARITY_ERROR
     */
    (TodErrors,bit(27)) ? selfCaptThr32;

    /** TOD_ERRORREGISTER[28]
     *  LOW_ORDER_STEP_REG_DATA_PARITY_ERROR
     */
    (TodErrors,bit(28)) ? selfCaptThr32;

    /** TOD_ERRORREGISTER[29]
     *  FSM_REG_DATA_PARITY_ERROR
     */
    (TodErrors,bit(29)) ? selfCaptThr32;

    /** TOD_ERRORREGISTER[30]
     *  RX_TTYPE_CONTROL_REG_DATA_PARITY_ERROR
     */
    (TodErrors,bit(30)) ? selfCaptThr32;

    /** TOD_ERRORREGISTER[31]
     *  REG_0X30_0X31_0X32_0X33_DATA_PARITY_ERROR
     */
    (TodErrors,bit(31)) ? selfCaptThr32;

    /** TOD_ERRORREGISTER[32]
     *  CHIP_CONTROL_REG_DATA_PARITY_ERROR
     */
    (TodErrors,bit(32)) ? selfCaptThr32;

    /** TOD_ERRORREGISTER[33]
     *  I_PATH_SYNC_CHECK_ERROR
     */
    (TodErrors,bit(33)) ? selfCaptThr32;

    /** TOD_ERRORREGISTER[34]
     *  I_PATH_FSM_STATE_PARITY_ERROR
     */
    (TodErrors,bit(34)) ? selfCaptThr32;

    /** TOD_ERRORREGISTER[35]
     *  I_PATH_TIME_REG_PARITY_ERROR
     */
    (TodErrors,bit(35)) ? selfCaptThr32;

    /** TOD_ERRORREGISTER[36]
     *  I_PATH_TIME_REG_OVERFLOW
     */
    (TodErrors,bit(36)) ? maskTodError;

    /** TOD_ERRORREGISTER[37]
     *  WOF_LOW_ORDER_STEP_COUNTER_PARITY_ERROR
     */
    (TodErrors,bit(37)) ? selfCaptThr32;

    /** TOD_ERRORREGISTER[38|39|40|41|42|43]
     *  RX_TTYPE_1
     */
    (TodErrors,bit(38|39|40|41|42|43)) ? defaultMaskedError;

    #Note: For firmware all the TOD-PIB errors are informational by nature.So,
    # not doing any special analysis.
    /** TOD_ERRORREGISTER[44]
     *  PIB_SLAVE_ADDR_INVALID_ERROR
     */
    (TodErrors,bit(44)) ? selfCaptThr32;

    /** TOD_ERRORREGISTER[45]
     *  PIB_SLAVE_WRITE_INVALID_ERROR
     */
    (TodErrors,bit(45)) ? selfCaptThr32;

    /** TOD_ERRORREGISTER[46]
     *  PIB_SLAVE_READ_INVALID_ERROR
     */
    (TodErrors,bit(46)) ? selfCaptThr32;

    /** TOD_ERRORREGISTER[47]
     *  PIB_SLAVE_ADDR_PARITY_ERROR
     */
    (TodErrors,bit(47)) ? selfCaptThr32;

    /** TOD_ERRORREGISTER[48]
     *  PIB_SLAVE_DATA_PARITY_ERROR
     */
    (TodErrors,bit(48)) ? selfCaptThr32;

    /** TOD_ERRORREGISTER[49]
     *  TTYPE_CONTROL_REG_DATA_PARITY_ERROR
     */
    #Note: Based on discussion with with Hardware Team and PHYP, this error
    #shall be routed to PHYP instead of FSP
    (TodErrors,bit(49)) ? defaultMaskedError;

    /** TOD_ERRORREGISTER[50|51|52]
     *  PIB_MASTER_RSP_INFO_ERROR
     */
    #ignoring TOD-PIB errors for any special analysis.Since errors are
    #informational by nature.
    (TodErrors,bit( 50|51|52 )) ? selfCaptThr32;

    /** TOD_ERRORREGISTER[53]
     *  RX_TTYPE_INVALID_ERROR
     */
    (TodErrors,bit(53 )) ? selfCaptThr32;

    /** TOD_ERRORREGISTER[54]
     *  RX_TTYPE_4_DATA_PARITY_ERROR
     */
    (TodErrors,bit(54)) ? selfCaptThr32;

    /** TOD_ERRORREGISTER[55]
     *  PIB_MASTER_REQUEST_ERROR
     */
    (TodErrors,bit(55)) ? selfCaptThr32;

    /** TOD_ERRORREGISTER[56]
     *  PIB_RESET_DURING_PIB_ACCESS_ERROR
     */
    (TodErrors,bit(56)) ? selfCaptThr32;

    /** TOD_ERRORREGISTER[57]
     *  EXTERNAL_XSTOP_ERROR
     */
    #bit tells us that TOD has received an external check stop
    #purpose is to merely provide an information. Hence not doing any
    #analysis.
    (TodErrors,bit(57)) ? defaultMaskedError;

    #bit[58:63] not implemented
    /** TOD_ERRORREGISTER[58|59|60|61|62|63]
     *  SPARE_ERROR
     */
    (TodErrors,bit(58|59|60|61|62|63)) ? defaultMaskedError;

};


actionclass level2_M_self_L_th_32perDay
{
    callout2ndLvlMed;
    calloutSelfLowNoGard;
    threshold32pday;
};

/** Callout connected NX, threshold 32/day */
actionclass nx_th_32perDay
{
    callout(connected(TYPE_NX,0), MRU_MED);
    threshold32pday;
};

/** Callout connected NX, threshold 1 */
actionclass nx_th_1
{
    callout(connected(TYPE_NX,0), MRU_MED);
    threshold1;
};

/** Callout connected NX, threshold 1, SUE originated from somewhere else */
actionclass nx_th_1_SUE { nx_th_1; SueSeen; };

/** PLL Threshold of 2 per 5 mins */
actionclass thresholdPll
{
    threshold( field(2 / 5 min) );
};

# This action is for the case where TP_LFIR[21] comes on
# but PLL code does not isolate to any PLL errors.  The
# threshold is the same as PLL one 2 per 5 mins with
# callout/gard the chip at threshold along with PLL scom
# data captured.
/** PCB Slave Internal parity error action */
actionclass pcb_slave_internal_parity
{
    capture(PllFIRs);
    calloutSelfHigh;
    thresholdPll;
    funccall("capturePllFfdc");
    funccall("clearParityError");
};

/**
 * Threshold 32/day (field) and 1 (mnfg). Do not predictively callout on
 * threshold, instead just mask.
 */
actionclass pb_cent_hang_recovery_gte
{
    capture(PbCentMode);
    calloutSelfMed;
    threshold32pday;
    funccall("ClearServiceCallFlag_mnfgInfo");
};

actionclass deadmanTimer
{
    funccall("handleDeadmanTimer");
};

actionclass sbe_vital_attn
{
    threshold_and_mask_self;
    funccall("handleSbeVital");
};

actionclass sys_osc_switch_error { defaultMaskedError; }; # Handled in PLL code
actionclass pci_osc_switch_error { defaultMaskedError; }; # Handled in PLL code

actionclass pmRecovery
{
    funccall("PmRecovery");
    threshold1;
};

/** Callout connected XBUS 0 interface on first occurrence */
actionclass calloutBusInterface_xbus0_th_1
{
    funccall("calloutBusInterface_XBUS0");
    threshold1;
};

/** Callout connected XBUS 1 interface on first occurrence */
actionclass calloutBusInterface_xbus1_th_1
{
    funccall("calloutBusInterface_XBUS1");
    threshold1;
};

/** Callout connected XBUS 2 interface on first occurrence */
actionclass calloutBusInterface_xbus2_th_1
{
    funccall("calloutBusInterface_XBUS2");
    threshold1;
};

/** Callout connected OBUS 0 interface on first occurrence */
actionclass calloutBusInterface_obus0_th_1
{
    funccall("calloutBusInterface_OBUS0");
    threshold1;
};

/** Callout connected OBUS 1 interface on first occurrence */
actionclass calloutBusInterface_obus1_th_1
{
    funccall("calloutBusInterface_OBUS1");
    threshold1;
};

/** Callout connected OBUS 2 interface on first occurrence */
actionclass calloutBusInterface_obus2_th_1
{
    funccall("calloutBusInterface_OBUS2");
    threshold1;
};

/** Callout connected OBUS 3 interface on first occurrence */
actionclass calloutBusInterface_obus3_th_1
{
    funccall("calloutBusInterface_OBUS3");
    threshold1;
};

# TOD Actions:
#   * Capture at least this chip TOD registers.
#
#   * Threshold normal TOD errors (TOD error register) at 32/day.
#
#   * Network Errors : Step Check Fault or "PHYP Failed Topology"
#    - PHYP Failed Topology must be visible and "Request new Topology".
#        - May have PHYP failure on another chip.
#    - Capture TOD registers for whole system.
#    - Isolate both topologies and make callout.

/**
 * Analyze TOD Register.
 */
actionclass TodReportByRegister
{
    capture(TODReg);
    try(analyze(gTodErrors),TodRegisterAnalyzeFail);
};

actionclass TodRegisterAnalyzeFail
{
    self_H_th_1;
};

/**
 * PHYP Network fault.
 */
actionclass TodReportByPHYP
{
    threshold1;
    funccall("todStepCheckFault");
};

/**
 * TOD Step Check Fault - Isolate topology.
 */
actionclass analyzeStepCheckErr
{
    threshold32pday;
    funccall("todStepCheckFault");
};

/** action for tod errors which do not need any specific ananlysis */

actionclass selfCaptThr32
{
    calloutSelfHigh;
    threshold32pday;
};

/**
 *  Mask indication from PHYP due to all cores evacuated.
 *    - Mask TOD errors from this chip.
 *    - Not visible unless xstp.
 *    - Request new topology if chip is MDMT.
 */
actionclass maskTodError
{
    self_H_th_1;
    funccall("ClearServiceCallFlag");
    funccall("todNewTopologyIfBackupMDMT");
};

/** callout Proc reporting error. If threshold reaches 32 per day, request
 *  reconfiguration of topology.
 */
actionclass selfCapThr32TopReConfig
{
    selfCaptThr32;
    funccall("requestTopologySwitch");
};

/** analyzes backup topology if TOD error analysis is enabled */
actionclass analyzeTodBackupTopology
{
    try( funccall("isTodDisabled"), TodReportByRegister );
};

/** callout and gard self if TOD error analysis is enabled */
actionclass analyzePibError
{
    capture(TODReg);
    try( funccall("isTodDisabled"), self_H_th_1 );
};

/** analyzes active topology if TOD error analysis is enabled */
actionclass analyzePhypTodError
{
    try( funccall("isTodDisabled"), TodReportByPHYP );
};

/** action to analyze INT_CQ_FIR_PC_RECOV_ERROR_0_2 */
actionclass analyzeIntCqFirPcRecovError
{
    try( funccall("handleIntCqFirPcRecovError"), level2_M_self_L_th_1 );
};

/** proc targets for PBIOOFIR handling **/
actionclass obus0SmpFailure_L0
{
    funccall("captureSmpObus0");
    funccall("obus0_callout_L0");
    threshold1;
};

actionclass obus0SmpFailure_L1
{
    funccall("captureSmpObus0");
    funccall("obus0_callout_L1");
    threshold1;
};

actionclass obus1SmpFailure_L0
{
    funccall("captureSmpObus1");
    funccall("obus1_callout_L0");
    threshold1;
};

actionclass obus1SmpFailure_L1
{
    funccall("captureSmpObus1");
    funccall("obus1_callout_L1");
    threshold1;
};

actionclass obus2SmpFailure_L0
{
    funccall("captureSmpObus2");
    funccall("obus2_callout_L0");
    threshold1;
};

actionclass obus2SmpFailure_L1
{
    funccall("captureSmpObus2");
    funccall("obus2_callout_L1");
    threshold1;
};

actionclass obus3SmpFailure_L0
{
    funccall("captureSmpObus3");
    funccall("obus3_callout_L0");
    threshold1;
};

actionclass obus3SmpFailure_L1
{
    funccall("captureSmpObus3");
    funccall("obus3_callout_L1");
    threshold1;
};

actionclass obus0SmpFailure_LALL
{
    funccall("captureSmpObus0");
    funccall("obus0_callout_L0");
    funccall("obus0_callout_L1");
    threshold1;
};

actionclass obus1SmpFailure_LALL
{
    funccall("captureSmpObus1");
    funccall("obus1_callout_L0");
    funccall("obus1_callout_L1");
    threshold1;
};

actionclass obus2SmpFailure_LALL
{
    funccall("captureSmpObus2");
    funccall("obus2_callout_L0");
    funccall("obus2_callout_L1");
    threshold1;
};

actionclass obus3SmpFailure_LALL
{
    funccall("captureSmpObus3");
    funccall("obus3_callout_L0");
    funccall("obus3_callout_L1");
    threshold1;
};

###############################################################################
# Analyze groups
###############################################################################

actionclass analyzePciChipletFir0
{
    capture(PciChipletFir0);
    analyze(gPCI0_CHIPLET_FIR);
};

actionclass analyzePciChipletFir1
{
    capture(PciChipletFir1);
    analyze(gPCI1_CHIPLET_FIR);
};

actionclass analyzePciChipletFir2
{
    capture(PciChipletFir2);
    analyze(gPCI2_CHIPLET_FIR);
};

actionclass analyzeTP_LFIR     { analyze(gTP_LFIR    ); };
actionclass analyzeOCCFIR      { analyze(gOCCFIR     ); };
actionclass analyzeN0_LFIR     { analyze(gN0_LFIR    ); };
actionclass analyzeNXDMAENGFIR { analyze(gNXDMAENGFIR); };
actionclass analyzeNXCQFIR     { analyze(gNXCQFIR    ); };
actionclass analyzeNXDMAENGFIR { analyze(gNXDMAENGFIR); };
actionclass analyzeN1_LFIR     { analyze(gN1_LFIR    ); };
actionclass analyzeMCDFIR_0    { analyze(gMCDFIR_0   ); };
actionclass analyzeMCDFIR_1    { analyze(gMCDFIR_1   ); };
actionclass analyzeVASFIR      { analyze(gVASFIR     ); };
actionclass analyzeN2_LFIR     { analyze(gN2_LFIR    ); };
actionclass analyzePSIFIR      { analyze(gPSIFIR     ); };
actionclass analyzeN3_LFIR     { analyze(gN3_LFIR    ); };
actionclass analyzePBWESTFIR   { analyze(gPBWESTFIR  ); };
actionclass analyzePBCENTFIR   { analyze(gPBCENTFIR  ); };
actionclass analyzePBEASTFIR   { analyze(gPBEASTFIR  ); };
actionclass analyzeNMMUCQFIR   { analyze(gNMMUCQFIR  ); };
actionclass analyzeNMMUFIR     { analyze(gNMMUFIR    ); };
actionclass analyzePBPPEFIR    { analyze(gPBPPEFIR   ); };
actionclass analyzePBIOEFIR    { analyze(gPBIOEFIR   ); };
actionclass analyzePBIOOFIR    { analyze(gPBIOOFIR   ); };
actionclass analyzePBAFIR      { analyze(gPBAFIR     ); };
actionclass analyzePSIHBFIR    { analyze(gPSIHBFIR   ); };
actionclass analyzePBAMFIR     { analyze(gPBAMFIR    ); };
actionclass analyzeXB_LFIR     { analyze(gXB_LFIR    ); };
actionclass analyzeXBPPEFIR    { analyze(gXBPPEFIR   ); };

actionclass analyzeINTCQFIR
{
    capture(intcqfir_ffdc);
    analyze(gINTCQFIR);
};

###############################################################################
# Analyze connected
###############################################################################

actionclass analyzeConnectedEQ0   { analyze(connected(TYPE_EQ,      0)); };
actionclass analyzeConnectedEQ1   { analyze(connected(TYPE_EQ,      1)); };
actionclass analyzeConnectedEQ2   { analyze(connected(TYPE_EQ,      2)); };
actionclass analyzeConnectedEQ3   { analyze(connected(TYPE_EQ,      3)); };
actionclass analyzeConnectedEQ4   { analyze(connected(TYPE_EQ,      4)); };
actionclass analyzeConnectedEQ5   { analyze(connected(TYPE_EQ,      5)); };
actionclass analyzeConnectedEC0   { analyze(connected(TYPE_CORE,    0)); };
actionclass analyzeConnectedEC1   { analyze(connected(TYPE_CORE,    1)); };
actionclass analyzeConnectedEC2   { analyze(connected(TYPE_CORE,    2)); };
actionclass analyzeConnectedEC3   { analyze(connected(TYPE_CORE,    3)); };
actionclass analyzeConnectedEC4   { analyze(connected(TYPE_CORE,    4)); };
actionclass analyzeConnectedEC5   { analyze(connected(TYPE_CORE,    5)); };
actionclass analyzeConnectedEC6   { analyze(connected(TYPE_CORE,    6)); };
actionclass analyzeConnectedEC7   { analyze(connected(TYPE_CORE,    7)); };
actionclass analyzeConnectedEC8   { analyze(connected(TYPE_CORE,    8)); };
actionclass analyzeConnectedEC9   { analyze(connected(TYPE_CORE,    9)); };
actionclass analyzeConnectedEC10  { analyze(connected(TYPE_CORE,   10)); };
actionclass analyzeConnectedEC11  { analyze(connected(TYPE_CORE,   11)); };
actionclass analyzeConnectedEC12  { analyze(connected(TYPE_CORE,   12)); };
actionclass analyzeConnectedEC13  { analyze(connected(TYPE_CORE,   13)); };
actionclass analyzeConnectedEC14  { analyze(connected(TYPE_CORE,   14)); };
actionclass analyzeConnectedEC15  { analyze(connected(TYPE_CORE,   15)); };
actionclass analyzeConnectedEC16  { analyze(connected(TYPE_CORE,   16)); };
actionclass analyzeConnectedEC17  { analyze(connected(TYPE_CORE,   17)); };
actionclass analyzeConnectedEC18  { analyze(connected(TYPE_CORE,   18)); };
actionclass analyzeConnectedEC19  { analyze(connected(TYPE_CORE,   19)); };
actionclass analyzeConnectedEC20  { analyze(connected(TYPE_CORE,   20)); };
actionclass analyzeConnectedEC21  { analyze(connected(TYPE_CORE,   21)); };
actionclass analyzeConnectedEC22  { analyze(connected(TYPE_CORE,   22)); };
actionclass analyzeConnectedEC23  { analyze(connected(TYPE_CORE,   23)); };
actionclass analyzeConnectedCAPP0 { analyze(connected(TYPE_CAPP,    0)); };
actionclass analyzeConnectedCAPP1 { analyze(connected(TYPE_CAPP,    1)); };
actionclass analyzeConnectedOBUS0 { analyze(connected(TYPE_OBUS,    0)); };
actionclass analyzeConnectedOBUS3 { analyze(connected(TYPE_OBUS,    3)); };
actionclass analyzeConnectedXBUS1 { analyze(connected(TYPE_XBUS,    1)); };
actionclass analyzeConnectedXBUS2 { analyze(connected(TYPE_XBUS,    2)); };
actionclass analyzeConnectedPEC0  { analyze(connected(TYPE_PEC,     0)); };
actionclass analyzeConnectedPEC1  { analyze(connected(TYPE_PEC,     1)); };
actionclass analyzeConnectedPEC2  { analyze(connected(TYPE_PEC,     2)); };
actionclass analyzeConnectedPHB0  { analyze(connected(TYPE_PHB,     0)); };
actionclass analyzeConnectedPHB1  { analyze(connected(TYPE_PHB,     1)); };
actionclass analyzeConnectedPHB2  { analyze(connected(TYPE_PHB,     2)); };
actionclass analyzeConnectedPHB3  { analyze(connected(TYPE_PHB,     3)); };
actionclass analyzeConnectedPHB4  { analyze(connected(TYPE_PHB,     4)); };
actionclass analyzeConnectedPHB5  { analyze(connected(TYPE_PHB,     5)); };