blob: 47dd33fd9e8800d8b157022975d9809d44bdeffc (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
|
# IBM_PROLOG_BEGIN_TAG
# This is an automatically generated prolog.
#
# $Source: src/usr/diag/prdf/common/plat/cumulus/cumulus_dmi_regs.rule $
#
# OpenPOWER HostBoot Project
#
# Contributors Listed Below - COPYRIGHT 2017,2018
# [+] International Business Machines Corp.
#
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
# You may obtain a copy of the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS,
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
# implied. See the License for the specific language governing
# permissions and limitations under the License.
#
# IBM_PROLOG_END_TAG
############################################################################
# Additional regs for P9 DMI target CHIFIR
############################################################################
register CHIFIR_AND
{
name "P9 DMI target CHIFIR atomic AND";
scomaddr 0x07010901;
capture group never;
access write_only;
};
register CHIFIR_OR
{
name "P9 DMI target CHIFIR atomic OR";
scomaddr 0x07010902;
capture group never;
access write_only;
};
register CHIFIR_MASK_OR
{
name "P9 DMI target CHIFIR_MASK atomic OR";
scomaddr 0x07010905;
capture group never;
access write_only;
};
register MCICFG0
{
name "MCI Configuration Register 0";
scomaddr 0x0701090A;
capture group default;
};
register MCISTAT
{
name "MCI Status Register";
scomaddr 0x0701090B;
capture group default;
};
register MCICRCSYN
{
name "MCI CRC Syndromes Register";
scomaddr 0x0701090C;
capture group default;
};
register MCIERRINJ
{
name "MCI Error Inject Register";
scomaddr 0x0701090D;
capture group default;
};
register MCICFG1
{
name "MCI Configuration Register 1";
scomaddr 0x0701090E;
capture group default;
};
register RECR
{
name "Read ECC Control Register";
scomaddr 0x07010914;
capture group default;
};
register EICR
{
name "Error Inject Control Register";
scomaddr 0x07010918;
capture group default;
};
register CERR0
{
name "Error detail register 0";
scomaddr 0x07010919;
capture group default;
};
register CERR1
{
name "Error detail register 1";
scomaddr 0x0701091A;
capture group default;
};
############################################################################
# Non-existent Registers for Capture
############################################################################
register VPD_FAILED_LANES_0TO63
{
name "Bit map 0-63 of failed lanes read from VPD";
scomaddr 0xFFFF0001;
access no_access;
capture group never;
};
register VPD_FAILED_LANES_64TO127
{
name "Bit map 64-127 of failed lanes read from VPD";
scomaddr 0xFFFF0002;
access no_access;
capture group never;
};
register ALL_FAILED_LANES_0TO63
{
name "Bit map 0-63 of failed lanes from io_read_erepair";
scomaddr 0xFFFF0003;
access no_access;
capture group never;
};
register ALL_FAILED_LANES_64TO127
{
name "Bit map 64-127 of failed lanes from io_read_erepair";
scomaddr 0xFFFF0004;
access no_access;
capture group never;
};
|
