path: root/src/usr/diag/prdf/common/plat/axone/axone_npu.rule

# IBM_PROLOG_BEGIN_TAG
# This is an automatically generated prolog.
#
# $Source: src/usr/diag/prdf/common/plat/axone/axone_npu.rule $
#
# OpenPOWER HostBoot Project
#
# Contributors Listed Below - COPYRIGHT 2018,2019
# [+] International Business Machines Corp.
#
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
# You may obtain a copy of the License at
#
#     http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS,
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
# implied. See the License for the specific language governing
# permissions and limitations under the License.
#
# IBM_PROLOG_END_TAG

chip axone_npu
{
    name        "AXONE NPU target";
    targettype  TYPE_NPU;
    sigoff      0x0000;
    dump        DUMP_CONTENT_HW;
    scomlen     64;

 #############################################################################
 #                                                                           #
 #  ######                                                                   #
 #  #     #  ######   ####     ###    ####    #####  ######  #####    ####   #
 #  #     #  #       #    #     #    #          #    #       #    #  #       #
 #  ######   #####   #          #     ####      #    #####   #    #   ####   #
 #  #   #    #       #  ###     #         #     #    #       #####        #  #
 #  #    #   #       #    #     #    #    #     #    #       #   #   #    #  #
 #  #     #  ######   ####     ###    ####      #    ######  #    #   ####   #
 #                                                                           #
 #############################################################################

    ############################################################################
    # P9 NPU target NPU0FIR
    ############################################################################

    register NPU0FIR
    {
        name        "P9 NPU target NPU0FIR";
        scomaddr    0x05013c00;
        reset       (&, 0x05013c01);
        mask        (|, 0x05013c05);
        capture     group npu0fir_ffdc;
    };

    register NPU0FIR_MASK
    {
        name        "P9 NPU target NPU0FIR MASK";
        scomaddr    0x05013c03;
        capture     group npu0fir_ffdc;
    };

    register NPU0FIR_ACT0
    {
        name        "P9 NPU target NPU0FIR ACT0";
        scomaddr    0x05013c06;
        capture     group npu0fir_ffdc;
        capture     req nonzero("NPU0FIR");
    };

    register NPU0FIR_ACT1
    {
        name        "P9 NPU target NPU0FIR ACT1";
        scomaddr    0x05013c07;
        capture     group npu0fir_ffdc;
        capture     req nonzero("NPU0FIR");
    };

    ############################################################################
    # P9 NPU target NPU1FIR
    ############################################################################

    register NPU1FIR
    {
        name        "P9 NPU target NPU1FIR";
        scomaddr    0x05013c40;
        reset       (&, 0x05013c41);
        mask        (|, 0x05013c45);
        capture     group npu1fir_ffdc;
    };

    register NPU1FIR_MASK
    {
        name        "P9 NPU target NPU1FIR MASK";
        scomaddr    0x05013c43;
        capture     group npu1fir_ffdc;
    };

    register NPU1FIR_ACT0
    {
        name        "P9 NPU target NPU1FIR ACT0";
        scomaddr    0x05013c46;
        capture     group npu1fir_ffdc;
        capture     req nonzero("NPU1FIR");
    };

    register NPU1FIR_ACT1
    {
        name        "P9 NPU target NPU1FIR ACT1";
        scomaddr    0x05013c47;
        capture     group npu1fir_ffdc;
        capture     req nonzero("NPU1FIR");
    };

    ############################################################################
    # P9 NPU target NPU2FIR
    ############################################################################

    register NPU2FIR
    {
        name        "P9 NPU target NPU2FIR";
        scomaddr    0x05013c80;
        reset       (&, 0x05013c81);
        mask        (|, 0x05013c85);
        capture     group npu2fir_ffdc;
    };

    register NPU2FIR_MASK
    {
        name        "P9 NPU target NPU2FIR MASK";
        scomaddr    0x05013c83;
        capture     group npu2fir_ffdc;
    };

    register NPU2FIR_ACT0
    {
        name        "P9 NPU target NPU2FIR ACT0";
        scomaddr    0x05013c86;
        capture     group npu2fir_ffdc;
        capture     req nonzero("NPU2FIR");
    };

    register NPU2FIR_ACT1
    {
        name        "P9 NPU target NPU2FIR ACT1";
        scomaddr    0x05013c87;
        capture     group npu2fir_ffdc;
        capture     req nonzero("NPU2FIR");
    };

# Include registers not defined by the xml
.include "p9_common_npu_regs.rule";

};

 ##############################################################################
 #                                                                            #
 # ####                                 #                                     #
 # #   # #   # #    #####  ###      #  # #    ##  ##### ###  ###  #   #  ###  #
 # #   # #   # #    #     #        #  #   #  #  #   #    #  #   # ##  # #     #
 # ####  #   # #    ####   ###    #  ####### #      #    #  #   # # # #  ###  #
 # #  #  #   # #    #         #  #   #     # #  #   #    #  #   # #  ##     # #
 # #   #  ###  #### #####  ###  #    #     #  ##    #   ###  ###  #   #  ###  #
 #                                                                            #
 ##############################################################################

################################################################################
# Summary for NPU
################################################################################

rule rNPU
{
  CHECK_STOP:
    summary( 0, rNPU0FIR ) |
    summary( 1, rNPU1FIR ) |
    summary( 2, rNPU2FIR );

  RECOVERABLE:
    summary( 0, rNPU0FIR ) |
    summary( 1, rNPU1FIR ) |
    summary( 2, rNPU2FIR );

  UNIT_CS:
    summary( 0, rNPU0FIR ) |
    summary( 1, rNPU1FIR ) |
    summary( 2, rNPU2FIR );

};

group gNPU attntype CHECK_STOP, RECOVERABLE, UNIT_CS
    filter singlebit
{
    (rNPU, bit(0)) ? analyzeNPU0FIR;
    (rNPU, bit(1)) ? analyzeNPU1FIR;
    (rNPU, bit(2)) ? analyzeNPU2FIR;
};

################################################################################
# P9 NPU target NPU0FIR
################################################################################

rule rNPU0FIR
{
  CHECK_STOP:
    NPU0FIR & ~NPU0FIR_MASK & ~NPU0FIR_ACT0 & ~NPU0FIR_ACT1;
  RECOVERABLE:
    NPU0FIR & ~NPU0FIR_MASK & ~NPU0FIR_ACT0 &  NPU0FIR_ACT1;
  UNIT_CS:
    NPU0FIR & ~NPU0FIR_MASK &  NPU0FIR_ACT0 &  NPU0FIR_ACT1;
};

group gNPU0FIR
    filter singlebit,
           cs_root_cause(1,2,3,4,5,6,7,9,10,16,18,19,25,29,31,40,42,44,45)
{
    /** NPU0FIR[0]
     *  NTL array CE
     */
    (rNPU0FIR, bit(0)) ? self_th_32perDay;

    /** NPU0FIR[1]
     *  NTL header array UE
     */
    (rNPU0FIR, bit(1)) ? self_th_1;

    /** NPU0FIR[2]
     *  NTL Data Array UE
     */
    (rNPU0FIR, bit(2)) ? self_th_1;

    /** NPU0FIR[3]
     *  NTL NVLInk Control/Header/AE PE
     */
    (rNPU0FIR, bit(3)) ? self_th_1;

    /** NPU0FIR[4]
     *  NTL NVLink Data Parity error
     */
    (rNPU0FIR, bit(4)) ? self_th_1;

    /** NPU0FIR[5]
     *  NTL NVLink Malformed Packet
     */
    (rNPU0FIR, bit(5)) ? self_th_1;

    /** NPU0FIR[6]
     *  NTL NVLink Unsupported Packet
     */
    (rNPU0FIR, bit(6)) ? self_th_1;

    /** NPU0FIR[7]
     *  NTL NVLink Config errors
     */
    (rNPU0FIR, bit(7)) ? self_th_1;

    /** NPU0FIR[8]
     *  NTL NVLink CRC errors or LMD=Stomp
     */
    (rNPU0FIR, bit(8)) ? defaultMaskedError;

    /** NPU0FIR[9]
     *  NTL PRI errors
     */
    (rNPU0FIR, bit(9)) ? self_th_1;

    /** NPU0FIR[10]
     *  NTL logic error
     */
    (rNPU0FIR, bit(10)) ? self_th_1;

    /** NPU0FIR[11]
     *  NTL LMD=Data Posion
     */
    (rNPU0FIR, bit(11)) ? defaultMaskedError;

    /** NPU0FIR[12]
     *  NTL data array SUE
     */
    (rNPU0FIR, bit(12)) ? defaultMaskedError;

    /** NPU0FIR[13]
     *  CQ CTL/SM ASBE Array single-bit CE
     */
    (rNPU0FIR, bit(13)) ? self_th_32perDay;

    /** NPU0FIR[14]
     *  CQ CTL/SM PBR PowerBus Recoverable err
     */
    (rNPU0FIR, bit(14)) ? defaultMaskedError;

    /** NPU0FIR[15]
     *  CQ CTL/SM REG Register ring error
     */
    (rNPU0FIR, bit(15)) ? self_th_32perDay;

    /** NPU0FIR[16]
     *  Data UE for MMIO store data
     */
    (rNPU0FIR, bit(16)) ? self_th_1;

    /** NPU0FIR[17]
     *  spare
     */
    (rNPU0FIR, bit(17)) ? defaultMaskedError;

    /** NPU0FIR[18]
     *  CQ CTL/SM NCF NVLink config error
     */
    (rNPU0FIR, bit(18)) ? self_th_1;

    /** NPU0FIR[19]
     *  CQ CTL/SM NVF NVLink fatal error
     */
    (rNPU0FIR, bit(19)) ? self_th_1;

    /** NPU0FIR[20]
     *  spare
     */
    (rNPU0FIR, bit(20)) ? defaultMaskedError;

    /** NPU0FIR[21]
     *  CQ CTL/SM AUE Array UE
     */
    (rNPU0FIR, bit(21)) ? self_th_1;

    /** NPU0FIR[22]
     *  CQ CTL/SM PBP PowerBus parity error
     */
    (rNPU0FIR, bit(22)) ? self_th_1;

    /** NPU0FIR[23]
     *  CQ CTL/SM PBF PowerBus Fatal Error
     */
    (rNPU0FIR, bit(23)) ? self_M_level2_L_th_1;

    /** NPU0FIR[24]
     *  PowerBus configuration error
     */
    (rNPU0FIR, bit(24)) ? level2_M_self_L_th_1;

    /** NPU0FIR[25]
     *  CQ CTL/SM FWD Forward-Progress error
     */
    (rNPU0FIR, bit(25)) ? self_th_1;

    /** NPU0FIR[26]
     *  CQ CTL/SM NLG NPU Logic error
     */
    (rNPU0FIR, bit(26)) ? self_th_1;

    /** NPU0FIR[27]
     *  Invalid access to secure memory attempted
     */
    (rNPU0FIR, bit(27)) ? self_th_1;

    /** NPU0FIR[28]
     *  spare
     */
    (rNPU0FIR, bit(28)) ? defaultMaskedError;

    /** NPU0FIR[29]
     *  CQ DAT ECC UE/SUE on data/BE arrays
     */
    (rNPU0FIR, bit(29)) ? self_th_1;

    /** NPU0FIR[30]
     *  CQ DAT ECC CE on data/BE arrays
     */
    (rNPU0FIR, bit(30)) ? self_M_level2_L_th_32perDay;

    /** NPU0FIR[31]
     *  CQ DAT parity error on data/BE latches
     */
    (rNPU0FIR, bit(31)) ? self_th_1;

    /** NPU0FIR[32]
     *  CQ DAT parity errs on config regs
     */
    (rNPU0FIR, bit(32)) ? self_th_1;

    /** NPU0FIR[33]
     *  CQ DAT parity errs/PowerBus rtag
     */
    (rNPU0FIR, bit(33)) ? self_th_1;

    /** NPU0FIR[34]
     *  CQ DAT parity errs nternal state latches
     */
    (rNPU0FIR, bit(34)) ? self_th_1;

    /** NPU0FIR[35]
     *  CQ DAT logic error
     */
    (rNPU0FIR, bit(35)) ? self_th_1;

    /** NPU0FIR[36]
     *  Future SUE
     */
    (rNPU0FIR, bit(36)) ? defaultMaskedError;

    /** NPU0FIR[37]
     *  ECC SUE on PB received data
     */
    (rNPU0FIR, bit(37)) ? defaultMaskedError;

    /** NPU0FIR[38:39]
     *  spare
     */
    (rNPU0FIR, bit(38|39)) ? defaultMaskedError;

    /** NPU0FIR[40]
     *  XTS internal logic error
     */
    (rNPU0FIR, bit(40)) ? self_th_1;

    /** NPU0FIR[41]
     *  XTS correctable errs in XTS SRAM
     */
    (rNPU0FIR, bit(41)) ? self_M_level2_L_th_32perDay;

    /** NPU0FIR[42]
     *  XTS Ues in XTS internal SRAM
     */
    (rNPU0FIR, bit(42)) ? self_th_1;

    /** NPU0FIR[43]
     *  XTS CE on incoming stack transactions
     */
    (rNPU0FIR, bit(43)) ? self_M_level2_L_th_32perDay;

    /** NPU0FIR[44]
     *  XTS  errs incoming stack transaction
     */
    (rNPU0FIR, bit(44)) ? self_th_1;

    /** NPU0FIR[45]
     *  XTS errs on incoming PBUS transaction
     */
    (rNPU0FIR, bit(45)) ? self_th_1;

    /** NPU0FIR[46]
     *  XTS Translate Request Fail
     */
    (rNPU0FIR, bit(46)) ? defaultMaskedError;

    /** NPU0FIR[47:59]
     *  spare
     */
    (rNPU0FIR, bit(47|48|49|50|51|52|53|54|55|56|57|58|59)) ? defaultMaskedError;

    /** NPU0FIR[60]
     *  MISC Pervasive SCOM satellite err
     */
    (rNPU0FIR, bit(60)) ? defaultMaskedError;

    /** NPU0FIR[61]
     *  MISC Pervasive SCOM satellite err
     */
    (rNPU0FIR, bit(61)) ? defaultMaskedError;

    /** NPU0FIR[62]
     *  Local FIR Parity Error RAS duplicate
     */
    (rNPU0FIR, bit(62)) ? defaultMaskedError;

    /** NPU0FIR[63]
     *  Local FIR Parity Err
     */
    (rNPU0FIR, bit(63)) ? defaultMaskedError;

};

################################################################################
# P9 NPU target NPU1FIR
################################################################################

rule rNPU1FIR
{
  CHECK_STOP:
    NPU1FIR & ~NPU1FIR_MASK & ~NPU1FIR_ACT0 & ~NPU1FIR_ACT1;
  RECOVERABLE:
    NPU1FIR & ~NPU1FIR_MASK & ~NPU1FIR_ACT0 &  NPU1FIR_ACT1;
  UNIT_CS:
    NPU1FIR & ~NPU1FIR_MASK &  NPU1FIR_ACT0 &  NPU1FIR_ACT1;
};

group gNPU1FIR
    filter singlebit,
           cs_root_cause(0,2,4,6,8,10,13,14,15,20,22,25,27,29,31,32,33,34,35,37,39,40,41,42,47,49,51,53,55,57)
{
    /** NPU1FIR[0]
     *  NDL Brick0 stall
     */
    (rNPU1FIR, bit(0)) ? self_th_1;

    /** NPU1FIR[1]
     *  NDL Brick0 nostall
     */
    (rNPU1FIR, bit(1)) ? defaultMaskedError;

    /** NPU1FIR[2]
     *  NDL Brick1 stall
     */
    (rNPU1FIR, bit(2)) ? self_th_1;

    /** NPU1FIR[3]
     *  NDL Brick1 nostall
     */
    (rNPU1FIR, bit(3)) ? defaultMaskedError;

    /** NPU1FIR[4]
     *  NDL Brick2 stall
     */
    (rNPU1FIR, bit(4)) ? self_th_1;

    /** NPU1FIR[5]
     *  NDL Brick2 nostall
     */
    (rNPU1FIR, bit(5)) ? defaultMaskedError;

    /** NPU1FIR[6]
     *  NDL Brick3 stall
     */
    (rNPU1FIR, bit(6)) ? self_th_1;

    /** NPU1FIR[7]
     *  NDL Brick3 nostall
     */
    (rNPU1FIR, bit(7)) ? defaultMaskedError;

    /** NPU1FIR[8]
     *  NDL Brick4 stall
     */
    (rNPU1FIR, bit(8)) ? self_th_1;

    /** NPU1FIR[9]
     *  NDL Brick4 nostall
     */
    (rNPU1FIR, bit(9)) ? defaultMaskedError;

    /** NPU1FIR[10]
     *  NDL Brick5 stall
     */
    (rNPU1FIR, bit(10)) ? self_th_1;

    /** NPU1FIR[11]
     *  NDL Brick5 nostall
     */
    (rNPU1FIR, bit(11)) ? defaultMaskedError;

    /** NPU1FIR[12]
     *  MISC Register ring error (ie noack)
     */
    (rNPU1FIR, bit(12)) ? self_th_32perDay;

    /** NPU1FIR[13]
     *  MISC Parity error on MISC Cntrl reg
     */
    (rNPU1FIR, bit(13)) ? self_th_1;

    /** NPU1FIR[14]
     *  MISC Parity error on SCOM D/A addr reg
     */
    (rNPU1FIR, bit(14)) ? self_th_1;

    /** NPU1FIR[15]
     *  MISC Parity error on MISC Cntrl reg
     */
    (rNPU1FIR, bit(15)) ? self_th_1;

    /** NPU1FIR[16]
     *  Reserved
     */
    (rNPU1FIR, bit(16)) ? defaultMaskedError;

    /** NPU1FIR[17]
     *  ATS Invalid TVT entry
     */
    (rNPU1FIR, bit(17)) ? defaultMaskedError;

    /** NPU1FIR[18]
     *  ATS TVT Address range error
     */
    (rNPU1FIR, bit(18)) ? defaultMaskedError;

    /** NPU1FIR[19]
     *  ATS TCE Page access error
     */
    (rNPU1FIR, bit(19)) ? defaultMaskedError;

    /** NPU1FIR[20]
     *  ATS Effective Address hit multiple TCE
     */
    (rNPU1FIR, bit(20)) ? self_th_1;

    /** NPU1FIR[21]
     *  ATS TCE Page access error
     */
    (rNPU1FIR, bit(21)) ? defaultMaskedError;

    /** NPU1FIR[22]
     *  ATS Timeout on TCE tree walk
     */
    (rNPU1FIR, bit(22)) ? self_th_1;

    /** NPU1FIR[23]
     *  ATS Parity error on TCE cache dir array
     */
    (rNPU1FIR, bit(23)) ? self_th_32perDay;

    /** NPU1FIR[24]
     *  ATS Parity error on TCE cache data array
     */
    (rNPU1FIR, bit(24)) ? self_th_32perDay;

    /** NPU1FIR[25]
     *  ATS ECC UE on Effective Address array
     */
    (rNPU1FIR, bit(25)) ? self_th_1;

    /** NPU1FIR[26]
     *  ATS ECC CE on Effective Address array
     */
    (rNPU1FIR, bit(26)) ? self_th_32perDay;

    /** NPU1FIR[27]
     *  ATS ECC UE on TDRmem array
     */
    (rNPU1FIR, bit(27)) ? self_th_1;

    /** NPU1FIR[28]
     *  ATS ECC CE on TDRmem array
     */
    (rNPU1FIR, bit(28)) ? self_th_32perDay;

    /** NPU1FIR[29]
     *  ATS ECC UE on CQ CTL DMA Read
     */
    (rNPU1FIR, bit(29)) ? self_th_1;

    /** NPU1FIR[30]
     *  ATS ECC CE on CQ CTL DMA Read
     */
    (rNPU1FIR, bit(30)) ? self_th_32perDay;

    /** NPU1FIR[31]
     *  ATS Parity error on TVT entry
     */
    (rNPU1FIR, bit(31)) ? self_th_1;

    /** NPU1FIR[32]
     *  ATS Parity err on IODA Address Reg
     */
    (rNPU1FIR, bit(32)) ? self_th_1;

    /** NPU1FIR[33]
     *  ATS Parity error on ATS Control Register
     */
    (rNPU1FIR, bit(33)) ? self_th_1;

    /** NPU1FIR[34]
     *  ATS Parity error on ATS reg
     */
    (rNPU1FIR, bit(34)) ? self_th_1;

    /** NPU1FIR[35]
     *  ATS Invalid IODA Table Select entry
     */
    (rNPU1FIR, bit(35)) ? self_th_1;

    /** NPU1FIR[36]
     *  Reserved
     */
    (rNPU1FIR, bit(36)) ? defaultMaskedError;

    /** NPU1FIR[37]
     *  Kill xlate epoch timeout
     */
    (rNPU1FIR, bit(37)) ? self_th_1;

    /** NPU1FIR[38]
     *  PEE secure SMF not secure
     */
    (rNPU1FIR, bit(38)) ? defaultMaskedError;

    /** NPU1FIR[39]
     *  XSL in suspend mode when OTL sends cmd
     */
    (rNPU1FIR, bit(39)) ? self_th_1;

    /** NPU1FIR[40]
     *  Unsupported page size
     */
    (rNPU1FIR, bit(40)) ? self_th_1;

    /** NPU1FIR[41]
     *  Unexpected XLATE release
     */
    (rNPU1FIR, bit(41)) ? self_th_1;

    /** NPU1FIR[42]
     *  Kill XLATE done fail
     */
    (rNPU1FIR, bit(42)) ? self_th_1;

    /** NPU1FIR[43:46]
     *  Reserved
     */
    (rNPU1FIR, bit(43|44|45|46)) ? defaultMaskedError;

    /** NPU1FIR[47]
     *  NDL Brick6 stall
     */
    (rNPU1FIR, bit(47)) ? self_th_1;

    /** NPU1FIR[48]
     *  NDL Brick6 nostall
     */
    (rNPU1FIR, bit(48)) ? defaultMaskedError;

    /** NPU1FIR[49]
     *  NDL Brick7 stall
     */
    (rNPU1FIR, bit(49)) ? self_th_1;

    /** NPU1FIR[50]
     *  NDL Brick7 nostall
     */
    (rNPU1FIR, bit(50)) ? defaultMaskedError;

    /** NPU1FIR[51]
     *  NDL Brick8 stall
     */
    (rNPU1FIR, bit(51)) ? self_th_1;

    /** NPU1FIR[52]
     *  NDL Brick8 nostall
     */
    (rNPU1FIR, bit(52)) ? defaultMaskedError;

    /** NPU1FIR[53]
     *  NDL Brick9 stall
     */
    (rNPU1FIR, bit(53)) ? self_th_1;

    /** NPU1FIR[54]
     *  NDL Brick9 nostall
     */
    (rNPU1FIR, bit(54)) ? defaultMaskedError;

    /** NPU1FIR[55]
     *  NDL Brick10 stall
     */
    (rNPU1FIR, bit(55)) ? self_th_1;

    /** NPU1FIR[56]
     *  NDL Brick10 nostall
     */
    (rNPU1FIR, bit(56)) ? defaultMaskedError;

    /** NPU1FIR[57]
     *  NDL Brick11 stall
     */
    (rNPU1FIR, bit(57)) ? self_th_1;

    /** NPU1FIR[58]
     *  NDL Brick11 nostall
     */
    (rNPU1FIR, bit(58)) ? defaultMaskedError;

    /** NPU1FIR[59]
     *  Reserved
     */
    (rNPU1FIR, bit(59)) ? defaultMaskedError;

    /** NPU1FIR[60]
     *  Misc SCOM ring 0 sat 0 signalled internal FSM error
     */
    (rNPU1FIR, bit(60)) ? defaultMaskedError;

    /** NPU1FIR[61]
     *  Misc SCOM ring 0 sat 1 signalled internal FSM error
     */
    (rNPU1FIR, bit(61)) ? defaultMaskedError;

    /** NPU1FIR[62]
     *  scom error
     */
    (rNPU1FIR, bit(62)) ? defaultMaskedError;

    /** NPU1FIR[63]
     *  scom error
     */
    (rNPU1FIR, bit(63)) ? defaultMaskedError;

};

################################################################################
# P9 NPU target NPU2FIR
################################################################################

rule rNPU2FIR
{
  CHECK_STOP:
    NPU2FIR & ~NPU2FIR_MASK & ~NPU2FIR_ACT0 & ~NPU2FIR_ACT1;
  RECOVERABLE:
    NPU2FIR & ~NPU2FIR_MASK & ~NPU2FIR_ACT0 &  NPU2FIR_ACT1;
  UNIT_CS:
    NPU2FIR & ~NPU2FIR_MASK &  NPU2FIR_ACT0 &  NPU2FIR_ACT1;
};

group gNPU2FIR
    filter singlebit,
           cs_root_cause(4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,20,21,22,23,24,25,26,27,28,29,30,31,36,37,38,39,40,41,42,43,45,47,48,50,51,52)
{
    /** NPU2FIR[0]
     *  OTL Brick2 translation fault
     */
    (rNPU2FIR, bit(0)) ? defaultMaskedError;

    /** NPU2FIR[1]
     *  OTL Brick3 translation fault
     */
    (rNPU2FIR, bit(1)) ? defaultMaskedError;

    /** NPU2FIR[2]
     *  OTL Brick4 translation fault
     */
    (rNPU2FIR, bit(2)) ? defaultMaskedError;

    /** NPU2FIR[3]
     *  OTL Brick5 translation fault
     */
    (rNPU2FIR, bit(3)) ? defaultMaskedError;

    /** NPU2FIR[4]
     *  OTL TL credit ctr overflow
     */
    (rNPU2FIR, bit(4)) ? self_th_1;

    /** NPU2FIR[5]
     *  OTL RX acTag invalid
     */
    (rNPU2FIR, bit(5)) ? self_th_1;

    /** NPU2FIR[6]
     *  OTL RX acTag points to an invalid entry.
     */
    (rNPU2FIR, bit(6)) ? self_th_1;

    /** NPU2FIR[7]
     *  OTL RX reserved opcode used.
     */
    (rNPU2FIR, bit(7)) ? self_th_1;

    /** NPU2FIR[8]
     *  OTL RX rtn_tl_credit cmd outside slot0.
     */
    (rNPU2FIR, bit(8)) ? self_th_1;

    /** NPU2FIR[9]
     *  OTL RX bad opcode and template combo
     */
    (rNPU2FIR, bit(9)) ? self_th_1;

    /** NPU2FIR[10]
     *  OTL RX unsupported template format.
     */
    (rNPU2FIR, bit(10)) ? self_th_1;

    /** NPU2FIR[11]
     *  OTL RX bad template x00 format.
     */
    (rNPU2FIR, bit(11)) ? self_th_1;

    /** NPU2FIR[12]
     *  OTL RX control flit overrun.
     */
    (rNPU2FIR, bit(12)) ? self_th_1;

    /** NPU2FIR[13]
     *  OTL RX unexpected data flit.
     */
    (rNPU2FIR, bit(13)) ? self_th_1;

    /** NPU2FIR[14]
     *  OTL RX DL link down.
     */
    (rNPU2FIR, bit(14)) ? self_th_1;

    /** NPU2FIR[15]
     *  OTL RX bad data received on command.
     */
    (rNPU2FIR, bit(15)) ? self_th_1;

    /** NPU2FIR[16]
     *  OTL RX bad data received on response.
     */
    (rNPU2FIR, bit(16)) ? self_th_1;

    /** NPU2FIR[17]
     *  OTL RX AP response not allowed
     */
    (rNPU2FIR, bit(17)) ? self_th_1;

    /** NPU2FIR[18]
     *  OR of all OTL parity errors.
     */
    (rNPU2FIR, bit(18)) ? self_th_1;

    /** NPU2FIR[19]
     *  OR of all OTL ECC CE errors.
     */
    (rNPU2FIR, bit(19)) ? self_th_32perDay;

    /** NPU2FIR[20]
     *  OR of all OTL ECC UE errors.
     */
    (rNPU2FIR, bit(20)) ? self_th_1;

    /** NPU2FIR[21]
     *  RXO OP Errors.
     */
    (rNPU2FIR, bit(21)) ? self_th_1;

    /** NPU2FIR[22]
     *  RXO Internal Errors.
     */
    (rNPU2FIR, bit(22)) ? self_th_1;

    /** NPU2FIR[23]
     *  OTL RXI fifo overrun.
     */
    (rNPU2FIR, bit(23)) ? self_th_1;

    /** NPU2FIR[24]
     *  OTL RXI ctrl flit data run len invalid.
     */
    (rNPU2FIR, bit(24)) ? self_th_1;

    /** NPU2FIR[25]
     *  OTL RXI opcode specifies dL=0b00.
     */
    (rNPU2FIR, bit(25)) ? self_th_1;

    /** NPU2FIR[26]
     *  OTL RXI bad data received vc2
     */
    (rNPU2FIR, bit(26)) ? self_th_1;

    /** NPU2FIR[27]
     *  OTL RXI dcp2 fifo overrun
     */
    (rNPU2FIR, bit(27)) ? self_th_1;

    /** NPU2FIR[28]
     *  OTL RXI vc1 fifo overrun
     */
    (rNPU2FIR, bit(28)) ? self_th_1;

    /** NPU2FIR[29]
     *  OTL RXI vc2 fifo overrun
     */
    (rNPU2FIR, bit(29)) ? self_th_1;

    /** NPU2FIR[30]
     *  OTL RXI Data link not supported
     */
    (rNPU2FIR, bit(30)) ? self_th_1;

    /** NPU2FIR[31]
     *  OTL TXI opcode error
     */
    (rNPU2FIR, bit(31)) ? self_th_1;

    /** NPU2FIR[32]
     *  OTL RXI reserved field not equal to 0
     */
    (rNPU2FIR, bit(32)) ? defaultMaskedError;

    /** NPU2FIR[33:35]
     *  Reserved
     */
    (rNPU2FIR, bit(33|34|35)) ? defaultMaskedError;

    /** NPU2FIR[36]
     *  MMIO invalidate while one in progress.
     */
    (rNPU2FIR, bit(36)) ? self_th_1;

    /** NPU2FIR[37]
     *  Unexpected ITAG on itag completion pt 0
     */
    (rNPU2FIR, bit(37)) ? self_th_1;

    /** NPU2FIR[38]
     *  Unexpected ITAG on itag completion pt 1
     */
    (rNPU2FIR, bit(38)) ? self_th_1;

    /** NPU2FIR[39]
     *  Unexpected Read PEE completion.
     */
    (rNPU2FIR, bit(39)) ? self_th_1;

    /** NPU2FIR[40]
     *  Unexpected Checkout response.
     */
    (rNPU2FIR, bit(40)) ? self_th_1;

    /** NPU2FIR[41]
     *  Translation request but SPAP is invalid.
     */
    (rNPU2FIR, bit(41)) ? self_th_1;

    /** NPU2FIR[42]
     *  Read a PEE which was not valid.
     */
    (rNPU2FIR, bit(42)) ? self_th_1;

    /** NPU2FIR[43]
     *  Bloom filter protection error.
     */
    (rNPU2FIR, bit(43)) ? self_th_1;

    /** NPU2FIR[44]
     *  Translation request to non-valid TA
     */
    (rNPU2FIR, bit(44)) ? defaultMaskedError;

    /** NPU2FIR[45]
     *  TA translation request to an invalid TA
     */
    (rNPU2FIR, bit(45)) ? self_th_1;

    /** NPU2FIR[46]
     *  correctable array error (SBE).
     */
    (rNPU2FIR, bit(46)) ? self_th_32perDay;

    /** NPU2FIR[47]
     *  array error (UE or parity).
     */
    (rNPU2FIR, bit(47)) ? self_th_1;

    /** NPU2FIR[48]
     *  S/TLBI buffer overflow.
     */
    (rNPU2FIR, bit(48)) ? self_th_1;

    /** NPU2FIR[49]
     *  SBE CE on Pb cout rsp or PEE read data.
     */
    (rNPU2FIR, bit(49)) ? self_th_32perDay;

    /** NPU2FIR[50]
     *  UE on Pb cut rsp or PEE read data.
     */
    (rNPU2FIR, bit(50)) ? self_th_1;

    /** NPU2FIR[51]
     *  SUE on Pb chkout rsp or Pb PEE rd data.
     */
    (rNPU2FIR, bit(51)) ? self_th_1;

    /** NPU2FIR[52]
     *  PA mem hit when bar mode is nonzero
     */
    (rNPU2FIR, bit(52)) ? self_th_1;

    /** NPU2FIR[53]
     *  XSL Reserved, macro bit 17.
     */
    (rNPU2FIR, bit(53)) ? defaultMaskedError;

    /** NPU2FIR[54]
     *  OTL Brick0 translation fault
     */
    (rNPU2FIR, bit(54)) ? defaultMaskedError;

    /** NPU2FIR[55]
     *  OTL Brick1 translation fault
     */
    (rNPU2FIR, bit(55)) ? defaultMaskedError;

    /** NPU2FIR[56:61]
     *  Reserved
     */
    (rNPU2FIR, bit(56|57|58|59|60|61)) ? defaultMaskedError;

    /** NPU2FIR[62]
     *  Local FIR PE RAS dup (ring 2, sat 2)
     */
    (rNPU2FIR, bit(62)) ? defaultMaskedError;

    /** NPU2FIR[63]
     *  Lcl PE ACTION/MASK regs (ring 2, sat 2)
     */
    (rNPU2FIR, bit(63)) ? defaultMaskedError;

};

 ##############################################################################
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# Include the actions defined for this target
.include "p9_common_actions.rule";
.include "p9_common_npu_actions.rule";