1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
|
/* IBM_PROLOG_BEGIN_TAG */
/* This is an automatically generated prolog. */
/* */
/* $Source: src/usr/diag/attn/test/attnfakeelement.H $ */
/* */
/* OpenPOWER HostBoot Project */
/* */
/* COPYRIGHT International Business Machines Corp. 2012,2014 */
/* */
/* Licensed under the Apache License, Version 2.0 (the "License"); */
/* you may not use this file except in compliance with the License. */
/* You may obtain a copy of the License at */
/* */
/* http://www.apache.org/licenses/LICENSE-2.0 */
/* */
/* Unless required by applicable law or agreed to in writing, software */
/* distributed under the License is distributed on an "AS IS" BASIS, */
/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */
/* implied. See the License for the specific language governing */
/* permissions and limitations under the License. */
/* */
/* IBM_PROLOG_END_TAG */
#ifndef __TEST_ATTNFAKEELEMENT_H
#define __TEST_ATTNFAKEELEMENT_H
/**
* @file attnfakeelement.H
*
* @brief HBATTN fake system element class definitions.
*/
#include "attntest.H"
namespace ATTN
{
/**
* @brief FakeSource Attention source interface.
*
* Interface definition for classes wishing to attach logic
* to FakeSystem error injections.
*/
class FakeSource
{
public:
/**
* @brief dtor
*/
virtual ~FakeSource() {}
/**
* @brief processPutAttention Process injected attention.
*
* @param[in] i_sys System on which attention was injected.
* @param[in] i_attn Attention that was injected.
* @param[in] i_count number of attentions currently present.
*/
virtual errlHndl_t processPutAttention(
FakeSystem & i_sys,
const PRDF::AttnData & i_attn,
uint64_t i_count) = 0;
/**
* @brief processClearAttention Process cleared attention.
*
* @param[in] i_sys System on which attention was cleared.
* @param[in] i_attn Attention that was cleared.
* @param[in] i_count number of attentions currently present.
*/
virtual errlHndl_t processClearAttention(
FakeSystem & i_sys,
const PRDF::AttnData & i_attn,
uint64_t i_count) = 0;
};
/**
* @brief FakeReg Register interface.
*
* Interface definition for classes wishing to attach logic
* to FakeSystem register modifications.
*/
class FakeReg
{
public:
/**
* @brief dtor
*/
virtual ~FakeReg() {}
/**
* @brief processPutReg Process modified register content.
*
* @param[in] i_sys System that modified register content.
* @param[in] i_target Target whose registers were modified.
* @param[in] i_address Address of register that was modified.
* @param[in] i_new Register content after modification.
* @param[in] i_old Register content before modification.
*/
virtual errlHndl_t processPutReg(
FakeSystem & i_sys,
TARGETING::TargetHandle_t i_target,
uint64_t i_address,
uint64_t i_new,
uint64_t i_old) = 0;
};
}
#endif
|
