blob: b121bfdb0ad0ce56615495c9a52153167429ddd7 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
|
/* IBM_PROLOG_BEGIN_TAG */
/* This is an automatically generated prolog. */
/* */
/* $Source: src/import/generic/memory/lib/utils/voltage/gen_mss_voltage_traits.H $ */
/* */
/* OpenPOWER HostBoot Project */
/* */
/* Contributors Listed Below - COPYRIGHT 2018 */
/* [+] International Business Machines Corp. */
/* */
/* */
/* Licensed under the Apache License, Version 2.0 (the "License"); */
/* you may not use this file except in compliance with the License. */
/* You may obtain a copy of the License at */
/* */
/* http://www.apache.org/licenses/LICENSE-2.0 */
/* */
/* Unless required by applicable law or agreed to in writing, software */
/* distributed under the License is distributed on an "AS IS" BASIS, */
/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */
/* implied. See the License for the specific language governing */
/* permissions and limitations under the License. */
/* */
/* IBM_PROLOG_END_TAG */
///
/// @file gen_mss_voltage_traits.H
/// @brief Contains voltage traits information
///
// *HWP HWP Owner: Stephen Glancy <sglancy@us.ibm.com>
// *HWP FW Owner: Andre Marin <aamarin@us.ibm.com>
// *HWP Team: Memory
// *HWP Level: 2
// *HWP Consumed by: CI
#ifndef _GEN_MSS_VOLTAGE_TRAITS_H_
#define _GEN_MSS_VOLTAGE_TRAITS_H_
#include <fapi2.H>
#include <generic/memory/lib/utils/shared/mss_generic_consts.H>
namespace mss
{
///
/// @class Traits and policy class for voltage code
/// @tparam P mss::proc_type processor type
/// @tparam D mss::spd::device_type DRAM device type (generation)
///
template< mss::mc_type P, mss::spd::device_type D >
class voltage_traits;
///
/// @class Traits and policy class for voltage code - specialization for the NIMBUS processor type, DDR4 device type
///
template<>
class voltage_traits<mss::mc_type::NIMBUS, mss::spd::device_type::DDR4>
{
public:
//////////////////////////////////////////////////////////////
// Target types
//////////////////////////////////////////////////////////////
static constexpr fapi2::TargetType VOLTAGE_TARGET_TYPE = fapi2::TARGET_TYPE_MCBIST;
static constexpr fapi2::TargetType SPD_TARGET_TYPE = fapi2::TARGET_TYPE_MCS;
//////////////////////////////////////////////////////////////
// Traits values
//////////////////////////////////////////////////////////////
// List of attribute setter functions for setting voltage rail values
static const std::vector<fapi2::ReturnCode (*)(const fapi2::Target<VOLTAGE_TARGET_TYPE>&, uint32_t)> voltage_setters;
};
///
/// @class Traits and policy class for voltage code - specialization for the AXONE processor type, DDR4 device type
///
template<>
class voltage_traits<mss::mc_type::EXPLORER, mss::spd::device_type::DDR4>
{
public:
//////////////////////////////////////////////////////////////
// Target types
//////////////////////////////////////////////////////////////
static constexpr fapi2::TargetType VOLTAGE_TARGET_TYPE = fapi2::TARGET_TYPE_OCMB_CHIP;
static constexpr fapi2::TargetType SPD_TARGET_TYPE = fapi2::TARGET_TYPE_MEM_PORT;
//////////////////////////////////////////////////////////////
// Traits values
//////////////////////////////////////////////////////////////
// List of attribute setter functions for setting voltage rail values
static const std::vector<fapi2::ReturnCode (*)(const fapi2::Target<VOLTAGE_TARGET_TYPE>&, uint32_t)> voltage_setters;
// Static consts for DDR4 voltages used in p9_mss_volt
static const uint64_t DDR4_NOMINAL_VOLTAGE = 1200;
static const uint64_t DDR4_VPP_VOLTAGE = 2500;
};
} // ns mss
#endif
|
