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<!-- IBM_PROLOG_BEGIN_TAG -->
<!-- This is an automatically generated prolog. -->
<!-- -->
<!-- $Source: src/import/chips/p9/procedures/xml/error_info/p9_pm_pss_errors.xml $ -->
<!-- -->
<!-- OpenPOWER HostBoot Project -->
<!-- -->
<!-- Contributors Listed Below - COPYRIGHT 2015,2018 -->
<!-- [+] International Business Machines Corp. -->
<!-- -->
<!-- -->
<!-- Licensed under the Apache License, Version 2.0 (the "License"); -->
<!-- you may not use this file except in compliance with the License. -->
<!-- You may obtain a copy of the License at -->
<!-- -->
<!-- http://www.apache.org/licenses/LICENSE-2.0 -->
<!-- -->
<!-- Unless required by applicable law or agreed to in writing, software -->
<!-- distributed under the License is distributed on an "AS IS" BASIS, -->
<!-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or -->
<!-- implied. See the License for the specific language governing -->
<!-- permissions and limitations under the License. -->
<!-- -->
<!-- IBM_PROLOG_END_TAG -->
<!-- Error definitions for p9_pm_pss_init procedure -->
<!--
*HWP HWP Owner: Amit Kumar <akumar3@us.ibm.com>
*HWP HWP Backup Owner: Greg Still <stillgs@us.ibm.com>
*HWP FW Owner: Sangeetha T S <sangeet2@in.ibm.com>
*HWP Team: PM
*HWP Level: 3
*HWP Consumed by: HS
-->
<hwpErrors>
<!-- *********************************************************************** -->
<hwpError>
<rc>RC_PM_PSS_ADC_ERROR</rc>
<description>SPIADC error bit asserted waiting for operation to complete.
</description>
<ffdc>CHIP</ffdc>
<ffdc>POLLCOUNT</ffdc>
<collectRegisterFfdc>
<id>PSS_FFDC_REGISTERS</id>
<target>CHIP</target>
<targetType>TARGET_TYPE_PROC_CHIP</targetType>
</collectRegisterFfdc>
<callout>
<target>CHIP</target>
<priority>HIGH</priority>
</callout>
<callout>
<procedure>CODE</procedure>
<priority>LOW</priority>
</callout>
</hwpError>
<!-- *********************************************************************** -->
<hwpError>
<rc>RC_PM_PSS_ADC_WRITE_WHILE_BUSY</rc>
<description>SPI ADC was written while the bridge was busy. Cleared with
coming reset.
</description>
<ffdc>CHIP</ffdc>
<ffdc>POLLCOUNT</ffdc>
<collectRegisterFfdc>
<id>PSS_FFDC_REGISTERS</id>
<target>CHIP</target>
<targetType>TARGET_TYPE_PROC_CHIP</targetType>
</collectRegisterFfdc>
<callout>
<target>CODE</target>
<priority>HIGH</priority>
</callout>
</hwpError>
<!-- *********************************************************************** -->
<hwpError>
<rc>RC_PM_PSS_ADC_TIMEOUT</rc>
<description>SPIADC timed waiting to be quiesced. The SPIADC will be reset
anyway so as to attempt to recover the interface.
</description>
<ffdc>CHIP</ffdc>
<ffdc>POLLCOUNT</ffdc>
<ffdc>MAXPOLLS</ffdc>
<ffdc>TIMEOUTUS</ffdc>
<collectRegisterFfdc>
<id>PSS_FFDC_REGISTERS</id>
<target>CHIP</target>
<targetType>TARGET_TYPE_PROC_CHIP</targetType>
</collectRegisterFfdc>
<callout>
<target>CHIP</target>
<priority>HIGH</priority>
</callout>
</hwpError>
<!-- *********************************************************************** -->
<hwpError>
<rc>RC_PM_PSS_P2S_ERROR</rc>
<description>SPIP2S error bit asserted waiting for operation to complete.
</description>
<ffdc>CHIP</ffdc>
<ffdc>POLLCOUNT</ffdc>
<collectRegisterFfdc>
<id>PSS_FFDC_REGISTERS</id>
<target>CHIP</target>
<targetType>TARGET_TYPE_PROC_CHIP</targetType>
</collectRegisterFfdc>
<callout>
<target>CHIP</target>
<priority>HIGH</priority>
</callout>
<callout>
<procedure>CODE</procedure>
<priority>LOW</priority>
</callout>
</hwpError>
<!-- *********************************************************************** -->
</hwpErrors>
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