blob: ec77ed527a50e9ac2de5fa9f1f27cce446d2f3b6 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
|
<!-- IBM_PROLOG_BEGIN_TAG -->
<!-- This is an automatically generated prolog. -->
<!-- -->
<!-- $Source: chips/p9/procedures/xml/attribute_info/pm_hwp_attributes.xml $ -->
<!-- -->
<!-- IBM CONFIDENTIAL -->
<!-- -->
<!-- EKB Project -->
<!-- -->
<!-- COPYRIGHT 2015,2016 -->
<!-- [+] International Business Machines Corp. -->
<!-- -->
<!-- -->
<!-- The source code for this program is not published or otherwise -->
<!-- divested of its trade secrets, irrespective of what has been -->
<!-- deposited with the U.S. Copyright Office. -->
<!-- -->
<!-- IBM_PROLOG_END_TAG -->
<!-- pm_plat_attributes.xml -->
<!-- -->
<!-- XML file specifying Power Management HWPF attributes. -->
<!-- These attributes are initialized by the platform. -->
<attributes>
<!-- ********************************************************************* -->
<attribute>
<id>ATTR_PROC_DPLL_DIVIDER</id>
<targetType>TARGET_TYPE_PROC_CHIP</targetType>
<description>The product of the DPLL internal prescalar divide
(CD_DIV124_DC) and the output divider(CD_DPLLOUT124_DC). This estalishes
the step size of the DPLL in terms of this number divided into the
processor reference clock.
if 0, consuming procedures will assume a default of 8.
Provided to override default value
</description>
<valueType>uint32</valueType>
<writeable/>
<initToZero/>
</attribute>
<!-- ********************************************************************* -->
<attribute>
<id>ATTR_STOPGPE_BOOT_COPIER_IVPR_OFFSET</id>
<targetType>TARGET_TYPE_PROC_CHIP</targetType>
<description>Set by p9_hcode_image build with the offset value from
the HOMER base where the SGPE Boot Copier interrupt vectors reside. This
value must be 512B aligned. The HOMER base address will be pre-establish
in PBABAR0 so the address needs to be off the form 0x8XXXXX00. The SGPE
will be Sreset after this value is established.
</description>
<valueType>uint32</valueType>
<writeable/>
</attribute>
<!-- ********************************************************************* -->
<attribute>
<id>ATTR_PSTATEGPE_BOOT_COPIER_IVPR_OFFSET</id>
<targetType>TARGET_TYPE_PROC_CHIP</targetType>
<description>Set by p9_hcode_image build with the offset value from
the HOMER base where the PGPE Boot Copier interrupt vectors reside. This
value must be 512B aligned. The HOMER base address will be pre-establish
in PBABAR0 so the address needs to be off the form 0x8XXXXX00. The PGPE
will be Sreset after this value is established
</description>
<valueType>uint32</valueType>
<writeable/>
</attribute>
<!-- ********************************************************************* -->
<attribute>
<id>ATTR_OCC_LFIR</id>
<targetType>TARGET_TYPE_PROC_CHIP</targetType>
<description>The attribute stores the Local FIR value of OCC taken
during the reset phase.
</description>
<valueType>uint32</valueType>
<writeable/>
</attribute>
<!-- ********************************************************************* -->
<attribute>
<id>ATTR_PBA_LFIR</id>
<targetType>TARGET_TYPE_PROC_CHIP</targetType>
<description>The attribute stores the Local FIR value of PBA taken
during the reset phase.
</description>
<valueType>uint32</valueType>
<writeable/>
</attribute>
<!-- ********************************************************************* -->
<attribute>
<id>ATTR_PM_FIRINIT_DONE_ONCE_FLAG</id>
<targetType>TARGET_TYPE_PROC_CHIP</targetType>
<description>
0 = OCC has never been loaded and FIR Masks have never been initialized,
1 = FIR masks have been initialized and the hardware should reflect
correct values,
2 = FIR masks have been initialized but the current hardware state is the
reset value
</description>
<valueType>uint8</valueType>
<writeable/>
</attribute>
<!-- ********************************************************************* -->
<attribute>
<id>ATTR_QUAD_PPM_ERRMASK</id>
<targetType>TARGET_TYPE_EQ</targetType>
<description>The error mask value that has to be restored to the PPM
ERRMASK register for the Quad. This value will be stored during the
reset phase when the ERRMASK will be cleared as part of the
cleanup action.
</description>
<valueType>uint32</valueType>
<writeable/>
</attribute>
<!-- ********************************************************************* -->
<attribute>
<id>ATTR_CORE_PPM_ERRMASK</id>
<targetType>TARGET_TYPE_CORE</targetType>
<description>The error mask value that has to be restored to the PPM
ERRMASK register for the CORE. This value will be stored during the
reset phase when the ERRMASK will be cleared as part of the
cleanup action.
</description>
<valueType>uint32</valueType>
<writeable/>
</attribute>
<!-- ********************************************************************* -->
<attribute>
<id>ATTR_CME_LOCAL_FIRMASK</id>
<targetType>TARGET_TYPE_EX</targetType>
<description>The FIR mask value that has to be restored to the CME FIR
register. This value will be stored during the reset phase when the
FIRMASK will be cleared as part of the cleanup action.
</description>
<valueType>uint32</valueType>
<writeable/>
</attribute>
<!-- ********************************************************************* -->
<attribute>
<id>ATTR_L2_HASCLOCKS</id>
<targetType>TARGET_TYPE_EX</targetType>
<description>Indicates the L2 region has clocks running and scommable
</description>
<valueType>uint8</valueType>
<writeable/>
</attribute>
<!-- ********************************************************************* -->
<attribute>
<id>ATTR_L3_HASCLOCKS</id>
<targetType>TARGET_TYPE_EX</targetType>
<description>Indicates the L3 region has clocks running and scommable
</description>
<valueType>uint8</valueType>
<writeable/>
</attribute>
<!-- ********************************************************************* -->
<attribute>
<id>ATTR_C0_EXEC_HASCLOCKS</id>
<targetType>TARGET_TYPE_EX</targetType>
<description>Indicates the execution units in core 0 have clocks running
and scommable
</description>
<valueType>uint8</valueType>
<writeable/>
</attribute>
<!-- ********************************************************************* -->
<attribute>
<id>ATTR_C1_EXEC_HASCLOCKS</id>
<targetType>TARGET_TYPE_EX</targetType>
<description>Indicates the execution units in core 1 have clocks running
and scommable
</description>
<valueType>uint8</valueType>
<writeable/>
</attribute>
<!-- ********************************************************************* -->
<attribute>
<id>ATTR_C0_PC_HASCLOCKS</id>
<targetType>TARGET_TYPE_EX</targetType>
<description>Indicates the core pervasive unit in core 0 has clocks
running and scommable
</description>
<valueType>uint8</valueType>
<writeable/>
</attribute>
<!-- ********************************************************************* -->
<attribute>
<id>ATTR_C1_PC_HASCLOCKS</id>
<targetType>TARGET_TYPE_EX</targetType>
<description>Indicates the core pervasive unit in core 1 has clocks
running and scommable
</description>
<valueType>uint8</valueType>
<writeable/>
</attribute>
<!-- ********************************************************************* -->
<attribute>
<id>ATTR_L2_HASPOWER</id>
<targetType>TARGET_TYPE_EX</targetType>
<description>Indicates L2 has power and has valid latch state that could
be scanned
</description>
<valueType>uint8</valueType>
<writeable/>
</attribute>
<!-- ********************************************************************* -->
<attribute>
<id>ATTR_L3_HASPOWER</id>
<targetType>TARGET_TYPE_EX</targetType>
<description>Indicates L3 has power and has valid latch state that could
be scanned
</description>
<valueType>uint8</valueType>
<writeable/>
</attribute>
<!-- ********************************************************************* -->
<attribute>
<id>ATTR_C0_HASPOWER</id>
<targetType>TARGET_TYPE_EX</targetType>
<description>Indicates core 0 has power and has valid latch state that
could be scanned
</description>
<valueType>uint8</valueType>
<writeable/>
</attribute>
<!-- ********************************************************************* -->
<attribute>
<id>ATTR_C1_HASPOWER</id>
<targetType>TARGET_TYPE_EX</targetType>
<description>Indicates core 1 has power and has valid latch state that
could be scanned
</description>
<valueType>uint8</valueType>
<writeable/>
</attribute>
<!-- ********************************************************************* -->
</attributes>
|
