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<!-- IBM_PROLOG_BEGIN_TAG -->
<!-- This is an automatically generated prolog. -->
<!-- -->
<!-- $Source: src/import/chips/p9/procedures/xml/attribute_info/p9a_omi_train.xml $ -->
<!-- -->
<!-- OpenPOWER HostBoot Project -->
<!-- -->
<!-- Contributors Listed Below - COPYRIGHT 2019 -->
<!-- [+] International Business Machines Corp. -->
<!-- -->
<!-- -->
<!-- Licensed under the Apache License, Version 2.0 (the "License"); -->
<!-- you may not use this file except in compliance with the License. -->
<!-- You may obtain a copy of the License at -->
<!-- -->
<!-- http://www.apache.org/licenses/LICENSE-2.0 -->
<!-- -->
<!-- Unless required by applicable law or agreed to in writing, software -->
<!-- distributed under the License is distributed on an "AS IS" BASIS, -->
<!-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or -->
<!-- implied. See the License for the specific language governing -->
<!-- permissions and limitations under the License. -->
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<!-- IBM_PROLOG_END_TAG -->
<!-- -->
<!-- @file p9a_omi_train.xml -->
<!-- @brief Attribute xml for p9a_omi_train -->
<!-- -->
<!-- *HWP HWP Owner: Devon Baughen <devon.baughen1@ibm.com> -->
<!-- *HWP HWP Backup: Stephen Glancy <sglancy@us.ibm.com> -->
<!-- *HWP FW Owner: Daniel Crowell <dcrowell@us.ibm.com> -->
<!-- *HWP Team: Memory -->
<!-- *HWP Level: 2 -->
<!-- *HWP Consumed by: FSP:HB -->
<!-- -->
<attributes>
<attribute>
<id>ATTR_OMI_DL_LN_REV_ENABLE</id>
<targetType>TARGET_TYPE_OMI</targetType>
<description>
The DL lane reversible enable bit in DL_CONFIG0_CFG (bit 38)
</description>
<valueType>uint8</valueType>
<enum>
ENABLED = 0x01,
DISABLED = 0x00
</enum>
<default>0x01</default>
<platInit/>
<mssAccessorName>omi_dl_ln_rev_enable</mssAccessorName>
</attribute>
</attributes>
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