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<!-- IBM_PROLOG_BEGIN_TAG -->
<!-- This is an automatically generated prolog. -->
<!-- -->
<!-- $Source: src/import/chips/p9/procedures/xml/attribute_info/p9_ei_bus_attributes.xml $ -->
<!-- -->
<!-- OpenPOWER HostBoot Project -->
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<!-- Contributors Listed Below - COPYRIGHT 2015,2016 -->
<!-- [+] International Business Machines Corp. -->
<!-- -->
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<!-- Licensed under the Apache License, Version 2.0 (the "License"); -->
<!-- you may not use this file except in compliance with the License. -->
<!-- You may obtain a copy of the License at -->
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<!-- http://www.apache.org/licenses/LICENSE-2.0 -->
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<!-- Unless required by applicable law or agreed to in writing, software -->
<!-- distributed under the License is distributed on an "AS IS" BASIS, -->
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<!-- implied. See the License for the specific language governing -->
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<!-- IBM_PROLOG_END_TAG -->
<attributes>
<!-- ********************************************************************** -->
<attribute>
<id>ATTR_EI_BUS_TX_MSBSWAP</id>
<targetType>TARGET_TYPE_DMI,TARGET_TYPE_MEMBUF_CHIP,TARGET_TYPE_XBUS</targetType>
<description>
Source: MRW: Downstream MSB Swap and Upstream MSB Swap
Usage: TX_MSBSWAP initfile setting for DMI and X buses
This attribute represents whether or not a single clock group bus such as DMI
and X bus was wired by the board designer using a feature called MSB Swap where
lane 0 of the TX chip wires to lane n-1 on the RX chip where 'n' is the width
of the bus. A basic description of this capability is that the board designer
can save layers on the board wiring by crossing the wiring between the two
chips in a prescribed manner. In a non-MSB Swapped bus Lane 0 on the TX chip
wires to lane 0 on the RX chip, lane 1 to lane 1 and so on. If a bus is MSB
Swapped then lane 0 of the TX chip wires to lane 'n-1' of the RX chip, lane 1
to lane 'n-2', etc. Random or arbitrary wiring of TX to RX lanes on different
chips is NOT ALLOWED.
The Master Chip of two connected chips is defined as the chip with the smaller
value of (100*Node + Pos). The Slave Chip of two connected chips is defined
as the chip with the larger value of (100*Node + Pos). The Downstream
direction is defined as the direction from the Master chip to the Slave chip.
The Upstream direction is defined as the direction from the Slave chip to the
Master chip.
The Downstream TX_MSBSWAP from the MRW is a uint8 value. 0x01 means the
Downstream bus is wired msb to lsb etc. and 0x00 means the bus is wired
normally, msb to msb, lsb to lsb (lane0 to lane0).
The Upstream TX_MSBSWAP from the MRW is a uint8 value. 0x01 means the
Upstream bus is wired msb to lsb etc. and 0x00 means the bus is wired
normally, msb to msb, lsb to lsb (lane0 to lane0).
It is up to the platform code to set up each ATTR_EI_BUS_TX_MSBSWAP value for
the correct target endpoints.
</description>
<valueType>uint8</valueType>
<enum>
NO_SWAP = 0x00,
ALL_SWAP = 0xFF,
GROUP_0_SWAP = 0x80,
GROUP_1_SWAP = 0x40
</enum>
<platInit/>
</attribute>
<!-- ********************************************************************** -->
</attributes>
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