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<!-- IBM_PROLOG_BEGIN_TAG -->
<!-- This is an automatically generated prolog. -->
<!-- -->
<!-- $Source: src/import/chips/p9/procedures/xml/attribute_info/memory_dq_attributes.xml $ -->
<!-- -->
<!-- OpenPOWER HostBoot Project -->
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<!-- Contributors Listed Below - COPYRIGHT 2016,2017 -->
<!-- [+] International Business Machines Corp. -->
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<!-- Licensed under the Apache License, Version 2.0 (the "License"); -->
<!-- you may not use this file except in compliance with the License. -->
<!-- You may obtain a copy of the License at -->
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<!-- http://www.apache.org/licenses/LICENSE-2.0 -->
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<!-- IBM_PROLOG_END_TAG -->
<attributes>
<attribute>
<id>ATTR_MSS_VPD_DQ_MAP</id>
<targetType>TARGET_TYPE_MCS</targetType>
<description>
[PORT][Dimm DQ PIN] The map from the Dual Inline Memory Module (DIMM) Data (DQ) Pin to the Module Package Data (DQ) Pinout
</description>
<initToZero></initToZero>
<valueType>uint8</valueType>
<writeable/>
<mssUnits></mssUnits>
<mssBlobStart>0</mssBlobStart>
<mssBlobLength>144</mssBlobLength>
<mssAccessorName>vpd_dq_map</mssAccessorName>
<array>2 72</array>
</attribute>
<attribute>
<id>ATTR_BAD_DQ_BITMAP</id>
<targetType>TARGET_TYPE_DIMM</targetType>
<description>
Bad DQ bitmap from a controller point of view.
The data is a 10 byte bitmap for each of 4 possible ranks.
The bad DQ data is stored in NVRAM, and it is stored in a special format
translated to a DIMM Connector point of view.
All of these details are hidden from the user of this attribute.
</description>
<valueType>uint8</valueType>
<mssAccessorName>bad_dq_bitmap</mssAccessorName>
<array>4 10</array>
<platInit/>
<initToZero/>
<writeable/>
</attribute>
</attributes>
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