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<!-- IBM_PROLOG_BEGIN_TAG -->
<!-- This is an automatically generated prolog. -->
<!-- -->
<!-- $Source: src/import/chips/p9/procedures/xml/attribute_info/memory_cke_attributes.xml $ -->
<!-- -->
<!-- OpenPOWER HostBoot Project -->
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<!-- Contributors Listed Below - COPYRIGHT 2016,2017 -->
<!-- [+] International Business Machines Corp. -->
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<!-- Licensed under the Apache License, Version 2.0 (the "License"); -->
<!-- you may not use this file except in compliance with the License. -->
<!-- You may obtain a copy of the License at -->
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<!-- http://www.apache.org/licenses/LICENSE-2.0 -->
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<!-- IBM_PROLOG_END_TAG -->
<attributes>
<attribute>
<id>ATTR_MSS_VPD_CKE_MAP</id>
<targetType>TARGET_TYPE_MCS</targetType>
<description>
The Memory Clock Enable MAP is a bit map describing the Memory Clock Enable signal to its respective rank.
There are 8 bits, but only 4 are currently used
[DIMM0 CKE0][DIMM0 CKE1][N/A][N/A][DIMM1 CKE0][DIMM1 CKE1][N/A][N/A]
E.g. 0x80 -> 0b10000000, which means DIMM0 CKE0 is mapped to that rank.
</description>
<initToZero></initToZero>
<valueType>uint8</valueType>
<writeable/>
<mssBlobStart>0</mssBlobStart>
<mssBlobLength>16</mssBlobLength>
<mssAccessorName>vpd_cke_map</mssAccessorName>
<array>2 2 4</array>
</attribute>
</attributes>
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