1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
|
/* IBM_PROLOG_BEGIN_TAG */
/* This is an automatically generated prolog. */
/* */
/* $Source: src/import/chips/p9/procedures/hwp/pm/p9_pm_pss_init.C $ */
/* */
/* OpenPOWER HostBoot Project */
/* */
/* Contributors Listed Below - COPYRIGHT 2015,2016 */
/* [+] International Business Machines Corp. */
/* */
/* */
/* Licensed under the Apache License, Version 2.0 (the "License"); */
/* you may not use this file except in compliance with the License. */
/* You may obtain a copy of the License at */
/* */
/* http://www.apache.org/licenses/LICENSE-2.0 */
/* */
/* Unless required by applicable law or agreed to in writing, software */
/* distributed under the License is distributed on an "AS IS" BASIS, */
/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */
/* implied. See the License for the specific language governing */
/* permissions and limitations under the License. */
/* */
/* IBM_PROLOG_END_TAG */
/// @file p9_pm_pss_init.C
/// @brief Initializes P2S and HWC logic
///
// *HWP HWP Owner: Amit Kumar <akumar3@us.ibm.com>
// *HWP Backup HWP Owner: Greg Still <stillgs@us.ibm.com>
// *HWP FW Owner: Sangeetha T S <sangeet2@in.ibm.com>
// *HWP Team: PM
// *HWP Level: 1
// *HWP Consumed by: FSP:HS
///
/// Procedure Summary:
/// --------------------
/// One procedure to initialize both P2S and HWC SPIPSS registers to
/// second Procedure is to access APSS or DPSS through P2S Bridge
/// Third procedure is to access APSS or DPSS through HWC (hardware control)
///
/// High-level procedure flow:
/// ----------------------------------
/// o INIT PROCEDURE(frame_size,cpol,cpha)
/// - set SPIPSS_ADC_CTRL_REG0(24b)
/// hwctrl_frame_size = 16
/// - set SPIPSS_ADC_CTRL_REG1
/// hwctrl_fsm_enable = disable
/// hwctrl_device = APSS
/// hwctrl_cpol = 0 (set idle state = deasserted)
/// hwctrl_cpha = 0 (set 1st edge = capture 2nd edge = change)
/// hwctrl_clock_divider = set to 10Mhz(0x1D)
/// hwctrl_nr_of_frames (4b) = 16 (for auto 2 mode)
/// - set SPIPSS_ADC_CTRL_REG2
/// hwctrl_interframe_delay = 0x0
/// - clear SPIPSS_ADC_WDATA_REG
/// - set SPIPSS_P2S_CTRL_REG0 (24b)
/// p2s_frame_size = 16
/// - set SPIPSS_P2S_CTRL_REG1
/// p2s_bridge_enable = disable
/// p2s_device = DPSS
/// p2s_cpol = 0
/// p2s_cpha = 0
/// p2s_clock_divider = set to 10Mhz
/// p2s_nr_of_frames (1b) = 0 (means 1 frame operation)
/// - set SPIPSS_P2S_CTRL_REG2
/// p2s_interframe_delay = 0x0
/// - clear SPIPSS_P2S_WDATA_REG
/// Procedure Prereq:
/// o System clocks are running
///
// -----------------------------------------------------------------------------
// Includes
// -----------------------------------------------------------------------------
#include <p9_pm_pss_init.H>
// -----------------------------------------------------------------------------
// Function prototypes
// -----------------------------------------------------------------------------
//------------------------------------------------------------------------------
///
/// @brief Determines the configuration setting for the SPI bus based on
/// attributes
///
/// @param[in] i_target Chip target
///
/// @return FAPI2_RC_SUCCESS on success, else error.
///
fapi2::ReturnCode pm_pss_config_spi_settings(
const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target);
//------------------------------------------------------------------------------
///
/// @brief Using configured attributed, performs the initialization of the PSS
/// function
///
/// @param[in] i_target Chip target
///
/// @return FAPI2_RC_SUCCESS on success, else error.
///
fapi2::ReturnCode pm_pss_init(
const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target);
//------------------------------------------------------------------------------
///
/// @brief Performs the reset of the PSS function
///
/// @param[in] i_target Chip target
///
/// @return FAPI2_RC_SUCCESS on success, else error.
///
fapi2::ReturnCode pm_pss_reset(
const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target);
// -----------------------------------------------------------------------------
// Function definitions
// -----------------------------------------------------------------------------
fapi2::ReturnCode p9_pm_pss_init(
const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target,
const p9pm::PM_FLOW_MODE i_mode)
{
FAPI_IMP("p9_pm_pss_init Enter");
FAPI_IMP("p9_pm_pss_init Exit");
return fapi2::current_err;
}
fapi2::ReturnCode pm_pss_config_spi_settings(
const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target)
{
FAPI_IMP("pm_pss_config_spi_settings Enter");
return fapi2::current_err;
}
fapi2::ReturnCode pm_pss_init(
const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target)
{
FAPI_IMP("pm_pss_init Enter");
return fapi2::current_err;
}
fapi2::ReturnCode pm_pss_reset(
const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target)
{
FAPI_IMP("pm_pss_reset Enter");
return fapi2::current_err;
}
|
