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/* IBM_PROLOG_BEGIN_TAG */
/* This is an automatically generated prolog. */
/* */
/* $Source: src/import/chips/p9/procedures/hwp/perv/p9_chiplet_enable_ridi.C $ */
/* */
/* OpenPOWER HostBoot Project */
/* */
/* Contributors Listed Below - COPYRIGHT 2015,2017 */
/* [+] International Business Machines Corp. */
/* */
/* */
/* Licensed under the Apache License, Version 2.0 (the "License"); */
/* you may not use this file except in compliance with the License. */
/* You may obtain a copy of the License at */
/* */
/* http://www.apache.org/licenses/LICENSE-2.0 */
/* */
/* Unless required by applicable law or agreed to in writing, software */
/* distributed under the License is distributed on an "AS IS" BASIS, */
/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */
/* implied. See the License for the specific language governing */
/* permissions and limitations under the License. */
/* */
/* IBM_PROLOG_END_TAG */
//------------------------------------------------------------------------------
/// @file p9_chiplet_enable_ridi.C
///
/// @brief Enable RI/DI for all IO chiplets (excluding XBUS)
//------------------------------------------------------------------------------
// *HWP HW Owner : Abhishek Agarwal <abagarw8@in.ibm.com>
// *HWP HW Backup Owner : Srinivas V Naga <srinivan@in.ibm.com>
// *HWP FW Owner : Sunil Kumar <skumar8j@in.ibm.com>
// *HWP Team : Perv
// *HWP Level : 2
// *HWP Consumed by : HB
//------------------------------------------------------------------------------
//## auto_generated
#include "p9_chiplet_enable_ridi.H"
#include "p9_perv_scom_addresses.H"
static fapi2::ReturnCode p9_chiplet_enable_ridi_net_ctrl_action_function(
const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chiplet);
fapi2::ReturnCode p9_chiplet_enable_ridi(const
fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target_chip)
{
FAPI_DBG("Entering ...");
for(auto l_target_cplt : i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV>
(static_cast<fapi2::TargetFilter>(fapi2::TARGET_FILTER_ALL_MC |
fapi2::TARGET_FILTER_ALL_PCI |
fapi2::TARGET_FILTER_ALL_OBUS),
fapi2::TARGET_STATE_FUNCTIONAL))
{
FAPI_INF("Call p9_chiplet_enable_ridi_net_ctrl_action_function");
FAPI_TRY(p9_chiplet_enable_ridi_net_ctrl_action_function(l_target_cplt));
}
FAPI_DBG("Exiting ...");
fapi_try_exit:
return fapi2::current_err;
}
/// @brief Enable Drivers/Recievers of O, PCIE, MC chiplets
///
/// @param[in] i_target_chiplet Reference to TARGET_TYPE_PERV target
/// @return FAPI2_RC_SUCCESS if success, else error code.
static fapi2::ReturnCode p9_chiplet_enable_ridi_net_ctrl_action_function(
const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chiplet)
{
bool l_read_reg = false;
fapi2::buffer<uint64_t> l_data64;
FAPI_DBG("Entering ...");
FAPI_INF("Check for chiplet enable");
//Getting NET_CTRL0 register value
FAPI_TRY(fapi2::getScom(i_target_chiplet, PERV_NET_CTRL0, l_data64));
l_read_reg = l_data64.getBit<0>(); //l_read_reg = NET_CTRL0.CHIPLET_ENABLE
if ( l_read_reg )
{
FAPI_INF("Enable Recievers, Drivers DI1 & DI2");
//Setting NET_CTRL0 register value
l_data64.flush<0>();
l_data64.setBit<19>(); //NET_CTRL0.RI_N = 1
l_data64.setBit<20>(); //NET_CTRL0.DI1_N = 1
l_data64.setBit<21>(); //NET_CTRL0.DI2_N = 1
FAPI_TRY(fapi2::putScom(i_target_chiplet, PERV_NET_CTRL0_WOR, l_data64));
}
FAPI_DBG("Exiting ...");
fapi_try_exit:
return fapi2::current_err;
}
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