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/* IBM_PROLOG_BEGIN_TAG */
/* This is an automatically generated prolog. */
/* */
/* $Source: chips/p9/procedures/hwp/memory/p9_mss_ddr_phy_reset.H $ */
/* */
/* IBM CONFIDENTIAL */
/* */
/* EKB Project */
/* */
/* COPYRIGHT 2015 */
/* [+] International Business Machines Corp. */
/* */
/* */
/* The source code for this program is not published or otherwise */
/* divested of its trade secrets, irrespective of what has been */
/* deposited with the U.S. Copyright Office. */
/* */
/* IBM_PROLOG_END_TAG */
///
/// @file p9_mss_ddr_phy_reset.H
/// @brief Reset and initialize the DDR PHY
///
// *HWP HWP Owner: Brian Silver <bsilver@us.ibm.com>
// *HWP HWP Backup: Andre Marin <aamarin@us.ibm.com>
// *HWP Team: Memory
// *HWP Level: 2
// *HWP Consumed by: FSP:HB
#ifndef P9_MSS_DDR_PHY_RESET_H_
#define P9_MSS_DDR_PHY_RESET_H_
#include <fapi2.H>
typedef fapi2::ReturnCode (*p9_mss_ddr_phy_reset_FP_t)(const fapi2::Target<fapi2::TARGET_TYPE_MCBIST>& i_target);
extern "C"
{
///
/// @brief Reset the DDR PHY
/// @param[in] i_target, the McBIST of the ports of the dram you're training
/// @return FAPI2_RC_SUCCESS iff ok
///
fapi2::ReturnCode p9_mss_ddr_phy_reset( const fapi2::Target<fapi2::TARGET_TYPE_MCBIST>& i_target );
}
#endif
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