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|
# Joe's initfile reference page:
# https://w3-connections.ibm.com/wikis/home?lang=en-us#!/wiki/W9dc674bd1c19_432e_9f66_0e8b6ce7195f/page/P9%20Initfile%20Strategy%20%26%20Execution
# http://ausxgsatm2.austin.ibm.com/gsa/home/j/m/jmcgill/web/public/p8/initfiles/mba_def.initfile
#--******************************************************************************
#-- ISSUES TO RESOVLE
#--******************************************************************************
#
#--******************************************************************************
#-- IMPORTANT SUPPORT NOTES AS OF 4/21/2016
#--******************************************************************************
# Currently only supports DIMMS where CL=TRCD=TRP (ie 16-16-16)
# Steve Powell says he's seen DIMMs that don't match
# What needs to be done to support other DIMMs
# Replace def_MEM_TYPE_1866_13_13_13 variables with freq+CL variables
# Because TRCD and TRP don't really matter for the equations that this variable is being used for
# So we should rewrite these equations in terms of just freq+CL
# Here we assume WL = ATTR_EFF_DRAM_CWL (which is true if no Additive Latency / Posted CAS).
# So no support for Posted CAS / Additive latency
# Only supports Burst Length 8 (CODE AND LOGIC STATEMENT)
# Initfile is hardcoded assuming BL=8 and BL/2=4
# Attribute does exist for Burst length. However, Nimbus logic does NOT support any other burst lengths
# If other burst lengths are to be supported, a logic change would be required
# Only supports RDIMM with RDIMM and LRDIMM with LRDIMM, no mixing (CODE AND LOGIC STATEMENT)
# Logic would have to support different wr data delays to differen DIMMs. It does NOT.
#
#--******************************************************************************
#-- FUTURE ENHANCEMENTS
#--******************************************************************************
# ATTR_EFF_TCCD_S attribute (hardcoded to 4 for now)
#--******************************************************************************
#-- REFERENCES FOR FILE
#--******************************************************************************
# Files used to check what target type attributes are
# /afs/awd/projects/eclipz/pz6/usr/sleung/ekb/chips/p9/procedures/xml/attribute_info/memory_mcs_attributes.xml
# /afs/awd/projects/eclipz/pz6/usr/sleung/ekb/chips/p9/procedures/xml/attribute_info/memory_spd_attributes.xml
# /afs/awd/projects/eclipz/pz6/usr/sleung/ekb/chips/p9/procedures/xml/attribute_info/memory_mr_attributes.xml
# Example:
# <id>ATTR_EFF_NUM_RANKS_PER_DIMM</id>
# <targetType>TARGET_TYPE_MCS</targetType>
# File used to see if attribute is 1D or 2D array
# /afs/awd/projects/eclipz/pz6/usr/sleung/ekb/output/gen/attribute_ids.H
# Example:
# typedef uint8_t ATTR_EFF_DIMM_TYPE_Type[2][2];
# File for finding correct spydef name
# 1st find the spydef file this ekb build is looking at by finding SPYDEF_FILE_LOCATION in file below
# /afs/awd/projects/eclipz/pz6/usr/sleung/ekb/tools/ifCompiler/scan_procedures.mk
# 2nd open *.spydef in that dir and search for spy names
# /afs/awd/projects/eclipz/lab/p9/vbu_models/n10_e9067_tp058_ec163uXXa_soa_sq_u190_01/edc/*.spydef
# (File comes from actually building a vbu file and looking at the spydef)
# Example:
# idial MCP.PORT1.SRQ.PC.MBAREF0Q_CFG_TRFC {
# Wrapper file calling this
# /afs/awd/projects/eclipz/pz6/usr/sleung/ekb/chips/p9/procedures/hwp/memory/p9_mss_scominit.C
# Output file generated
# /afs/awd/projects/eclipz/pz6/usr/sleung/ekb/chips/p9/procedures/hwp/initfiles/p9_mca_scom.C
#
# COMMON DEBUG
# -debug5.16.i6.d
# If complaining unsupported attribute, try commenting out of attribute in attribute file
# If complaining memory fault, maybe wrong integer length in attribute file
#--******************************************************************************
#-- Required keywords/variables
#--******************************************************************************
SyntaxVersion = 3
target_type 0 TARGET_TYPE_MCA;
target_type 1 TARGET_TYPE_MCBIST;
target_type 2 TARGET_TYPE_MCS;
target_type 3 TARGET_TYPE_SYSTEM;
define MCBIST = TGT1; # If referencing Attr from mcbist, add "MCBIST." in front
define MCS = TGT2; # If referencing Attr from mcs, add "MCS." in front
define SYS = TGT3; # If referencing Attr from system, add "SYS." in front
define def_IS_HW = SYS.ATTR_IS_SIMULATION == 0;
define def_IS_SIM = SYS.ATTR_IS_SIMULATION == 1;
#--******************************************************************************
#-- Systems Config
#--******************************************************************************
#--******************************************************************************
#-- Effective Attributes
#--******************************************************************************
# PORT INDEX FOR ACCESSING PROPER ENTRY IN ARRAY
define def_POSITION = ATTR_CHIP_UNIT_POS;
define def_PORT_INDEX = def_POSITION % 2;
# define frequency range for potential support of sync mode
define def_MSS_FREQ_EQ_1866 = ( (MCBIST.ATTR_MSS_FREQ<1867));
define def_MSS_FREQ_EQ_2133 = ((MCBIST.ATTR_MSS_FREQ>=1867) && (MCBIST.ATTR_MSS_FREQ<2134));
define def_MSS_FREQ_EQ_2400 = ((MCBIST.ATTR_MSS_FREQ>=2134) && (MCBIST.ATTR_MSS_FREQ<2401));
define def_MSS_FREQ_EQ_2667 = ((MCBIST.ATTR_MSS_FREQ>=2667) );
define def_MEM_TYPE_1866_13 = def_MSS_FREQ_EQ_1866 && ( MCS.ATTR_EFF_DRAM_CL[def_PORT_INDEX] == 13 );
define def_MEM_TYPE_1866_14 = def_MSS_FREQ_EQ_1866 && ( MCS.ATTR_EFF_DRAM_CL[def_PORT_INDEX] == 14 );
define def_MEM_TYPE_2133_15 = def_MSS_FREQ_EQ_2133 && ( MCS.ATTR_EFF_DRAM_CL[def_PORT_INDEX] == 15 );
define def_MEM_TYPE_2133_16 = def_MSS_FREQ_EQ_2133 && ( MCS.ATTR_EFF_DRAM_CL[def_PORT_INDEX] == 16 );
define def_MEM_TYPE_2400_16 = def_MSS_FREQ_EQ_2400 && ( MCS.ATTR_EFF_DRAM_CL[def_PORT_INDEX] == 16 );
define def_MEM_TYPE_2400_17 = def_MSS_FREQ_EQ_2400 && ( MCS.ATTR_EFF_DRAM_CL[def_PORT_INDEX] == 17 );
define def_MEM_TYPE_2400_18 = def_MSS_FREQ_EQ_2400 && ( MCS.ATTR_EFF_DRAM_CL[def_PORT_INDEX] == 18 );
define def_MEM_TYPE_2667_18 = def_MSS_FREQ_EQ_2667 && ( MCS.ATTR_EFF_DRAM_CL[def_PORT_INDEX] == 18 );
define def_MEM_TYPE_2667_19 = def_MSS_FREQ_EQ_2667 && ( MCS.ATTR_EFF_DRAM_CL[def_PORT_INDEX] == 19 );
define def_MEM_TYPE_2667_20 = def_MSS_FREQ_EQ_2667 && ( MCS.ATTR_EFF_DRAM_CL[def_PORT_INDEX] == 20 );
define def_NUM_RANKS = ( MCS.ATTR_EFF_NUM_RANKS_PER_DIMM[def_PORT_INDEX][0]
+ MCS.ATTR_EFF_NUM_RANKS_PER_DIMM[def_PORT_INDEX][1] );
# We don't have a div 0 problem here as we don't run this if we don't have DIMM so the number of ranks won't be 0.
define def_REFRESH_INTERVAL = ((MCS.ATTR_EFF_DRAM_TREFI[def_PORT_INDEX])/(8*def_NUM_RANKS));
define def_RANK_SWITCH_TCK = 4 + ((MCBIST.ATTR_MSS_FREQ-1866)/267); # 1866: 4 2133: 5 2400: 6 2667: 7
define def_BUS_TURNAROUND_TCK = 4 + ((MCBIST.ATTR_MSS_FREQ-1866)/267); # 1866: 4 2133: 5 2400: 6 2667: 7
# Funky ... If the attribute is 0, then the value of the == operation will be 1 which bitwise-or'd with 0 gives us 1. If the attribute is != 0, then the
# value of the == operation will be 0 which when bitwise-or'd with the attribute will give us the attribute value. Love, Prachi, Jenny, Shelton and Brian.
define def_SLOT0_DENOMINATOR = (MCS.ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[def_PORT_INDEX][0] == 0x0) | MCS.ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[def_PORT_INDEX][0];
define def_SLOT1_DENOMINATOR = (MCS.ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[def_PORT_INDEX][1] == 0x0) | MCS.ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[def_PORT_INDEX][1];
define def_SLOT0_DRAM_STACK_HEIGHT = ( MCS.ATTR_EFF_NUM_RANKS_PER_DIMM[def_PORT_INDEX][0]
/ def_SLOT0_DENOMINATOR );
define def_SLOT1_DRAM_STACK_HEIGHT = ( MCS.ATTR_EFF_NUM_RANKS_PER_DIMM[def_PORT_INDEX][1]
/ def_SLOT1_DENOMINATOR );
#--******************************************************************************
#-- Dial Assignments
#--******************************************************************************
# TMR0 SCOM REGISTER #
# DRAM TIMING PARAMETERS #
ispy MCP.PORT0.SRQ.MBA_TMR0Q_RRDM_DLY [when=S] { # BL/2+rank_switch
spyv;
4 + def_RANK_SWITCH_TCK;
}
ispy MCP.PORT0.SRQ.MBA_TMR0Q_RRSMSR_DLY [when=S] { # tccd_s
spyv;
4;
}
ispy MCP.PORT0.SRQ.MBA_TMR0Q_RRSMDR_DLY [when=S] { # tccd_s
spyv;
4;
}
ispy MCP.PORT0.SRQ.MBA_TMR0Q_RROP_DLY [when=S] { # tccd_l
spyv;
MCS.ATTR_EFF_DRAM_TCCD_L[def_PORT_INDEX];
}
ispy MCP.PORT0.SRQ.MBA_TMR0Q_WWDM_DLY [when=S] { # BL/2+rank_switch
spyv;
4 + def_RANK_SWITCH_TCK;
}
ispy MCP.PORT0.SRQ.MBA_TMR0Q_WWSMSR_DLY [when=S] { # tccd_s
spyv;
4;
}
ispy MCP.PORT0.SRQ.MBA_TMR0Q_WWSMDR_DLY [when=S] { # tccd_s
spyv;
4;
}
ispy MCP.PORT0.SRQ.MBA_TMR0Q_WWOP_DLY [when=S] { # tccd_l
spyv;
MCS.ATTR_EFF_DRAM_TCCD_L[def_PORT_INDEX];
}
ispy MCP.PORT0.SRQ.MBA_TMR0Q_RWDM_DLY [when=S] { # (RL+BL/2+turn_around)-WL
spyv;
MCS.ATTR_EFF_DRAM_CL[def_PORT_INDEX] + 4 + def_BUS_TURNAROUND_TCK - MCS.ATTR_EFF_DRAM_CWL[def_PORT_INDEX];
}
ispy MCP.PORT0.SRQ.MBA_TMR0Q_RWSMSR_DLY [when=S] { # (RL+BL/2+turn_around)-WL
spyv;
MCS.ATTR_EFF_DRAM_CL[def_PORT_INDEX] + 4 + def_BUS_TURNAROUND_TCK - MCS.ATTR_EFF_DRAM_CWL[def_PORT_INDEX];
}
ispy MCP.PORT0.SRQ.MBA_TMR0Q_RWSMDR_DLY [when=S] { # (RL+BL/2+turn_around)-WL
spyv;
MCS.ATTR_EFF_DRAM_CL[def_PORT_INDEX] + 4 + def_BUS_TURNAROUND_TCK - MCS.ATTR_EFF_DRAM_CWL[def_PORT_INDEX];
}
ispy MCP.PORT0.SRQ.MBA_TMR0Q_WRDM_DLY [when=S] { # (WL+BL/2+turn_around)-RL
spyv;
MCS.ATTR_EFF_DRAM_CWL[def_PORT_INDEX] + 4 + def_BUS_TURNAROUND_TCK - MCS.ATTR_EFF_DRAM_CL[def_PORT_INDEX];
}
ispy MCP.PORT0.SRQ.MBA_TMR0Q_WRSMSR_DLY [when=S] { # WL+BL/2+(Twtr_s/clock period)
spyv;
MCS.ATTR_EFF_DRAM_CWL[def_PORT_INDEX] + 4 + MCS.ATTR_EFF_DRAM_TWTR_S[def_PORT_INDEX];
}
ispy MCP.PORT0.SRQ.MBA_TMR0Q_WRSMDR_DLY [when=S] { # WL+BL/2+Twtr_s
spyv;
MCS.ATTR_EFF_DRAM_CWL[def_PORT_INDEX] + 4 + MCS.ATTR_EFF_DRAM_TWTR_S[def_PORT_INDEX];
}
# TMR1 SCOM REGISTER #
# DRAM TIMING PARAMETERS #
ispy MCP.PORT0.SRQ.MBA_TMR1Q_RRSBG_DLY [when=S] { # tCCDL
spyv;
MCS.ATTR_EFF_DRAM_TCCD_L[def_PORT_INDEX];
}
ispy MCP.PORT0.SRQ.MBA_TMR1Q_WRSBG_DLY [when=S] { # WL+BL/2+Twtr_l
spyv;
MCS.ATTR_EFF_DRAM_CWL[def_PORT_INDEX] + 4 + MCS.ATTR_EFF_DRAM_TWTR_L[def_PORT_INDEX];
}
ispy MCP.PORT0.SRQ.MBA_TMR1Q_CFG_TFAW [when=S] {
spyv;
MCS.ATTR_EFF_DRAM_TFAW[def_PORT_INDEX];
}
ispy MCP.PORT0.SRQ.MBA_TMR1Q_CFG_TRCD [when=S] {
spyv;
MCS.ATTR_EFF_DRAM_TRCD[def_PORT_INDEX];
}
ispy MCP.PORT0.SRQ.MBA_TMR1Q_CFG_TRP [when=S] {
spyv;
MCS.ATTR_EFF_DRAM_TRP[def_PORT_INDEX];
}
ispy MCP.PORT0.SRQ.MBA_TMR1Q_CFG_TRAS [when=S] {
spyv;
MCS.ATTR_EFF_DRAM_TRAS[def_PORT_INDEX];
}
ispy MCP.PORT0.SRQ.MBA_TMR1Q_CFG_WR2PRE [when=S] { # CWL+BL/2+Twr
spyv;
MCS.ATTR_EFF_DRAM_CWL[def_PORT_INDEX] + 4 + MCS.ATTR_EFF_DRAM_TWR[def_PORT_INDEX];
}
ispy MCP.PORT0.SRQ.MBA_TMR1Q_CFG_RD2PRE [when=S] {
spyv;
MCS.ATTR_EFF_DRAM_TRTP[def_PORT_INDEX];
}
ispy MCP.PORT0.SRQ.MBA_TMR1Q_TRRD [when=S] {
spyv;
MCS.ATTR_EFF_DRAM_TRRD_S[def_PORT_INDEX];
}
ispy MCP.PORT0.SRQ.MBA_TMR1Q_TRRD_SBG [when=S] {
spyv;
MCS.ATTR_EFF_DRAM_TRRD_L[def_PORT_INDEX];
}
ispy MCP.PORT0.SRQ.MBA_TMR1Q_CFG_ACT_TO_DIFF_RANK_DLY [when=S] {
spyv, expr;
8, (def_MSS_FREQ_EQ_1866==1);
9, (def_MSS_FREQ_EQ_2133==1);
10, (def_MSS_FREQ_EQ_2400==1);
11, (def_MSS_FREQ_EQ_2667==1);
}
# DSM0 SCOM REGISTER #
# DRAM TIMING PARAMETERS #
# TODO RTC: 166455 NEED TO GET THE FORMULA FOR THIS - CURRENTLY GUESSES!
ispy MCP.PORT0.SRQ.MBA_DSM0Q_CFG_RDTAG_DLY [when=S] { # ATTR_EFF_DIMM_TYPE: CDIMM = 0 RDIMM = 1 UDIMM = 2 LRDIMM = 3
spyv, expr;
17, def_IS_SIM;
22, ((def_MEM_TYPE_1866_13==1) && (MCS.ATTR_EFF_DIMM_TYPE[def_PORT_INDEX][0]==1)) && def_IS_HW;
22, ((def_MEM_TYPE_1866_14==1) && (MCS.ATTR_EFF_DIMM_TYPE[def_PORT_INDEX][0]==1)) && def_IS_HW;
26, ((def_MEM_TYPE_2133_15==1) && (MCS.ATTR_EFF_DIMM_TYPE[def_PORT_INDEX][0]==1)) && def_IS_HW;
26, ((def_MEM_TYPE_2133_16==1) && (MCS.ATTR_EFF_DIMM_TYPE[def_PORT_INDEX][0]==1)) && def_IS_HW;
26, ((def_MEM_TYPE_2400_16==1) && (MCS.ATTR_EFF_DIMM_TYPE[def_PORT_INDEX][0]==1)) && def_IS_HW;
26, ((def_MEM_TYPE_2400_17==1) && (MCS.ATTR_EFF_DIMM_TYPE[def_PORT_INDEX][0]==1)) && def_IS_HW;
26, ((def_MEM_TYPE_2400_18==1) && (MCS.ATTR_EFF_DIMM_TYPE[def_PORT_INDEX][0]==1)) && def_IS_HW;
26, ((def_MEM_TYPE_2667_18==1) && (MCS.ATTR_EFF_DIMM_TYPE[def_PORT_INDEX][0]==1)) && def_IS_HW;
28, ((def_MEM_TYPE_2667_19==1) && (MCS.ATTR_EFF_DIMM_TYPE[def_PORT_INDEX][0]==1)) && def_IS_HW;
28, ((def_MEM_TYPE_2667_20==1) && (MCS.ATTR_EFF_DIMM_TYPE[def_PORT_INDEX][0]==1)) && def_IS_HW;
24, ((def_MEM_TYPE_1866_13==1) && (MCS.ATTR_EFF_DIMM_TYPE[def_PORT_INDEX][0]==3)) && def_IS_HW;
24, ((def_MEM_TYPE_1866_14==1) && (MCS.ATTR_EFF_DIMM_TYPE[def_PORT_INDEX][0]==3)) && def_IS_HW;
28, ((def_MEM_TYPE_2133_15==1) && (MCS.ATTR_EFF_DIMM_TYPE[def_PORT_INDEX][0]==3)) && def_IS_HW;
28, ((def_MEM_TYPE_2133_16==1) && (MCS.ATTR_EFF_DIMM_TYPE[def_PORT_INDEX][0]==3)) && def_IS_HW;
28, ((def_MEM_TYPE_2400_16==1) && (MCS.ATTR_EFF_DIMM_TYPE[def_PORT_INDEX][0]==3)) && def_IS_HW;
28, ((def_MEM_TYPE_2400_17==1) && (MCS.ATTR_EFF_DIMM_TYPE[def_PORT_INDEX][0]==3)) && def_IS_HW;
28, ((def_MEM_TYPE_2400_18==1) && (MCS.ATTR_EFF_DIMM_TYPE[def_PORT_INDEX][0]==3)) && def_IS_HW;
26, ((def_MEM_TYPE_2667_18==1) && (MCS.ATTR_EFF_DIMM_TYPE[def_PORT_INDEX][0]==3)) && def_IS_HW;
30, ((def_MEM_TYPE_2667_19==1) && (MCS.ATTR_EFF_DIMM_TYPE[def_PORT_INDEX][0]==3)) && def_IS_HW;
30, ((def_MEM_TYPE_2667_20==1) && (MCS.ATTR_EFF_DIMM_TYPE[def_PORT_INDEX][0]==3)) && def_IS_HW;
}
ispy MCP.PORT0.SRQ.MBA_DSM0Q_CFG_WRDATA_DLY [when=S] {
spyv, expr;
MCS.ATTR_EFF_DRAM_CWL[def_PORT_INDEX] + MCS.ATTR_MSS_VPD_MR_DPHY_WLO[def_PORT_INDEX] - 8, (MCS.ATTR_EFF_DIMM_TYPE[def_PORT_INDEX][0]==1); # RDIMM
MCS.ATTR_EFF_DRAM_CWL[def_PORT_INDEX] + MCS.ATTR_MSS_VPD_MR_DPHY_WLO[def_PORT_INDEX] - 9, (MCS.ATTR_EFF_DIMM_TYPE[def_PORT_INDEX][0]!=1); # not RDIMM
}
ispy MCP.PORT0.SRQ.MBA_DSM0Q_CFG_WRDONE_DLY [when=S] {
spyv;
24;
}
ispy MCP.PORT0.SRQ.MBA_DSM0Q_CFG_RODT_START_DLY [when=S] {
spyv, expr;
4, (def_MEM_TYPE_1866_13==1);
5, (def_MEM_TYPE_1866_14==1);
6, (def_MEM_TYPE_2133_15==1);
7, (def_MEM_TYPE_2133_16==1);
7, (def_MEM_TYPE_2400_16==1);
8, (def_MEM_TYPE_2400_17==1);
9, (def_MEM_TYPE_2400_18==1);
9, (def_MEM_TYPE_2667_18==1);
10, (def_MEM_TYPE_2667_19==1);
11, (def_MEM_TYPE_2667_20==1);
}
ispy MCP.PORT0.SRQ.MBA_DSM0Q_CFG_RODT_END_DLY [when=S] {
spyv, expr;
9, (def_MEM_TYPE_1866_13==1);
10, (def_MEM_TYPE_1866_14==1);
11, (def_MEM_TYPE_2133_15==1);
12, (def_MEM_TYPE_2133_16==1);
12, (def_MEM_TYPE_2400_16==1);
13, (def_MEM_TYPE_2400_17==1);
14, (def_MEM_TYPE_2400_18==1);
14, (def_MEM_TYPE_2667_18==1);
15, (def_MEM_TYPE_2667_19==1);
16, (def_MEM_TYPE_2667_20==1);
}
ispy MCP.PORT0.SRQ.MBA_DSM0Q_CFG_WODT_START_DLY [when=S] {
spyv;
1;
}
ispy MCP.PORT0.SRQ.MBA_DSM0Q_CFG_WODT_END_DLY [when=S] {
spyv;
6;
}
# FARB0 SCOM REGISTER #
espy MCP.PORT0.SRQ.MBA_FARB0Q_CFG_PARITY_AFTER_CMD [when=S] {
spyv;
ON;
}
# REF0 SCOM REGISTER #
#gdial std_size 4gbx4 (8GB rank)
ispy MCP.PORT0.SRQ.PC.MBAREF0Q_CFG_REFRESH_INTERVAL [when=S] {
spyv;
def_REFRESH_INTERVAL;
}
ispy MCP.PORT0.SRQ.PC.MBAREF0Q_CFG_TRFC [when=S] {
spyv;
MCS.ATTR_EFF_DRAM_TRFC[def_PORT_INDEX];
}
ispy MCP.PORT0.SRQ.PC.MBAREF0Q_CFG_REFR_TSV_STACK [when=S] {
spyv;
MCS.ATTR_EFF_DRAM_TRFC_DLR[def_PORT_INDEX];
}
# RPC0 SCOM REGISTER #
ispy MCP.PORT0.SRQ.PC.MBARPC0Q_CFG_PUP_PDN [when=S] { # tCKE
spyv, expr;
5, (def_MSS_FREQ_EQ_1866==1);
6, (def_MSS_FREQ_EQ_2133==1);
6, (def_MSS_FREQ_EQ_2400==1);
7, (def_MSS_FREQ_EQ_2667==1);
}
ispy MCP.PORT0.SRQ.PC.MBARPC0Q_CFG_PDN_PUP [when=S] { # tPD
spyv, expr;
5, (def_MSS_FREQ_EQ_1866==1);
6, (def_MSS_FREQ_EQ_2133==1);
6, (def_MSS_FREQ_EQ_2400==1);
7, (def_MSS_FREQ_EQ_2667==1);
}
ispy MCP.PORT0.SRQ.PC.MBARPC0Q_CFG_PUP_AVAIL [when=S] { # tXP
spyv, expr;
6, (def_MSS_FREQ_EQ_1866==1);
7, (def_MSS_FREQ_EQ_2133==1);
8, (def_MSS_FREQ_EQ_2400==1);
9, (def_MSS_FREQ_EQ_2667==1);
}
# STR0 SCOM REGISTER #
ispy MCP.PORT0.SRQ.PC.MBASTR0Q_CFG_TCKSRE [when=S] {
spyv, expr;
10, (def_MSS_FREQ_EQ_1866==1);
11, (def_MSS_FREQ_EQ_2133==1);
12, (def_MSS_FREQ_EQ_2400==1);
14, (def_MSS_FREQ_EQ_2667==1);
}
ispy MCP.PORT0.SRQ.PC.MBASTR0Q_CFG_TCKSRX [when=S] {
spyv, expr;
10, (def_MSS_FREQ_EQ_1866==1);
11, (def_MSS_FREQ_EQ_2133==1);
12, (def_MSS_FREQ_EQ_2400==1);
14, (def_MSS_FREQ_EQ_2667==1);
}
ispy MCP.PORT0.SRQ.PC.MBASTR0Q_CFG_TCKESR [when=S] {
spyv;
5;
}
ispy MCP.PORT0.SRQ.PC.MBASTR0Q_CFG_TXSDLL [when=S] {
spyv, expr;
597, (def_MSS_FREQ_EQ_1866==1);
768, (def_MSS_FREQ_EQ_2133==1);
768, (def_MSS_FREQ_EQ_2400==1);
939, (def_MSS_FREQ_EQ_2667==1);
}
# Make Safe Refresh Match Refresh Interval
ispy MCP.PORT0.SRQ.PC.MBASTR0Q_CFG_SAFE_REFRESH_INTERVAL [when=S] {
spyv;
def_REFRESH_INTERVAL;
}
# CID
# Slot 0
ispy MCP.PORT0.SRQ.MBA_FARB1Q_CFG_SLOT0_S0_CID [when=S] {
spyv;
0b000;
}
ispy MCP.PORT0.SRQ.MBA_FARB1Q_CFG_SLOT0_S1_CID [when=S] {
spyv;
0b100;
}
ispy MCP.PORT0.SRQ.MBA_FARB1Q_CFG_SLOT0_S2_CID [when=S] {
spyv;
0b010;
}
ispy MCP.PORT0.SRQ.MBA_FARB1Q_CFG_SLOT0_S3_CID [when=S] {
spyv;
0b110;
}
ispy MCP.PORT0.SRQ.MBA_FARB1Q_CFG_SLOT0_S4_CID [when=S] {
spyv, expr;
0b001, (def_SLOT0_DRAM_STACK_HEIGHT == 8);
0b000, (def_SLOT0_DRAM_STACK_HEIGHT != 8);
}
ispy MCP.PORT0.SRQ.MBA_FARB1Q_CFG_SLOT0_S5_CID [when=S] {
spyv, expr;
0b101, (def_SLOT0_DRAM_STACK_HEIGHT == 8);
0b100, (def_SLOT0_DRAM_STACK_HEIGHT != 8);
}
ispy MCP.PORT0.SRQ.MBA_FARB1Q_CFG_SLOT0_S6_CID [when=S] {
spyv, expr;
0b011, (def_SLOT0_DRAM_STACK_HEIGHT == 8);
0b010, (def_SLOT0_DRAM_STACK_HEIGHT != 8);
}
ispy MCP.PORT0.SRQ.MBA_FARB1Q_CFG_SLOT0_S7_CID [when=S] {
spyv, expr;
0b111, (def_SLOT0_DRAM_STACK_HEIGHT == 8);
0b110, (def_SLOT0_DRAM_STACK_HEIGHT != 8);
}
# Slot 1
ispy MCP.PORT0.SRQ.MBA_FARB1Q_CFG_SLOT1_S0_CID [when=S] {
spyv;
0b000;
}
ispy MCP.PORT0.SRQ.MBA_FARB1Q_CFG_SLOT1_S1_CID [when=S] {
spyv;
0b100;
}
ispy MCP.PORT0.SRQ.MBA_FARB1Q_CFG_SLOT1_S2_CID [when=S] {
spyv;
0b010;
}
ispy MCP.PORT0.SRQ.MBA_FARB1Q_CFG_SLOT1_S3_CID [when=S] {
spyv;
0b110;
}
ispy MCP.PORT0.SRQ.MBA_FARB1Q_CFG_SLOT1_S4_CID [when=S] {
spyv, expr;
0b001, (def_SLOT1_DRAM_STACK_HEIGHT == 8);
0b000, (def_SLOT1_DRAM_STACK_HEIGHT != 8);
}
ispy MCP.PORT0.SRQ.MBA_FARB1Q_CFG_SLOT1_S5_CID [when=S] {
spyv, expr;
0b101, (def_SLOT1_DRAM_STACK_HEIGHT == 8);
0b100, (def_SLOT1_DRAM_STACK_HEIGHT != 8);
}
ispy MCP.PORT0.SRQ.MBA_FARB1Q_CFG_SLOT1_S6_CID [when=S] {
spyv, expr;
0b011, (def_SLOT1_DRAM_STACK_HEIGHT == 8);
0b010, (def_SLOT1_DRAM_STACK_HEIGHT != 8);
}
ispy MCP.PORT0.SRQ.MBA_FARB1Q_CFG_SLOT1_S7_CID [when=S] {
spyv, expr;
0b111, (def_SLOT1_DRAM_STACK_HEIGHT == 8);
0b110, (def_SLOT1_DRAM_STACK_HEIGHT != 8);
}
# ODT RD
# Slot 0
ispy MCP.PORT0.SRQ.MBA_FARB2Q_CFG_RANK0_RD_ODT [when=S] {
spyv;
MCS.ATTR_MSS_VPD_MT_ODT_RD[def_PORT_INDEX][0][0];
}
ispy MCP.PORT0.SRQ.MBA_FARB2Q_CFG_RANK1_RD_ODT [when=S] {
spyv;
MCS.ATTR_MSS_VPD_MT_ODT_RD[def_PORT_INDEX][0][1];
}
ispy MCP.PORT0.SRQ.MBA_FARB2Q_CFG_RANK2_RD_ODT [when=S] {
spyv;
MCS.ATTR_MSS_VPD_MT_ODT_RD[def_PORT_INDEX][0][2];
}
ispy MCP.PORT0.SRQ.MBA_FARB2Q_CFG_RANK3_RD_ODT [when=S] {
spyv;
MCS.ATTR_MSS_VPD_MT_ODT_RD[def_PORT_INDEX][0][3];
}
# Slot 1
ispy MCP.PORT0.SRQ.MBA_FARB2Q_CFG_RANK4_RD_ODT [when=S] {
spyv;
MCS.ATTR_MSS_VPD_MT_ODT_RD[def_PORT_INDEX][1][0];
}
ispy MCP.PORT0.SRQ.MBA_FARB2Q_CFG_RANK5_RD_ODT [when=S] {
spyv;
MCS.ATTR_MSS_VPD_MT_ODT_RD[def_PORT_INDEX][1][1];
}
ispy MCP.PORT0.SRQ.MBA_FARB2Q_CFG_RANK6_RD_ODT [when=S] {
spyv;
MCS.ATTR_MSS_VPD_MT_ODT_RD[def_PORT_INDEX][1][2];
}
ispy MCP.PORT0.SRQ.MBA_FARB2Q_CFG_RANK7_RD_ODT [when=S] {
spyv;
MCS.ATTR_MSS_VPD_MT_ODT_RD[def_PORT_INDEX][1][3];
}
# ODT WR
# Slot 0
ispy MCP.PORT0.SRQ.MBA_FARB2Q_CFG_RANK0_WR_ODT [when=S] {
spyv;
MCS.ATTR_MSS_VPD_MT_ODT_WR[def_PORT_INDEX][0][0];
}
ispy MCP.PORT0.SRQ.MBA_FARB2Q_CFG_RANK1_WR_ODT [when=S] {
spyv;
MCS.ATTR_MSS_VPD_MT_ODT_WR[def_PORT_INDEX][0][1];
}
ispy MCP.PORT0.SRQ.MBA_FARB2Q_CFG_RANK2_WR_ODT [when=S] {
spyv;
MCS.ATTR_MSS_VPD_MT_ODT_WR[def_PORT_INDEX][0][2];
}
ispy MCP.PORT0.SRQ.MBA_FARB2Q_CFG_RANK3_WR_ODT [when=S] {
spyv;
MCS.ATTR_MSS_VPD_MT_ODT_WR[def_PORT_INDEX][0][3];
}
# Slot 1
ispy MCP.PORT0.SRQ.MBA_FARB2Q_CFG_RANK4_WR_ODT [when=S] {
spyv;
MCS.ATTR_MSS_VPD_MT_ODT_WR[def_PORT_INDEX][1][0];
}
ispy MCP.PORT0.SRQ.MBA_FARB2Q_CFG_RANK5_WR_ODT [when=S] {
spyv;
MCS.ATTR_MSS_VPD_MT_ODT_WR[def_PORT_INDEX][1][1];
}
ispy MCP.PORT0.SRQ.MBA_FARB2Q_CFG_RANK6_WR_ODT [when=S] {
spyv;
MCS.ATTR_MSS_VPD_MT_ODT_WR[def_PORT_INDEX][1][2];
}
ispy MCP.PORT0.SRQ.MBA_FARB2Q_CFG_RANK7_WR_ODT [when=S] {
spyv;
MCS.ATTR_MSS_VPD_MT_ODT_WR[def_PORT_INDEX][1][3];
}
####################################################
# DD1 WORKAROUNDS
####################################################
# Force clock enable high DD1 Periodics Issue
espy MCP.PORT0.SRQ.MBA_FARB0Q_CFG_OE_ALWAYS_ON [when=S]{
spyv;
ON;
}
# Epsilon Settings per Power Bus Spreadsheet
ispy MC01.PORT0.ATCL.CL.CLSCOM.MCEPSQ_JITTER_EPSILON [when=S] {
spyv;
0x1;
}
ispy MC01.PORT0.ATCL.CL.CLSCOM.MCEPSQ_LOCAL_NODE_EPSILON [when=S] {
spyv;
SYS.ATTR_PROC_EPS_READ_CYCLES_T0 / 4;
}
ispy MC01.PORT0.ATCL.CL.CLSCOM.MCEPSQ_NEAR_NODAL_EPSILON [when=S] {
spyv;
SYS.ATTR_PROC_EPS_READ_CYCLES_T1 / 4;
}
ispy MC01.PORT0.ATCL.CL.CLSCOM.MCEPSQ_REMOTE_NODAL_EPSILON [when=S] {
spyv;
SYS.ATTR_PROC_EPS_READ_CYCLES_T2 / 4;
}
ispy MC01.PORT0.ATCL.CL.CLSCOM.MCEPSQ_GROUP_EPSILON [when=S] {
spyv;
SYS.ATTR_PROC_EPS_READ_CYCLES_T1 / 4;
}
ispy MC01.PORT0.ATCL.CL.CLSCOM.MCEPSQ_VECTOR_GROUP_EPSILON [when=S] {
spyv;
SYS.ATTR_PROC_EPS_READ_CYCLES_T2 / 4;
}
# HW366164 - SRQ Fullness Control
ispy MC01.PORT0.ATCL.CL.CLSCOM.MCPERF2_SQ_LFSR_CNTL [when=S] {
spyv;
0b0100;
}
# Number of RMW buffers available
ispy MC01.PORT0.ATCL.CL.CLSCOM.MCPERF2_NUM_RMW_BUF [when=S] {
spyv;
0b11100;
}
# All rctrl ops through tag FIFO (bit 0)
# Serialize CMDLIST pf drop through rctrl (bit 1)
# (bit 0 keep at 0)
ispy MC01.PORT0.ATCL.CL.CLSCOM.MCPERF2_RCTRL_CONFIG [when=S] {
spyv;
0b110;
}
# Max 24 64-byte read buffers (HW375534)
ispy MCP.PORT0.SRQ.MBA_RRQ0Q_CFG_RDBUFF_CAPACITY_LIMIT [when=S] {
spyv;
0b011000;
}
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