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--- s1.act_OLD 2013-01-31 08:45:48.124017093 -0600
+++ s1.act 2013-01-31 08:50:03.124226895 -0600
@@ -35,6 +35,8 @@
# F865077 dsanner 01/04/13 Actions for EX based on Gard mask
# SW180860 thi 01/07/13 Actions for proc_start_clock_chiplets v1.10
# D865847 andrewg 01/08/13 Set e0001, bit 0 in master to 0 on sbe start
+# D867908 andrewg 01/23/13 Fix clock states on proc 1
+# SW185124 thi 01/31/13 Add dmi pll lock action
CAUSE_EFFECT {
LABEL=[Assert all logic clock domains off when chip logic power asserted off]
@@ -83,7 +85,9 @@
EFFECT: TARGET=[FSIMBOX(0x1C)] OP=[OR,BUF] DATA=[LITERAL(64,000FFFFF 00000000)]
#Also has effect of causing clocks on
- EFFECT: TARGET=[REG(0x08030008)] OP=[EQUALTO,BUF] DATA=[LITERAL(64,000007FF FFFFFFFF)]
+ EFFECT: TARGET=[REG(0x08030008)] OP=[EQUALTO,BUF] DATA=[LITERAL(64,007FFFFF FFFFFFFF)]
+ EFFECT: TARGET=[REG(0x04030008)] OP=[EQUALTO,BUF] DATA=[LITERAL(64,00003FFF FFFFFFFF)]
+ EFFECT: TARGET=[REG(0x09030008)] OP=[EQUALTO,BUF] DATA=[LITERAL(64,000E07FF FFFFFFFF)]
EFFECT: TARGET=[LOGIC(0xFF000001)] OP=[EQUALTO,BUF] DATA=[LITERAL(64,0xFDB40000 0x00000001)]
EFFECT: TARGET=[LOGIC(0xFF0CC005)] OP=[BIT,ON] BIT=[1] #Trigger updates to EX state
}
@@ -870,13 +874,14 @@
WATCH=[REG(0x020F0013)]
CAUSE: TARGET=[REG(0x020F0013)] OP=[EQUALTO,BUF] DATA=[LITERAL(64,F7FFFFFF FFFFFFFF)]
EFFECT: TARGET=[REG(0x020F0019)] OP=[BIT,ON] BIT=[0] # PLL Lock
+ EFFECT: TARGET=[REG(0x020F0019)] OP=[BIT,ON] BIT=[1] # PLL Lock
}
CAUSE_EFFECT {
LABEL=[P8 PCIE PLL Lock]
WATCH=[REG(0x090F0013)]
CAUSE: TARGET=[REG(0x090F0013)] OP=[EQUALTO,BUF] DATA=[LITERAL(64,F7FFFFFF FFFFFFFF)]
- EFFECT: TARGET=[REG(0x090F0019)] OP=[BIT,ON] BIT=[0] # PLL Lock
+ EFFECT: TARGET=[REG(0x090F0019)] OP=[BIT,ON] BIT=[0] # PLL Lock
}
### END PLL Lock actions ###
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