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This is an automatically generated prolog.
$SOURCE_BEGIN_TAG $filename $SOURCE_END_TAG
OpenPOWER $projectName Project
$copyrightStr $copyrightYear
$copyright_Contributors
Copyright (c) 2019 SMART Modular Technologies, Inc.
All Rights Reserved.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
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