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* Automatically include config.hDan Crowell2019-12-061-1/+0
| | | | | | | | | | | | | | | | | | Rather than having to remember to include config.h anywhere we reference a CONFIG variable (and usually forgetting), this adds it to the default compiler flags so that it gets included in every source file we build. Change-Id: I53622ab4d46c55d942e98cae6ec03049fd5b3d08 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/87475 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Zachary Clark <zach@ibm.com> Reviewed-by: Roland Veloz <rveloz@us.ibm.com> Reviewed-by: Christian R Geddes <crgeddes@us.ibm.com> Reviewed-by: Nicholas E Bofferding <bofferdn@us.ibm.com>
* Make MCS acker workaround changes permanentCorey Swenson2019-02-041-9/+9
| | | | | | | | | | | | | | | | | Workaround moved the p9_revert_sbe_mcs_setup HWP from istep06 to istep14. Remove call_host_revert_sbe_mcs_setup.C from istep06 and remove workaround comments in istep14. Change-Id: I93c70364b7dde013bf003cf1920535ba78b9a58b RTC:184860 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/70792 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com> Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com> Reviewed-by: Matt Derksen <mderkse1@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* Secure Boot: Implement Centaur SCOM cacheNick Bofferding2018-05-081-0/+15
| | | | | | | | | | | | | | | | | | | This change implements a Centaur SCOM cache for sensitive SCOM registers. The cache is initialized and enabled before the first Centaur SCOM, and disabled just prior to locking down the Centaur configuration. Once the Centaur has been locked down, the real register values are compared to the cache entries, and the Centaur is deconfigured (not garded) on any mismatch in assumptions. RTC: 187288 Change-Id: I7b13bfd7eb6b427aba115d6944958bf55e171008 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/57532 Reviewed-by: ILYA SMIRNOV <ismirno@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Michael Baiocchi <mbaiocch@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* Secure Boot: Secure Centaurs in istep 14.5Nick Bofferding2018-05-071-1/+64
| | | | | | | | | | | | | | | | | If secureboot is enabled, call HWP in istep 14.5 to secure the Centaurs. The HWP will set protection bits in the Centaur that cannot be reversed without a full re-init of the chip. Change-Id: I8f72a11b3b79df4bd9dbd6869f525d8271d36887 RTC: 187288 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/55951 Reviewed-by: ILYA SMIRNOV <ismirno@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com> Reviewed-by: Michael Baiocchi <mbaiocch@us.ibm.com> Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* Leave MCS acker open until Istep14Corey Swenson2018-01-121-1/+45
| | | | | | | | | | | | | | | | New MCD changes require a HB workaround. Moved p9_revert_sbe_mcs_setup HWP from Istep06 to Istep14. Change-Id: If42b90127a1f0fb90003e7e6c147c94909d2a487 CMVC-Prereq: 1042570 CMVC-Coreq: 1042845 Backport: release-fips910 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/51744 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Reviewed-by: Dean Sanner <dsanner@us.ibm.com> Reviewed-by: William G. Hoffa <wghoffa@us.ibm.com> Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* L2 HWP -- p9_setup_barsJoe McGill2016-08-251-13/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | p9_setup_bars initial relase -- program FSP/PSI/NPU BARs & configure MCD nest_attributes proc_setup_bars_attributes adjust scope of BAR base address attributes from chip->system change to reflect offset from base of chip address range, rather than absolute address p9_fbc_utils modify p9_fbc_utils_get_chip_base_address() to output base of each on chip region, consider policy affecting placement of mirrrored memory p9_mss_eff_grouping p9_sbe_load_bootloader p9_sbe_mcs_setup adapt to p9_fbc_utils_get_chip_base_address() changes p9_sbe_scominit adapt to p9_fbc_utils_get_chip_base_address() / attribute scope changes add placeholder for FIR register initialization p9_pcie_config adapt to p9_fbc_utils_get_chip_base_address() / attribute scope changes skip programming of INT resources Change-Id: I62e1766fbe8366168cc3f1b9b43c64f48659aec0 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/27841 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Reviewed-by: Peng Fei Gou <shgoupf@cn.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Thi N. Tran <thi@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/27850 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* Enable the hwp p9_mss_setup_barsAndres Lugo-Reyes2016-05-241-4/+3
| | | | | | | | | | | Change-Id: I17f18ca185e947748c20c92c33230f82199503cd RTC:134082 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/24555 Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com> Tested-by: Jenkins Server Reviewed-by: Matt Derksen <v2cibmd@us.ibm.com> Tested-by: FSP CI Jenkins Reviewed-by: William G. Hoffa <wghoffa@us.ibm.com>
* Istep 14 Infrastructure and memory attribute additioncrgeddes2016-05-061-108/+39
| | | | | | | | | | | | | | | This commit turns on a lot of functionality for istep 14. In addition it updates HB's attributes with the new memory fapi attributes after this commit memory_mcs_attributes.xml , memory_spd_attributes.xml , and p9_htm_setup_attributes.xml can be mirrored from the ekb. RTC: 134082 Change-Id: If09e3089eef110517002abcd78d4c6368aa0a8e7 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/24001 Tested-by: Jenkins Server Tested-by: FSP CI Jenkins Reviewed-by: Andres A. Lugo-Reyes <aalugore@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* P9 Isteps: Created directory structure for istep 14 wrappersPrachi Gupta2015-12-111-0/+225
Change-Id: Idad8c430afef013a91e0c206d4fff80fc45053c0 RTC:137652 Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/21501 Tested-by: Jenkins Server Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
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