summaryrefslogtreecommitdiffstats
path: root/src/usr/diag/prdf
Commit message (Expand)AuthorAgeFilesLines
* PRD: Row Repair adjust for MBA Port 1 inversionCaleb Palmer2018-11-011-0/+10
* PRD: Increment addr to next row for VCM row repairCaleb Palmer2018-10-2914-55/+296
* PRD: Row repair fix checking dram for prev repairCaleb Palmer2018-10-181-1/+1
* PRD: wrong target used in PLL analysis codeZane Shelley2018-10-181-3/+3
* PRD: Add Row Repair VPD data to errlCaleb Palmer2018-10-158-1/+188
* PRD: removed default resolution due to problems with CS filterZane Shelley2018-10-151-1/+11
* PRD: PM error log parser updatesZane Shelley2018-10-101-13/+32
* PRD: Fixes for MBS timeout casesCaleb Palmer2018-10-086-6/+235
* PRD: Request SW dump type for unhandled core checkstopsBenjamin Weisenbeck2018-10-082-7/+7
* PRD: Correct interpretation of PLL error bits in TP error registerBenjamin Weisenbeck2018-10-081-6/+44
* PRD: ATTR_EFF_DRAM_ROWS and ATTR_EFF_DRAM_COLS not used on NimbusZane Shelley2018-10-083-45/+28
* PRD: obus extra signaturesZane Shelley2018-10-041-0/+3
* PRD: Capture extra FFDC for current memory mirroring configZane Shelley2018-10-014-1/+36
* PRD: change register used to query for active chnl fail attnZane Shelley2018-10-011-2/+10
* PRD: Updates for PM ffdc parserBenjamin Weisenbeck2018-09-263-34/+85
* PRD: updates to sync the XML with actual values from hardwareZane Shelley2018-09-267-32/+30
* PRD: Fix inputted DRAM pos for row repairCaleb Palmer2018-09-264-2/+48
* PRD: Distinguish hard obus link failures from predictive calloutsBenjamin Weisenbeck2018-09-263-25/+64
* PRD: Make predictive callout on L3 multi bitline failsBenjamin Weisenbeck2018-09-173-4/+34
* PRD: Fix lane repair FFDC for XBUS clock 1 domainZane Shelley2018-09-171-2/+5
* PRD: Add all relevant callouts for SMP interface errorsBenjamin Weisenbeck2018-09-171-3/+4
* PRD: add 'max spares exceeded' attentions to checkstop root causeZane Shelley2018-09-132-2/+2
* PRD: lane repair virtual registers for DMI targetZane Shelley2018-09-131-0/+36
* PRD: better isolation for RCD parity errors and channel failuresZane Shelley2018-09-106-295/+349
* PRD: Handle chips with different MF clock sourcesBenjamin Weisenbeck2018-08-311-3/+79
* Deconfig EC/EX/EQ at runtimeRoland Veloz2018-08-301-3/+4
* PRD: fix input parameters for lane repair power down HWPsZane Shelley2018-08-291-6/+6
* PRD: RX trgt used for TX trgt in XBUS lane repair VPD writeZane Shelley2018-08-251-1/+1
* PRD: give MC chiplets priority for channel failure analysisZane Shelley2018-08-251-1/+2
* PRD: fixed priority of PreAnalysis functionZane Shelley2018-08-253-51/+53
* PRD: Add parser for power management recovery FFDCBenjamin Weisenbeck2018-08-236-4/+635
* PRD: Fix MF ref failover error signatureBenjamin Weisenbeck2018-08-231-3/+3
* PRD: Simplified System::Analyze() interfaceZane Shelley2018-08-233-54/+56
* PRD: handle write blocked RC when clearing chip mark on MBAZane Shelley2018-08-231-5/+40
* PRD: Separate PLL handling by domain typeBenjamin Weisenbeck2018-08-233-100/+100
* PRD: Row Repair VCM UpdatesCaleb Palmer2018-08-235-44/+334
* PRDF: Add utilities for checking dram sparesCaleb Palmer2018-08-234-39/+177
* PRD: Add MemRowRepair classCaleb Palmer2018-08-218-16/+539
* PRD: added PlatServices::isRowRepairEnabled()Zane Shelley2018-08-167-9/+129
* PRD: linker issue with template specializations in VcmEvent classZane Shelley2018-08-164-54/+40
* PRD: resume command support in VcmEvent for Row RepairZane Shelley2018-08-156-162/+226
* PRD: resume super fast read support for Row RepairZane Shelley2018-08-155-71/+300
* PRD: Adjust core checkstop handling for EX rt deconfigBenjamin Weisenbeck2018-08-152-5/+10
* PRD: Sys/PCI oscillator failover thresholdingZane Shelley2018-08-081-0/+6
* PRD: getScom() retry for HBRT channel failuresZane Shelley2018-08-061-13/+43
* PRD: Fix makefile for PllPostAnalysisBenjamin Weisenbeck2018-08-061-0/+1
* PRD: add lane repair extra signatures to appropriate targetsZane Shelley2018-08-016-7/+41
* PRD: change threshold for L3FIR[28] LRU parity errorZane Shelley2018-07-311-1/+1
* PRD: Add core scratch register 3 to FFDCZane Shelley2018-07-271-0/+10
* PRD: segfault in PLL domain codeZane Shelley2018-07-271-10/+11
OpenPOWER on IntegriCloud