summaryrefslogtreecommitdiffstats
path: root/src/usr/diag/prdf/common
Commit message (Expand)AuthorAgeFilesLines
...
* PRD: rule and action file support for ExplorerZane Shelley2018-11-302-0/+1633
* PRD: updates to the XML parser for centaurZane Shelley2018-11-302-5/+15
* PRD: Fixed last functional core function for P9Zane Shelley2018-11-272-10/+10
* PRD: Initial Axone rule filesZane Shelley2018-11-2727-2/+15927
* PRD: separated NPU registers and actions into separate rule filesZane Shelley2018-11-167-663/+722
* PRD: Fixed XML parser for summary analysisZane Shelley2018-11-1623-30/+220
* PRD: update filter parsing in XML parserZane Shelley2018-11-1626-216/+531
* PRD: Rule file updates for CentaurZane Shelley2018-11-163-91/+106
* PRD: updates from XML and XML parserZane Shelley2018-11-1621-351/+286
* Pushing HB plugins and related files for building errltoolVenkatesh Sainath2018-11-152-0/+8
* PRD: rule file updates for XML parsing toolZane Shelley2018-11-1218-156/+236
* PRD: Updates from the RAS XMLZane Shelley2018-11-1226-197/+170
* PRD: Fix compile warning for Centaur extra signaturesZane Shelley2018-11-084-1/+124
* PRD: Remove remaining P8 codeZane Shelley2018-11-0834-16885/+0
* PRD: Fixed TOD register capturingZane Shelley2018-11-071-3/+1
* PRD: Created Centaur specific rule filesZane Shelley2018-11-0716-102/+102
* PRD: Created Nimbus specific rule filesZane Shelley2018-11-0726-165/+165
* PRD: Created Cumulus specific rule filesZane Shelley2018-11-0726-230/+5399
* PRD: Make getDimmSlct/Port genericCaleb Palmer2018-11-055-70/+20
* PRD: Axone GetConnected supportCaleb Palmer2018-11-012-27/+114
* PRD: Support for new Axone domainsCaleb Palmer2018-11-017-3/+321
* PRD: prep splitting rule files by chip modelZane Shelley2018-11-0140-68/+67
* PRD: Row Repair adjust for MBA Port 1 inversionCaleb Palmer2018-11-011-0/+10
* PRD: Increment addr to next row for VCM row repairCaleb Palmer2018-10-292-6/+86
* PRD: wrong target used in PLL analysis codeZane Shelley2018-10-181-3/+3
* PRD: Add Row Repair VPD data to errlCaleb Palmer2018-10-158-1/+188
* PRD: removed default resolution due to problems with CS filterZane Shelley2018-10-151-1/+11
* PRD: PM error log parser updatesZane Shelley2018-10-101-13/+32
* PRD: Fixes for MBS timeout casesCaleb Palmer2018-10-086-6/+235
* PRD: Request SW dump type for unhandled core checkstopsBenjamin Weisenbeck2018-10-081-7/+4
* PRD: Correct interpretation of PLL error bits in TP error registerBenjamin Weisenbeck2018-10-081-6/+44
* PRD: ATTR_EFF_DRAM_ROWS and ATTR_EFF_DRAM_COLS not used on NimbusZane Shelley2018-10-082-35/+24
* PRD: obus extra signaturesZane Shelley2018-10-041-0/+3
* PRD: Capture extra FFDC for current memory mirroring configZane Shelley2018-10-014-1/+36
* PRD: change register used to query for active chnl fail attnZane Shelley2018-10-011-2/+10
* PRD: Updates for PM ffdc parserBenjamin Weisenbeck2018-09-263-34/+85
* PRD: updates to sync the XML with actual values from hardwareZane Shelley2018-09-267-32/+30
* PRD: Fix inputted DRAM pos for row repairCaleb Palmer2018-09-263-1/+46
* PRD: Distinguish hard obus link failures from predictive calloutsBenjamin Weisenbeck2018-09-263-25/+64
* PRD: Make predictive callout on L3 multi bitline failsBenjamin Weisenbeck2018-09-173-4/+34
* PRD: Fix lane repair FFDC for XBUS clock 1 domainZane Shelley2018-09-171-2/+5
* PRD: Add all relevant callouts for SMP interface errorsBenjamin Weisenbeck2018-09-171-3/+4
* PRD: add 'max spares exceeded' attentions to checkstop root causeZane Shelley2018-09-132-2/+2
* PRD: lane repair virtual registers for DMI targetZane Shelley2018-09-131-0/+36
* PRD: better isolation for RCD parity errors and channel failuresZane Shelley2018-09-106-295/+349
* PRD: Handle chips with different MF clock sourcesBenjamin Weisenbeck2018-08-311-3/+79
* PRD: fix input parameters for lane repair power down HWPsZane Shelley2018-08-291-6/+6
* PRD: RX trgt used for TX trgt in XBUS lane repair VPD writeZane Shelley2018-08-251-1/+1
* PRD: give MC chiplets priority for channel failure analysisZane Shelley2018-08-251-1/+2
* PRD: fixed priority of PreAnalysis functionZane Shelley2018-08-253-51/+53
OpenPOWER on IntegriCloud