Commit message (Expand) | Author | Age | Files | Lines | |
---|---|---|---|---|---|
* | PRD: prep splitting rule files by chip model | Zane Shelley | 2018-11-01 | 1 | -1270/+0 |
* | PRD: Separate PLL handling by domain type | Benjamin Weisenbeck | 2018-08-23 | 1 | -0/+7 |
* | PRD: Add core scratch register 3 to FFDC | Zane Shelley | 2018-07-27 | 1 | -0/+10 |
* | PRD: missing TP_LFIR_MASK_OR registers in rule code | Zane Shelley | 2018-04-22 | 1 | -1/+13 |
* | PRD: TOD fault analysis | Benjamin Weisenbeck | 2018-04-20 | 1 | -79/+132 |
* | PRD: add c_err_rpt registers for INTCQFIR | Zane Shelley | 2018-03-21 | 1 | -0/+221 |
* | PRD: extra FFDC for NPU0FIR | Zane Shelley | 2018-03-09 | 1 | -37/+589 |
* | PRD: Add regs to capture list for NVLINK analysis | Brian Stegmiller | 2018-03-01 | 1 | -0/+89 |
* | PRD: Define extra registers for Cumulus chip | Benjamin Weisenbeck | 2018-01-16 | 1 | -0/+326 |