| Commit message (Collapse) | Author | Age | Files | Lines |
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Rather than having to remember to include config.h anywhere
we reference a CONFIG variable (and usually forgetting),
this adds it to the default compiler flags so that it
gets included in every source file we build.
Change-Id: I53622ab4d46c55d942e98cae6ec03049fd5b3d08
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/87475
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Zachary Clark <zach@ibm.com>
Reviewed-by: Roland Veloz <rveloz@us.ibm.com>
Reviewed-by: Christian R Geddes <crgeddes@us.ibm.com>
Reviewed-by: Nicholas E Bofferding <bofferdn@us.ibm.com>
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When we take machine checks in hostboot we will escalate them to a
checkstop by setting bit 31 in the PB Fir reg 0x5012000. This is
done via xscom in some kernel code. There were 2 bugs found in this
path. The first was in how we were calculating the MMIO addressed
used to perform the xscom. The other issue was that we were not
forcing the kernel code to perform a cache-inhibited store. This
commit addressed both of these problems.
Change-Id: I41871fa754cbedf4cdb913711ce02a00f0213334
CQ: SW481030
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/87539
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Daniel M Crowell <dcrowell@us.ibm.com>
Reviewed-by: Nicholas E Bofferding <bofferdn@us.ibm.com>
Reviewed-by: William G Hoffa <wghoffa@us.ibm.com>
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This commit fixes a NULL-dereference in the register dump code for the
kernel crash handler. The task pointer can be NULL, in which case we
should not attempt to dump registers.
Change-Id: I3433ca466f34827f102d64ef2aac4fffc5b49b70
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/87422
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: William G Hoffa <wghoffa@us.ibm.com>
Reviewed-by: Nicholas E Bofferding <bofferdn@us.ibm.com>
Reviewed-by: Daniel M Crowell <dcrowell@us.ibm.com>
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Add a printout for a crashed task's general-purpose registers to the
kernel backtrace printout as a debugging aid.
Change-Id: I84d81cc6af679dfc8618145e1f143db7b4b6d9db
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/85925
Reviewed-by: Michael Baiocchi <mbaiocch@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Nicholas E Bofferding <bofferdn@us.ibm.com>
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Axone ended up using the same core as Nimbus so it has the same
bugs.
Change-Id: Ie27b3e49219ce872bbc8dda60aacccbb71093b8c
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/80909
Reviewed-by: Ilya Smirnov <ismirno@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Reviewed-by: Dean Sanner <dsanner@us.ibm.com>
Reviewed-by: Daniel M Crowell <dcrowell@us.ibm.com>
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This commit fixes GCOV code coverage for P9 with GCC 4.9.2
Change-Id: Ie1e7c35f67414531dbd6e7a771ac1529a9ebd59d
RTC: 208351
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/76812
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Reviewed-by: Nicholas E. Bofferding <bofferdn@us.ibm.com>
Reviewed-by: Ilya Smirnov <ismirno@us.ibm.com>
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
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The current read only contraint used to determine when to cast out read only
pages exceeds the maximum LRU value, and thus the required page evictions never
occur. This change decreases the constraint so that it is one less than the
max LRU value.
Change-Id: I9e37067c4ed219458778edce6ab826ef481dbf21
CQ: FW690233
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/76054
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Reviewed-by: Glenn Miles <milesg@ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
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Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Reviewed-by: Michael Baiocchi <mbaiocch@us.ibm.com>
Reviewed-by: Nicholas E. Bofferding <bofferdn@us.ibm.com>
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Fixes a page coalesce bug where the page coalesce routine failed to factor in
the actual start address of the range, and therefore could not coalesce pages
back together correctly. Additionally, decreases the amount of space reserved
for the OCC bootloader from an inadvertent 32k to 4k as intended.
Change-Id: Iffd35560d67f6b2f27daf6dca3dc45a900fb4335
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/75636
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Reviewed-by: Ilya Smirnov <ismirno@us.ibm.com>
Reviewed-by: Michael Baiocchi <mbaiocch@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
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There is a scenario wherein if a PNOR ECC UE occurs when attempting to service a
page fault, the kernel will deadlock when it attempts to kill the task that
triggered the fault. This is due to the kill routine being called while holding
the VMM spinlock and then collecting a backtrace, which also performs
a nested acquire of the same spinlock. This fix inhibits invoking the
backtrace if the kill routine holds the VMM spinlock.
Change-Id: I75bf1f248740a08fd485379d88e146096edf65a9
CQ: SW461429
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/75264
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Ilya Smirnov <ismirno@us.ibm.com>
Reviewed-by: Michael Baiocchi <mbaiocch@us.ibm.com>
Reviewed-by: Matthew Raybuck <matthew.raybuck@ibm.com>
Reviewed-by: William G. Hoffa <wghoffa@us.ibm.com>
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We are memory constrained in some configurations during 10.2
because we are forced to pin large chunks of memory to hold a
few data partitions. In some instances we have run out of free
memory completely. The fact that we don't hit this all the time
indicates it is purely based on timing and the random nature of
page allocations.
A few changes were made to better handle these kinds of low
memory situations:
- Any time we dip into the kernel's private stash of free pages
we will force memory periodics to run. This should free up
some pages so that the kernel's stash can remain full.
- The size of the kernel's private page stash is increased from
4 to 10. We need this larger number due to the increased layers
involved in paging code in/out with secureboot enabled.
- The LRU algorithm was modified to keep pages around longer. A
page will not be evicted under normal circumstances until we go
10 refresh cycles without an access (up from 3). This should
help balance out the increased number of forced periodics that
could now come into play.
Change-Id: I289d866270db9d70cac275d8c98ab185caaade05
CQ: SW458623
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/73189
Reviewed-by: Nicholas E. Bofferding <bofferdn@us.ibm.com>
Reviewed-by: Matt Derksen <mderkse1@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
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This commit fixes a bug wherein, if a task was pinned and then migrated to
master, a page fault to load any instructions after the migrate but before the
unpin, could cause the task to migrate away unexpectedly, causing a range of
symptoms such as not being able to find the master core.
Change-Id: I596f67d678f7641bb51ab9a9a3ae2b3ab65ae9b9
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/73390
Reviewed-by: Michael Baiocchi <mbaiocch@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Matthew Raybuck <matthew.raybuck@ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
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This fix accesses the cpu struct based on current thread
PIR instead of relying on an indirect pointer in the
current task struct. It is attempting to eliminate a
weak consistency/timing issue on the thread wakeups on
the secondary cores.
Given the way hostboot wakes up from the doorbell, there
is a good chunck of code executed prior to the doorbell
interrupt handler --> this also adds a msgsync instruction
in the sreset (0x100) interrupt handler.
Change-Id: I23db1d786a8a8f0637a890e2ac5de6197ee9cabb
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/71582
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Reviewed-by: William G. Hoffa <wghoffa@us.ibm.com>
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Nicholas E. Bofferding <bofferdn@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
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If we hit a situation where we can't allocate a page of memory,
this will force a coalesce (defrag) a few times and then
eventually trigger other memory reclamation actions.
Also tweaked a few spots in the kernel to enhance debug:
- add more stops to look at errors (HB_BREAK_ON_ERROR)
- add more backtrace calls
- add a new debug flag to count the extra coalesce calls
Change-Id: Ibac7079a44a12dc61e41304de4c4ae518c206d13
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/71653
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Reviewed-by: Matt Derksen <mderkse1@us.ibm.com>
Reviewed-by: Nicholas E. Bofferding <bofferdn@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
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We are still seeing some very intermittent errors in the slave
core wakeup path. It still seems like we may have a timing issue.
Until we figure out exactly what is going on, I am adding a retry
mechanism that should get the core to report in correctly. The
retry is done by issuing an additional doorbell message to the
core that didn't report in.
Change-Id: Ib87e5d58e079674d1eebb44c10d0252a35ea0519
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/70761
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Nicholas E. Bofferding <bofferdn@us.ibm.com>
Reviewed-by: Dean Sanner <dsanner@us.ibm.com>
Reviewed-by: William G. Hoffa <wghoffa@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
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POWER9 added a new sync mode called 'msgsync' that is required
to avoid weak consistency issues when you are using doorbell
(msgsnd) functions.
See POWER ISA Section 5.9.2 for details, excerpt here:
The ordering done by sync (and ptesync) provides
the appearance of "causality" across a sequence of
msgsnd instructions, as in the following example.
"msgsnd->T1" means "msgsnd instruction target-
ting thread T1". "<DHDI 0>" means "occurrence of
Directed Hypervisor Doorbell interrupt caused by
msgsnd executed on T0". On T0, register r1 is
assumed to contain the value 1.
T0 T1 T2
std r1,X <DHDI 0> <DHDI 1>
sync msgsnd->T2 msgsync
msgsnd->T1 ld r1,X
In this example, T2's load from X must return 1.
The change here adds the msgsync call to the code that executes
any time we handle a doorbell interrupt. In addition there is a
POWER9 DD2 errata that indicates we also require a lwsync to
ensure consistency.
Change-Id: Ib0f3571926d71efcbffa205093278e2a1d58df85
CQ: SW454611
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/70648
Reviewed-by: Nicholas E. Bofferding <bofferdn@us.ibm.com>
Reviewed-by: Dean Sanner <dsanner@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Reviewed-by: William G. Hoffa <wghoffa@us.ibm.com>
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Add a specific 'istep' MAGIC call that indicates a successful boot
that can be used by the Simics CI suite
Change-Id: If4dcdd7f16d8b630b0200d7d5edc61f473e4e123
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/69580
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
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Due to the way POWER works, there is no guarantee that a memory
location written by 1 thread is actually visible to another thread
unless you explicitly assert a sync of some kind. In the code
that runs to wake up new cores, there is a path where memory
is written by 1 thread (usually on the master processor) but is
immediately consumed by a new thread that just woke up. It is
possible for the new thread to consume the memory and not see
the contents that were written by the other thread.
The fix is to add a sync command before we send the doorbell
msgsnd operation. This will ensure the memory contents are
visible to the thread as soon as it wakes up.
Change-Id: I8a1483dd7bbda5af064ba6d004dc9e0a3a61ce78
CQ: SW453195
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/70311
Reviewed-by: Dean Sanner <dsanner@us.ibm.com>
Reviewed-by: Nicholas E. Bofferding <bofferdn@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
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This is an untested version of the new MMIO device driver that
will give access to the OCMB. It will be tested once the Axone
model IPLs in Simics.
Change-Id: I4bc1d2f7306f1b238d1d65c24462ac4121266b11
RTC: 189447
RTC: 189220
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/66941
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Reviewed-by: Nicholas E. Bofferding <bofferdn@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Matt Derksen <mderkse1@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com>
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This commit implements a compile time feature (set MALLOC_FENCING to
y in the src/lib/HBconfig file) which puts check bytes around each malloc.
Whenever an allocation is freed, if the check bytes have changed, the memory
manager immediate crashes Hostboot. It also fixes a heap corruption in
the SBE get capabilities command.
Change-Id: I3df96d5fce43c34d3574c47f3c674076842d90e1
CQ: SW442980
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/68214
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Ilya Smirnov <ismirno@us.ibm.com>
Reviewed-by: Roland Veloz <rveloz@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
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Change-Id: Iba2230cb79e83bd5b9dc68d95259d730b191ea33
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/63250
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: STEWART E. SMITH <stewart@linux.ibm.com>
Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com>
Reviewed-by: William G. Hoffa <wghoffa@us.ibm.com>
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Support SMF for P9N/P9C. Lots of minor tweaks to make this
work, but the biggest is to run userspace in problem state
This is needed because for SMF Hostboot will need to run in S=1,
HV=0,PR=1 (and kernel in S=1, HV=1, PR=0)
This commit makes P9 HB userpsace run in HV=0 PR=1 and kernel in
HV=1, PR=0.
Change-Id: Ia4771df5e8858c6b7ae54b0746e62b283afb4bc4
RTC: 197243
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/50530
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Reviewed-by: Dean Sanner <dsanner@us.ibm.com>
Reviewed-by: Nicholas E. Bofferding <bofferdn@us.ibm.com>
Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
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- Add the new cpu type, update the pvr checks and other
miscellaneous changes to support a new Axone proc chip type
Change-Id: Ie2541bf826bdff65f6f11b0f16839855d69eb4d6
RTC: 173001
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/64260
Reviewed-by: Matt Derksen <mderkse1@us.ibm.com>
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Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
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Change-Id: I329dd64345f2474cb0dad628ccc2244d85be86c2
CQ: SW429364
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/63147
Reviewed-by: ILYA SMIRNOV <ismirno@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Reviewed-by: Prachi Gupta <pragupta@us.ibm.com>
Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
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Recent changes to direclty use HRMOR for calculating
addresses broke 3 and 4 node configs. This commit
removes the multiplication of _nodal_ HRMOR * group id
(since the _nodal_ HRMOR mechanism now factors that in).
It also uses the IPC addresses to handle start payload,
so math/constants are not used to find master node.
Change-Id: I919783bc60b5e4914c58f80752881fcb15649e95
CQ:SW438196
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/62659
Reviewed-by: Thi N. Tran <thi@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
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Reviewed-by: William G. Hoffa <wghoffa@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/62708
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Memory VPD contents have changed since the cards have been
built so we need to provide a method to override the data
as part of a FW build. We have done the same thing
previously for the MEMD record on the Nimbus machines
so will use the same design here for SPDX.
As part of this change, the previous MEMD support was
refactored to be completely generic so a single code path
can be used for any arbitrary record.
Change-Id: I5af5e965429c881be3de0d18c82b1d7918ac9c22
CQ: SW430659
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/61190
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Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Michael Baiocchi <mbaiocch@us.ibm.com>
Reviewed-by: Nicholas E. Bofferding <bofferdn@us.ibm.com>
Reviewed-by: William G. Hoffa <wghoffa@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/60980
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When a TI occurs during ECC corruption, the kernel asserts as part
of the error flow, and the assert makes it into the TI area before
the ECC error code, which makes it hard to debug the underlying
issue. This change introduces the logging of the TI code to the
HB TI area as part of the doShutdown path and a mechanism to not
overwrite the first logged error code. That way the TI area will
always contain the first error code that caused the TI.
Change-Id: Idcd5727314aea9b92a6eb9d19ec6ed223111861a
CQ:SW431570
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/61661
Reviewed-by: Michael Baiocchi <mbaiocch@us.ibm.com>
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Reviewed-by: William G. Hoffa <wghoffa@us.ibm.com>
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Prior to this change, the assembly code to invoke p9 attentions did not
flush the instruction cache, which led to the alternative behavior of the
attn instruction, namely invoking the hypervisor emulation assistance
interrupt / illegal instruction handler. This caused chaos in the shutdown
path, especially after the CPUs come online in istep 16.
Change-Id: I7c5bf4342a41136e82326da285eed059d4fb17a3
CQ: SW419736
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/61351
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Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
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In order to know where the IPC message of a given node is,
we save off the HRMOR of every node in a hw register.
Originally, we were saving this information in the core
scratch register. Since, the core scratch registers are
wiped off when the cores go into the winkle state, therefore,
we were writing to the register after we come out of winkle.
But, at that point, we ran into race conditions because
other nodes could be ahead and try to access the register
on a node that is not exactly out of winkle yet.
This fixes the problems by using the mbox scratch register
rather than the core scratch register because they are saved
off even when the cores go into winkle state. Because the
registers are preseved, we can set the value prior to
cores coming out of winkle, so, we don't run into the race
condition where one node is trying to read a value prior to
the other one writing the value.
Change-Id: I822bfc8defe09cbb418edc5f36a99b7cd41eec88
CQ:SW435271
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/61093
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Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
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During boot, Hostboot will push key pointers into memory. This
allows the debug tools to find the pointers (using a known static
memory address) to base memory accesses on. This replaces the
existing symbol lookup that we use now. That means we don't
need to have the exact symbol file for the build we're debugging
against.
Change-Id: I4618e15a3dc90acc3a89520a502eb818c1b4258c
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/56097
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There are two main changes in this commit:
1) Forcing an assert if we cannot allocate pages after
10,000 attempts to yield.
2) Adding a backtrace for a lot of exception paths.
Change-Id: I755ada753b78abed56e553f7c669f0f98ae68700
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/58224
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Reviewed-by: Thi N. Tran <thi@us.ibm.com>
Reviewed-by: William G. Hoffa <wghoffa@us.ibm.com>
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Current code has each Node calculate each Remote Node's IPC area
remote address by performing a fixed format calculation.
This change has each Node calculating its IPC area Remote address
and posting this value to a local SCOM register. A Node reads
a Remote Node's SCOM register to acquire the Remote IPC area
address.
Change-Id: I25260ce180e0d07e5e81990d4c1f99e249912491
RTC:191463
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/59177
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Reviewed-by: Prachi Gupta <pragupta@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
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Hostboot code will write the current HRMOR value into core
scratch reg 1 (scom=xx010A87, spr=0x08) at initial boot.
This data is ORed into the memory size data that was already
present. The bootloader code will do the same.
Also updated the debug tools to key off of this data if it
is available to avoid any HRMOR hardcoding.
The purpose of this change is to provide a method for the FSP
code to handle various memory remapping scenarios that are
currently in plan without needing any explicit communication
from Hostboot.
Change-Id: Ia3c81980ebd780ae182956cddae785dd408fbed9
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/59699
Reviewed-by: Prachi Gupta <pragupta@us.ibm.com>
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Reviewed-by: William G. Hoffa <wghoffa@us.ibm.com>
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The heap memory coalesce algorithm previously did not account for the right page
start address and the hole carved out for the page table. This change fixes
both issues
Change-Id: I730b546eb1966051c1d5dd8459d76a7943234bea
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/59813
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Reviewed-by: Nicholas E. Bofferding <bofferdn@us.ibm.com>
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8001 - Tell Simics we are waiting on the FSP
8006 - Tell Simics we shutdown
8020 - Tell Simics which istep we're running
CQ: SW423959
Change-Id: Icea13d2ed7ff73de04400c46b9b1855e94db7c84
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/58104
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Reviewed-by: Hieu C. Nguyen <hieu.nguyen@us.ibm.com>
Reviewed-by: William G. Hoffa <wghoffa@us.ibm.com>
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This reverts commit f5024f66d08a343a40c452d9d86da1cf49998e14.
CQ: SW429535
Change-Id: I60828c8c5f52128e04c3cbac1536bd7969382eaa
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/58968
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Rather than rely on HWSV code to recognize there is a TI with SRC, and so
do a Hostboot dump, just always set the flag in the TI with SRC data that
will request that HWSV to do the HB dump.
Change-Id: Ia7b64b924e7ad8bbbacd4bdc244efaddcaacf148
CQ: SW427305
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/58675
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Reviewed-by: Brian E. Bakke <bbakke@us.ibm.com>
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Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
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- In MPIPL the HW interrupt config could be such that interrupts will
cross node boundaries. HB handles interrupts independently on each
node - so initialize INTRP in a way to handle this transition.
- Modify the MPIPL flow with the following changes:
a) Set the Interrupt LSI State Machine to disabled
b) Enable LSI Mode via the Interrupt Control Register
c) Force all nodes to sync after steps a + b
- Enable INTRP Multi-Node MPIPL Sync Code developed in P8
- Each node will now initialize its own internode_info
data area during an initial IPL
- Coalescing of the Host will modify this data to define
all the nodes in the system
- During the MPIPL each node can view each others area to
determine when all nodes have reached the common sync point
- Remove Legacy P8 MPIPL INTRP Code that is not used
Change-Id: Idb742eafc7389f328ea7f506c4c4541c989e52b6
RTC: 182712
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/57993
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Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com>
Reviewed-by: Richard J. Knight <rjknight@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
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Ran into a case where Hostboot was getting booted with the wrong
fabricid for the node it was on. In the process I realized it
was hard to tell what was going on.
Added printk output to show the PIR of the boot core.
Modified how force-hrmor option is consumed in ecmd-debug-framework
so that you can force unnatural lookups.
Change-Id: I77fc614889aa3cedcc8ccd39cac9ebc36f239b56
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/57910
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Reviewed-by: Martin Gloff <mgloff@us.ibm.com>
Reviewed-by: Prachi Gupta <pragupta@us.ibm.com>
Reviewed-by: Roland Veloz <rveloz@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
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When Hostboot has a TI with a PLID rather than a Reason Code (RC), HWSV does not
attempt the Hostboot Dump. Thought is that happens per the design as the error
log related to the PLID sent by Hostboot should already have the required
information. There are instances where the error log does not have sufficient
data and a dump would be beneficial. A path is being added so an error log can
be flagged as needing a Hostboot dump.
Change-Id: I97972308c70e7210f578fb818563bb9b0cd940b4
CQ: SW420219
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/56600
CI-Ready: Daniel M. Crowell <dcrowell@us.ibm.com>
CI-Ready: Martin Gloff <mgloff@us.ibm.com>
Reviewed-by: Matt Derksen <mderkse1@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
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Reviewed-by: Corey V. Swenson <cswenson@us.ibm.com>
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Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
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PHYP needs a way to know if SBE security backdoor is enabled
for debug purposes. This change creates a flag in TPM instance
data structure to indicate whether the backdoor is enabled. This
flag is passed by SBE to the hb bootloader; also added the flag
to indicate whether PCR is poisoned (default of 0).
The population of this flag will be implemented on Fleetwood.
Change-Id: I22305dbc9651134ba7dfe3b0bd3c760fe53c2c85
RTC: 188961
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/56045
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CI-Ready: Daniel M. Crowell <dcrowell@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
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Default MSR[ME]=0 during initial boot for bootloader and
hostboot kernel
Once the xscom address range has been mapped in, enable the
machine check handler to force a checkstop and set MSR[ME]=1
to allow regular machine check handling
CQ: SW401402
Change-Id: I104e39465e61b3b19d5c073e71271102711ae54f
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/47179
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Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
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- Addresses review comments from original commit
- Adds inband scom multicast workaround
Change-Id: Ia17a8e5359227691464f3552ded585ede771813b
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/55305
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Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Prachi Gupta <pragupta@us.ibm.com>
Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com>
Reviewed-by: William G. Hoffa <wghoffa@us.ibm.com>
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- Add function to compress SCOM address
- Old MCS target is now DMI
- Add istep12 call to enable inband SCOMs
- Set each DMI offset attribute in processMrw
Change-Id: If5171f8da6c58404ac598047ca0177aead048771
RTC:147272
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/54574
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Reviewed-by: Prachi Gupta <pragupta@us.ibm.com>
Reviewed-by: William G. Hoffa <wghoffa@us.ibm.com>
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- Display size of page requested if requested memory
doesn't become available
Change-Id: I5b101ce6650cdc155be276c5d00f95bc35a0ff90
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/54491
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Prachi Gupta <pragupta@us.ibm.com>
Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
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P9 Doorbells operate differently than P8 IPI mechanism, creating
a race condition. Basically because the HB kernel turns a
doorbell into a message, and then is ready for another one -- it
can lose the next one since repeated messages with same key are
dropped (IPC handling clears memory comm area, other HB instances
notice, fill and drop a doorbell before getting back into kernel)
Change-Id: I8eb6f010600afb9de365c8942fcd24227903436f
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/54118
Reviewed-by: Prachi Gupta <pragupta@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: William G. Hoffa <wghoffa@us.ibm.com>
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-Fixed node/group id calculations
-Reduced dbell printk to prevent printk overflow
-Fixed architectual hole in how internode IPC works
Workitems won't work, instead just always check
for IPC on any doorbells to master thread
-Changed PIR tracing to print out in hex
Change-Id: I25eb7f87fd812a90f98a7724b1ac1100f764fe7b
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/53187
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Reviewed-by: Prachi Gupta <pragupta@us.ibm.com>
Reviewed-by: William G. Hoffa <wghoffa@us.ibm.com>
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Dean Sanner <dsanner@us.ibm.com>
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- move p9_fab_iovalid to fab_iovalid common lib
to avoid conflicts with hwp lib
- doorbell_send to wake up the cores in istep18
- move block wakeup interrupts set later in the
istep 18 flow after we have suspended the mbox
and drained the interrupt queue
Change-Id: I241240ca1d1787182c5baaf3bdd10283878d5798
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/52701
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Reviewed-by: SWATHI M. BHATTIPROLU <bhmadhur@in.ibm.com>
Reviewed-by: Sakethan R. Kotta <sakkotta@in.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Martin Gloff <mgloff@us.ibm.com>
Reviewed-by: William G. Hoffa <wghoffa@us.ibm.com>
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- Use doorbells instead of IPIs (no IPI support
using LSI interupts in the XIVE intr architecture)
- New message type from kernel to userspace so the
kernel can notify the HB userspace Interrupt
Resource Provider (INTRP) that an IPC message was
sent to the particular HB instance (in P8 this
happened automatically as that was part of the
IPI architecture).
- Re-enable testcase that validates that an IPC
message can be successfully sent.
Change-Id: Ic846f8dca45217205ed61d8381a573e995cb16f2
RTC: 150861
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/52004
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Prachi Gupta <pragupta@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
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We hit out-of-memory errors while trying to boot a Opal system
due to the large amount of memory used by the PM procedures
and the pinning of memory in secure mode.
Also did some other rearranging of the pinned memory sections
to get some space back.
Change-Id: I61f219d7f32871a39b236d963bae893a6ef0ce0e
CQ: SW413191
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/51724
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Matt Derksen <mderkse1@us.ibm.com>
Reviewed-by: Martin Gloff <mgloff@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
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Change-Id: Iadfded90c09b149948348ee462ab34f9c2431982
RTC: 182134
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/49865
Reviewed-by: Matt Derksen <mderkse1@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com>
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
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