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| author | Bill Hoffa <wghoffa@us.ibm.com> | 2018-08-10 12:39:34 -0500 |
|---|---|---|
| committer | Daniel M. Crowell <dcrowell@us.ibm.com> | 2018-08-20 12:24:28 -0500 |
| commit | 498b466c442549c0bd261ebd149dc7b610fbf2f1 (patch) | |
| tree | 4c8eeed50e6a8d4b10da5957bd6c0f6e314b64a7 /src/kernel | |
| parent | 3341c6aab4fa63296cab262fb89f56e67fa804c6 (diff) | |
| download | talos-hostboot-498b466c442549c0bd261ebd149dc7b610fbf2f1.tar.gz talos-hostboot-498b466c442549c0bd261ebd149dc7b610fbf2f1.zip | |
Base Core/Kernel Changes to Support the Axone Processor Chip
- Add the new cpu type, update the pvr checks and other
miscellaneous changes to support a new Axone proc chip type
Change-Id: Ie2541bf826bdff65f6f11b0f16839855d69eb4d6
RTC: 173001
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/64260
Reviewed-by: Matt Derksen <mderkse1@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Diffstat (limited to 'src/kernel')
| -rw-r--r-- | src/kernel/basesegment.C | 1 | ||||
| -rw-r--r-- | src/kernel/cpuid.C | 5 | ||||
| -rw-r--r-- | src/kernel/cpumgr.C | 1 | ||||
| -rw-r--r-- | src/kernel/exception.C | 1 | ||||
| -rw-r--r-- | src/kernel/misc.C | 3 |
5 files changed, 10 insertions, 1 deletions
diff --git a/src/kernel/basesegment.C b/src/kernel/basesegment.C index 2574c8d6a..59e077b60 100644 --- a/src/kernel/basesegment.C +++ b/src/kernel/basesegment.C @@ -59,6 +59,7 @@ void BaseSegment::_init() case CORE_POWER8_NAPLES: case CORE_POWER9_NIMBUS: case CORE_POWER9_CUMULUS: + case CORE_POWER9_AXONE: default: iv_physMemSize = VMM_BASE_BLOCK_SIZE; break; diff --git a/src/kernel/cpuid.C b/src/kernel/cpuid.C index 8d3555eed..6a67e1516 100644 --- a/src/kernel/cpuid.C +++ b/src/kernel/cpuid.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2011,2017 */ +/* Contributors Listed Below - COPYRIGHT 2011,2018 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -67,6 +67,9 @@ namespace CpuID } } + case PVR_t::P9_AXONE: + return CORE_POWER9_AXONE; + default: return CORE_UNKNOWN; } diff --git a/src/kernel/cpumgr.C b/src/kernel/cpumgr.C index 6ef08051c..c0c1be333 100644 --- a/src/kernel/cpumgr.C +++ b/src/kernel/cpumgr.C @@ -469,6 +469,7 @@ size_t CpuManager::getThreadCount() case CORE_POWER9_NIMBUS: case CORE_POWER9_CUMULUS: + case CORE_POWER9_AXONE: threads = 4; break; diff --git a/src/kernel/exception.C b/src/kernel/exception.C index 8dc4b53e3..d12b6da7d 100644 --- a/src/kernel/exception.C +++ b/src/kernel/exception.C @@ -301,6 +301,7 @@ void kernel_execute_softpatch() case CORE_POWER8_NAPLES: case CORE_POWER9_NIMBUS: case CORE_POWER9_CUMULUS: + case CORE_POWER9_AXONE: case CORE_UNKNOWN: p8_softpatch_denorm_assist(t->fp_context); break; diff --git a/src/kernel/misc.C b/src/kernel/misc.C index c770fc49f..ed964da79 100644 --- a/src/kernel/misc.C +++ b/src/kernel/misc.C @@ -510,6 +510,7 @@ namespace KernelMisc case CORE_POWER8_NAPLES: case CORE_POWER9_NIMBUS: case CORE_POWER9_CUMULUS: + case CORE_POWER9_AXONE: startAddr = reinterpret_cast<uint64_t*> ( VmmManager::INITIAL_MEM_SIZE ) ; endAddr = reinterpret_cast<uint64_t*>(i_expandSize); @@ -574,6 +575,7 @@ namespace KernelMisc break; case CORE_POWER9_NIMBUS: case CORE_POWER9_CUMULUS: + case CORE_POWER9_AXONE: case CORE_UNKNOWN: default: // See EX07.EC.CC.PCC0.COMMON.SPR_COMMON.SCOMC in scomdef for @@ -660,6 +662,7 @@ const char* ProcessorCoreTypeStrings[] "Naples", "Nimbus", "Cumulus", + "Axone", "Unknown" }; |
