| Commit message (Collapse) | Author | Age | Files | Lines |
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This fix accesses the cpu struct based on current thread
PIR instead of relying on an indirect pointer in the
current task struct. It is attempting to eliminate a
weak consistency/timing issue on the thread wakeups on
the secondary cores.
Given the way hostboot wakes up from the doorbell, there
is a good chunck of code executed prior to the doorbell
interrupt handler --> this also adds a msgsync instruction
in the sreset (0x100) interrupt handler.
Change-Id: I23db1d786a8a8f0637a890e2ac5de6197ee9cabb
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/71582
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Reviewed-by: William G. Hoffa <wghoffa@us.ibm.com>
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Nicholas E. Bofferding <bofferdn@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
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Support SMF for P9N/P9C. Lots of minor tweaks to make this
work, but the biggest is to run userspace in problem state
This is needed because for SMF Hostboot will need to run in S=1,
HV=0,PR=1 (and kernel in S=1, HV=1, PR=0)
This commit makes P9 HB userpsace run in HV=0 PR=1 and kernel in
HV=1, PR=0.
Change-Id: Ia4771df5e8858c6b7ae54b0746e62b283afb4bc4
RTC: 197243
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/50530
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Dean Sanner <dsanner@us.ibm.com>
Reviewed-by: Nicholas E. Bofferding <bofferdn@us.ibm.com>
Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
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During boot, Hostboot will push key pointers into memory. This
allows the debug tools to find the pointers (using a known static
memory address) to base memory accesses on. This replaces the
existing symbol lookup that we use now. That means we don't
need to have the exact symbol file for the build we're debugging
against.
Change-Id: I4618e15a3dc90acc3a89520a502eb818c1b4258c
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/56097
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
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Default MSR[ME]=0 during initial boot for bootloader and
hostboot kernel
Once the xscom address range has been mapped in, enable the
machine check handler to force a checkstop and set MSR[ME]=1
to allow regular machine check handling
CQ: SW401402
Change-Id: I104e39465e61b3b19d5c073e71271102711ae54f
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/47179
Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: William G. Hoffa <wghoffa@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
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-Fixed node/group id calculations
-Reduced dbell printk to prevent printk overflow
-Fixed architectual hole in how internode IPC works
Workitems won't work, instead just always check
for IPC on any doorbells to master thread
-Changed PIR tracing to print out in hex
Change-Id: I25eb7f87fd812a90f98a7724b1ac1100f764fe7b
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/53187
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Reviewed-by: Prachi Gupta <pragupta@us.ibm.com>
Reviewed-by: William G. Hoffa <wghoffa@us.ibm.com>
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Dean Sanner <dsanner@us.ibm.com>
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From Linux 80f23935cadb ("powerpc: Convert cmp to cmpd in idle enter sequence"):
PowerPC's "cmp" instruction has four operands. Normally people write
"cmpw" or "cmpd" for the second cmp operand 0 or 1. But, frequently
people forget, and write "cmp" with just three operands.
With older binutils this is silently accepted as if this was "cmpw",
while often "cmpd" is wanted. With newer binutils GAS will complain
about this for 64-bit code. For 32-bit code it still silently assumes
"cmpw" is what is meant.
In this instance the code comes directly from ISA v2.07, including the
cmp, but cmpd is correct. Backport to stable so that new toolchains can
build old kernels.
This is change is a noop with the existing toolchain. We change from
implicitly generating the cmpwi to explicitly stating in for
compatibility with newer toolchains.
With gcc 4.9.3, binutils 2.25.2:
$ cat asm-test.S
.text
.global test
cmpi 0, 8, 1
$ powerpc64-linux-gcc -c asm-test.S
$ objdump -d asm-test.o
0000000000000000 <.text>:
2c 08 00 01 cmpwi r8,1
Old compiler, updated instruction:
$ cat asm-test.S
.text
.global test
cmpwi 0, 8, 1
$ powerpc64-linux-gcc -c asm-test.S
$ objdump -d asm-test.o
0000000000000000 <.text>:
2c 08 00 01 cmpwi r8,1
And then the new toolchain (gcc 6.3.0, binutils 2.28) with the updated
asm:
$ cat asm-test.S
.text
.global test
cmpwi 0, 8, 1
$ powerpc64-linux-gnu-gcc -c asm-test.S
$ objdump -d asm-test.o
0000000000000000 <.text>:
2c 08 00 01 cmpwi r8,1
Change-Id: If981e20a578ec98ede68a31eee2888c27d5c3d10
Signed-off-by: Joel Stanley <joel@jms.id.au>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/42259
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: STEWART E. SMITH <stewart@linux.vnet.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
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Change-Id: I58a382cfc285e37cc8748fe8e23f71c877850263
RTC: 130186
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/816
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
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Change-Id: I4c5ef96c4793f6da26d54d1d61a51f6395e6b34b
Backport: master-p8
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/930
Tested-by: Jenkins Server
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Reviewed-by: William G. Hoffa <wghoffa@us.ibm.com>
Tested-by: FSP CI Jenkins
Reviewed-by: Matthew A. Ploetz <maploetz@us.ibm.com>
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Change-Id: I04c7d38860f042e392026f81f9f3772212dfe14f
Depends-on:Ib0db5ac2b9b5d5f5c2967ff97794493d867fb04b
Depends-on:Ic8bac9940b00eae01c175f51dd1872b2bb128b95
RTC:133832
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/21901
Tested-by: Jenkins Server
Tested-by: FSP CI Jenkins
Reviewed-by: Martin Gloff <mgloff@us.ibm.com>
Reviewed-by: Andrew J. Geissler <andrewg@us.ibm.com>
Reviewed-by: William G. Hoffa <wghoffa@us.ibm.com>
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This change includes the following:
- Kernel Updates to handle hypervisor interrupt vector
- Interrupt Resource Provider changes to setup and handle
LSI Based interrupts
- Kernel updates to handle modified interrupt flow for
LSI Based interrupts
- Attribute updates for Scom BAR Registers
Change-Id: If63f246a0090ab8c81c3fa8ac3ab6871a0af2e31
RTC:137561
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/20692
Tested-by: Jenkins Server
Tested-by: FSP CI Jenkins
Reviewed-by: Andrew J. Geissler <andrewg@us.ibm.com>
Reviewed-by: Prachi Gupta <pragupta@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
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Change-Id: Ic8bac9940b00eae01c175f51dd1872b2bb128b95
Depends-on:Ib0db5ac2b9b5d5f5c2967ff97794493d867fb04b
RTC:133832
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/20552
Tested-by: Jenkins Server
Reviewed-by: Andrew J. Geissler <andrewg@us.ibm.com>
Tested-by: FSP CI Jenkins
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Reviewed-by: William G. Hoffa <wghoffa@us.ibm.com>
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Change-Id: I2ad133be733ee9e41590b3b8bd60bd6abe69d1a9
RTC: 126786
Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/22054
Tested-by: Jenkins Server
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
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RTC: 124148
Change-Id: I055885bc7d7cfc4ebd7cf1a662f677bdf4e28c62
Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/22313
Tested-by: Jenkins Server
Reviewed-by: Richard J. Knight <rjknight@us.ibm.com>
Reviewed-by: Brian Silver <bsilver@us.ibm.com>
Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
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Change-Id: I5d19166fe949394fae536f5165ce6138be7f820b
Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/12277
Tested-by: Jenkins Server
Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
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Change-Id: I5664587b4f889099290ef50d50fa9ce5e580e1eb
Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/11167
Tested-by: Jenkins Server
Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
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See HW822317. The HMER register in P8 is not implemented to
handle multi-threaded XSCOM properly, so we need to move the
XSCOM mutex from per-thread to per-core. Also, there is an
issue where the 'done' bit can come on 1 cycle before the error
indicators, so need to potentially read the HMER a second time.
Change-Id: I495031a6e425fe7d5c6ffef8dda1e7a71caac9f2
CQ: SW250902
Backport: release-fips810
Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/9929
Reviewed-by: Michael Baiocchi <baiocchi@us.ibm.com>
Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
Tested-by: Jenkins Server
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* Ensure that unhandled SRESET will trigger TI.
Change-Id: I34807bc357ba6908327ede975afc9c6b6b17c098
RTC: 92848
Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/8933
Tested-by: Jenkins Server
Reviewed-by: Douglas R. Gilbert <dgilbert@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
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Change-Id: I743687d7072af303e62d638a7ee5ad6f89afbccb
RTC: 89403
Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/7484
Tested-by: Jenkins Server
Reviewed-by: Douglas R. Gilbert <dgilbert@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
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Change-Id: Ic5cb0817118bf0de7d706124708e5b8551ba4258
RTC: 41425
Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/1899
Tested-by: Jenkins Server
Reviewed-by: Van H. Lee <vanlee@us.ibm.com>
Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
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- Add include files into the fsp.tar
Change-Id: I12a50f7e09f70b1bc6acf436d896b6f3747a7507
RTC:50578
Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/2115
Tested-by: Jenkins Server
Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
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Change-Id: Idb7a2d8d72a55f644efd0b2548eca5df5d062e6d
RTC: 47491
Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/2011
Tested-by: Jenkins Server
Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
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The memory profiling tools sometimes encountered a condition where
the kernel stack was becoming corrupted. I tracked it down to the
winkle code storing the winkle-save state at the wrong end of the
stack. Moving the winkle-save area to the bottom of the stack,
which is where I originally intended it to go.
Also noticed that the task issuing the winkle was in "running"
state while waiting for the cores to come out of winkle. Ensure
that the kernel updates the task state with a non-running status
while we are waiting for winkle to complete.
Change-Id: I07a56ea6f24cbc09362f9227d81915da5bc9f148
Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/1737
Tested-by: Jenkins Server
Reviewed-by: Douglas R. Gilbert <dgilbert@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
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When executing the nap instruction, all thread state can be
lost. This was causing r0 to be lost, which contained the
system-call number for the idle thread to request permission
to execute nap and as a result 'task-yield' was executed
instead of 'cpu-nap' after the idle thread took its first
nap.
Re-arranged the sreset code that handles nap-wakeup to deal
with thread-state being lost when entering nap and instead
using the previously saved task-state from the 'cpu-nap'
system call.
Change-Id: Id7468a8577c4d7b273b23bc97e7dd040555e7b67
Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/1567
Tested-by: Jenkins Server
Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
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Created per-node arrays of CPU objects rather than a single array
for the entire system. These are created dynamically as CPUs are
enabled.
Also disabled support for P7 due to the PIR layout being different
and hence would have needed two different sets of assembly code.
We have been running exclusively on the P8 Mambo model for a while.
RTC: 42815
Change-Id: Ib92de8a7c07c2e700a3b7f0c03c64d484b447ca2
Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/1630
Tested-by: Jenkins Server
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
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The Power processor has instructions of the form 'or a,a,a'
that allow code to change the priority of a hw-thread relative
to the others. We initially used 'or 1,1,1' as low priority
and 'or 3,3,3' as high priority. This is used in, for instance,
spinlocks to reduce the priority of a hw-thread while waiting
for another thread to perform an activity.
This code originally came from HAL. In reading the Power ISA
closer I realized that 'or 3,3,3' has no effect when in
user-space code, which means that a spinlock-like effect in
user code is going to end up with the thread stuck at low
priority until the next context switch. To prevent this we
are going to change from 1/3 to 1/2 as the priority levels.
Change-Id: I60ee866cde37499106f5e1e1d68a0b5ddeedf403
Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/1569
Tested-by: Jenkins Server
Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
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Change-Id: I47a8ad7914c6833c476a7944be5d352f45467f3a
RTC: 47725
Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/1646
Tested-by: Jenkins Server
Reviewed-by: Mark W. Wenning <wenning@us.ibm.com>
Reviewed-by: Douglas R. Gilbert <dgilbert@us.ibm.com>
Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
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* Choose thread with the lowest PIR as the last to enter payload.
* Use HRMOR update process from Murano Book IV.
RTC: 43166
Change-Id: I629f4a55cba1967a13c31a16095697b7142ca407
Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/1529
Tested-by: Jenkins Server
Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
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RTC: 44730
Change-Id: Ifaeecc659e1bfd8ded4744dc591fc993471519ba
Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/1471
Tested-by: Jenkins Server
Reviewed-by: Mark W. Wenning <wenning@us.ibm.com>
Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
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Change-Id: Ifd611129c2d7173b5e0dec36c870e06a4d851009
Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/1384
Tested-by: Jenkins Server
Reviewed-by: Douglas R. Gilbert <dgilbert@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
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Task 44887
Change-Id: If87b6e80b974bb4cbff13844d8a3f055a17282d2
Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/1378
Tested-by: Jenkins Server
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Reviewed-by: Douglas R. Gilbert <dgilbert@us.ibm.com>
Reviewed-by: Mark W. Wenning <wenning@us.ibm.com>
Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
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RTC: 37009
Change-Id: I56669805c86d9659a20ad7c26e5e9860c7a248c7
Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/1087
Tested-by: Jenkins Server
Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
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This code is currently unused, due to InitService not having the
payload address and the start_host_os IPL step being unimplemented.
For testing purposes the 'shutdown' call in initservice.C can be
changed to pass a non-zero base address (such as 256MB).
RTC: 40871
Change-Id: I0f4b6bae62ede1853aabbcb28082300005e31897
Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/926
Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
Tested-by: Jenkins Server
Reviewed-by: Douglas R. Gilbert <dgilbert@us.ibm.com>
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The P8 processor (in RFC02230 targeted for ISA 2.07) adds a
new SPR register HFSCR (Hypervisor Facility Status and Control
Register). This register allows the hypervisor to disable
access to some resources, such as floating point and VSX,
from a partition. The purpose of this is to save time in
saving the partition context when switching partitions.
Since we sometimes enable floating point instructions we need
to also enable the HFSCR[FP]. We could do this when enabling
floating point in the MSR, but the SPR does not exist in P7.
Instead we'll do it as-needed on the hw-thread the first time
it executes a FP instruction. The FP instruction will cause
the hype_fac_unavail exception and the exception handler will
set HFSCR appropriately.
Change-Id: I6c1e75939bb59142cbcf692fa56deb2271d6bdc3
Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/676
Tested-by: Jenkins Server
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Reviewed-by: Douglas R. Gilbert <dgilbert@us.ibm.com>
Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
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Change-Id: I73a446754cd03178055459eb75c7b2f87b51b0f3
Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/635
Tested-by: Jenkins Server
Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
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Change-Id: If6b499d819b71298b8a64e096e1eb83c639ad645
Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/517
Tested-by: Jenkins Server
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
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Change-Id: Ic8c0a5567f4f1e008014a4d54fb640dda6669cbc
Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/346
Tested-by: Jenkins Server
Reviewed-by: Douglas R. Gilbert <dgilbert@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
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Change-Id: I529e6f072993c0dd0a638fe7e53bcc871e6a928c
Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/326
Tested-by: Jenkins Server
Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
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Change-Id: I859cac1c01bf631d12223702d68813b45339b65f
Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/295
Tested-by: Jenkins Server
Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
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Change-Id: I970d645108de041d410599847edce877cb794015
Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/275
Tested-by: Jenkins Server
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
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Change-Id: I205f2409e56032cfc0aaf01d7e26d357f0b86373
Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/277
Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
Tested-by: Jenkins Server
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Change-Id: Ica416251241a2881459b2eb1ae0ad3c746de1200
Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/267
Tested-by: Jenkins Server
Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
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Change-Id: Ie1133bd079e7b9a8f2f82daa06efc426bf0fd0d6
Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/268
Tested-by: Jenkins Server
Reviewed-by: Douglas R. Gilbert <dgilbert@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
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Change-Id: I03a7460b347b47f4653a6f457d1d7711fc0a0512
Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/209
Tested-by: Jenkins Server
Reviewed-by: Douglas R. Gilbert <dgilbert@us.ibm.com>
Reviewed-by: MATTHEW S. BARTH <msbarth@us.ibm.com>
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This is required to reduce the memory footprint of the kernel
so we can fit within 2MB. This patch will cause (in simics)
all other cores/threads to execute a 'doze' instruction and
cease executing. In VBU, only 1 core will be active anyhow.
Change-Id: If1bdc01393b02d802ba7595a88dcf3331efc2d4e
Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/203
Tested-by: Jenkins Server
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Reviewed-by: Douglas R. Gilbert <dgilbert@us.ibm.com>
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This will prevent kernel space from needing to dereference user-space
addresses for starting a task, which is safer and is easier for VMM.
Change-Id: Icad3b832550cedbf291ed8b032840f4049fba18e
Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/202
Tested-by: Jenkins Server
Reviewed-by: Douglas R. Gilbert <dgilbert@us.ibm.com>
Reviewed-by: MATTHEW S. BARTH <msbarth@us.ibm.com>
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Change-Id: Icc7494986d19950a18cc9ee53fd5125c86096a72
Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/105
Tested-by: Jenkins Server
Reviewed-by: Douglas R. Gilbert <dgilbert@us.ibm.com>
Reviewed-by: Andrew J. Geissler <andrewg@us.ibm.com>
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Change-Id: I6d6304851a1794e117782277f6e3aee7544afcc7
Reviewed-on: http://gfwr801.rchland.ibm.com:8080/gerrit/6
Tested-by: Jenkins Server
Reviewed-by: Andrew J. Geissler <andrewg@us.ibm.com>
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