| Commit message (Collapse) | Author | Age | Files | Lines |
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The address where SBE is to populate the ultravisor white/blacklist
is to be put in Mbox reg1, which means that the register needs to
be masked in the command we're sending. Before this change, only
Mbox reg0 was masked, and SBE was not getting the correct address
at which to populate the UVBWLIST. This change masks Mbox Reg 1 so
that SBE can receive the correct address for the UVBWLIST.
Change-Id: I841db74dc407f51c14f005b9ccd457d5641ffa7e
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/87102
Reviewed-by: Nicholas E Bofferding <bofferdn@us.ibm.com>
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Reviewed-by: RAJA DAS <rajadas2@in.ibm.com>
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Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Daniel M Crowell <dcrowell@us.ibm.com>
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Change-Id: I4a4b7c8fccab508ee59e5e6330b27b07b5ae91f8
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/71417
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Reviewed-by: Ilya Smirnov <ismirno@us.ibm.com>
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Reviewed-by: MURULIDHAR NATARAJU <murulidhar@in.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
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Change-Id: I595fdcecaa08830514dacd81255bc0e9af222b40
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/61964
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Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
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- Handling a PSU DD Timeout involves invoking the SBE Retry
handler, which can cause crashes (FAPI library not yet
initialized) if the timeout happens very early in the IPL.
- Added a check if the FAPI Library was loaded, and added a
call to handle the early timeout later in the IPL.
Change-Id: I199cf0302af916b3f6ffec598ccab04c031e48e6
RTC:433868
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/61730
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Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Disable-CI: Nicholas E. Bofferding <bofferdn@us.ibm.com>
Reviewed-by: Prachi Gupta <pragupta@us.ibm.com>
Reviewed-by: William G. Hoffa <wghoffa@us.ibm.com>
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- Remove PSU Handling from INTRP code and instead treat PSU
interrupts like any other interrupt type
- Add msg_handler to SBE PSU Code to handle interrupts
- Add better interrupt handling to timeout path so the interrupt
condition will be cleared instead of represented continuously
- Handle shutdown message from INTRP
Change-Id: I5eafea806e147c22be235ae1c54a5ce4706aa012
RTC: 149698
CQ: SW418168
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/60049
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Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com>
Reviewed-by: Nicholas E. Bofferding <bofferdn@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
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Structure sbeCapabilities_t was added to the sbe_utils.H, a common file that
can be shared among other files that need the sbeCapabilities_t struct.
The psuCommand structure was updated, in file sbe_psudd.H, to facilitate the
PSU call to get SBE Capabilities. Also structs fifoGetCapabilitiesResponse/
fifoGetCapabilitiesRequest were added to file sbe_fifodd to facilitate
the FIFO call to get SBE Capabilities.
Attributes SBE_COMMIT_ID, SBE_VERSION_INFO and SBE_RELEASE_TAGS were added to
the target '<id>chip-processor</id>'. These attributes are the ultimate
receiver of the SBE capabilities' version, commit id and release tags info.
New file sbe_capabilities.C contains the call to getPsuSbeCapabilities and
getFifoSbeCapabilities which ultimately perform the call to do the PSU chip
operation, FIFO chip operation and update the attributes above. In step 6,
host_discover_targets, and in step 8,
call_proc_check_slave_sbe_seeprom_complete, is where the calls to
getPsuSbeCapabilities and getFifoSbeCapabilities are made respectively.
The file FipS_SBE_Interface_Specification_v1.3a.pdf (FIFO), file
Host_SBE_Interface_Specification_v0.9d.pdf and looking at
HW code were used to guide the coding of this.
Change-Id: I32ccdeab7bf0a478298b199d42d74650a3f393f6
RTC:181139
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/56317
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Reviewed-by: Martin Gloff <mgloff@us.ibm.com>
Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Prachi Gupta <pragupta@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
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During an SBE update we were getting I2C collisions when trying to
access pnor on the "running" or "active" side of the seeprom. This
commit adds support for a PSU chipOp called "readSeeprom" which
allows the host to make a request to the SBE to copy a specified
chunk of pnor out to a buffer in memory which the host can access.
This commit also uses this chipOp in place of the I2C read during
the SBE update of the active seeprom side.
Change-Id: I4b639ebe6090dcc0bdbb42f13fcb12c23260a8b4
RTC: 180959
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/48408
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Reviewed-by: Matt Derksen <mderkse1@us.ibm.com>
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Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
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Before we only needed to get the target info for the scan chipop,
now more sbe chip ops require this functionality so we are moving
it to common code
Change-Id: Ifbb680db27c5975ee216d5d21ff78192c9ea2d34
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/46345
Reviewed-by: Martin Gloff <mgloff@us.ibm.com>
Reviewed-by: Matt Derksen <mderkse1@us.ibm.com>
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Reviewed-by: William G. Hoffa <wghoffa@us.ibm.com>
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Previously we were relying on the reservedMem section to be a certain
address for the attrrp to find after an MPIPL. With this change the
address is passed through the SBE so the reservedMem data can be
anywhere
RTC: 165369
Change-Id: I06521c049088c4a53a8c0a51fa07e5200da09483
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/44624
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Reviewed-by: Brian E. Bakke <bbakke@us.ibm.com>
Reviewed-by: Martin Gloff <mgloff@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
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This commit provides the base support of Opening and Closing Unsecure
Memory Regions via PSU commands to the SBE. It introduces external
interfaces, a Memory Region Manager class, and a testcase that
covers the expected use of the interfaces. However, it does not
enable the actual PSU commands to the SBE since their support
is not yet available.
Change-Id: I086011fcbd485abf2db574a82d43cfdea120ffc8
RTC:145686
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/42834
Reviewed-by: Nicholas E. Bofferding <bofferdn@us.ibm.com>
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Reviewed-by: Stephen M. Cprek <smcprek@us.ibm.com>
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Reviewed-by: Marshall J. Wilks <mjwilks@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
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For mpipl we need to pass an address through the SBE. To do this
the SBE is writing functionality that takes in uint8_t key and a
uint64_t value and from this chipOp and stores it in the bootloader
image (before 12k exception vector but after magic keyword). I also
cleaned up some prior naming inconsitencies in this commit
RTC: 173362
Change-Id: Id6dc47ed0e34f50f74fc894007dd144b2f7bfe81
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/41844
Reviewed-by: Martin Gloff <mgloff@us.ibm.com>
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Reviewed-by: Matt Derksen <mderkse1@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
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Add the response and the target processor to the SRC for
PSU timeouts.
Change-Id: I4c739a66ab5bee8e35a514f6851e4c55e09d18e8
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/42369
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Change-Id: Ia2b1012cf2938f34cc6acdbb888b5a489aac98f6
RTC: 164405
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/40453
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Reviewed-by: Shakeeb A. Pasha B K <shakeebbk@in.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
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Create space for SBE Communications buffer in HB reserved memory and
send Set FFDC Address PSU command to SBE.
Change-Id: Ibccdf087d0416edaf6e1e2c5993a10adcddf67fd
RTC: 170758
Depends-on: Id14471b1e6f036c278fd5ae1950b942290282c1e
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/38251
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Reviewed-by: Corey V. Swenson <cswenson@us.ibm.com>
Reviewed-by: William G. Hoffa <wghoffa@us.ibm.com>
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Call sendPsuQuiesceSbe before doing the deviceWrite of the SBE SEEPROM
with the SBE image.
Change-Id: I6d3cec5b0430b8083acabc30bb7ff14ba5e1b56e
RTC:158899
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/34994
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Reviewed-by: Michael Baiocchi <mbaiocch@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
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There is at least 1 scenario where the FSP and HB are both
accessing the SBE at the same time. The FSP operation can
take a very long time so HB is increasing our timeout so
that we don't fail if we happen to hit that window.
Change-Id: I8908608a1db4ac8c27ded59eced8f0ad71f70314
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/35612
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Reviewed-by: William G. Hoffa <wghoffa@us.ibm.com>
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Add SBE FFDC error handling to FIFO driver
Change-Id: I6ae81062eac1d5362c5fa5651c8ca5a2043b5c73
RTC: 149454
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/32969
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Reviewed-by: William G. Hoffa <wghoffa@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
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The SBE provides an interfaces for the HOST to issue a psu cmd
that will quiesce the SBE. This commit adds the ability for
HB code to call one function and notify the SBE to quiesce
Change-Id: Icb153875b797f107891b05fd26dccbc413fd8f93
RTC:158899
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/33610
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Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
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Turn sbe_psudd into singleton.
Add handle FFDCError function
Change-Id: If84bb2bafcca685c8d31c664f7005de056e96c4c
RTC: 144313
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/31468
Reviewed-by: William G. Hoffa <wghoffa@us.ibm.com>
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The SBE needs to know about other PROCs in the sytem. To do
this we are sending a 64 bit string that encodes the system
configuration down to the SBE at the end of the IPL. This
commit just sets up some of the infrastructure that will be needed
to send the message.
Change-Id: I1a4dfb4e54e043d94697fa809acf1eee8ba9f726
RTC: 160666
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Reviewed-by: Matthew A. Ploetz <maploetz@us.ibm.com>
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Change-Id: I4930633f87bdb61acb19e01f17a8006277f7868d
RTC:132654
CMVC-Prereq: 1004971
CMVC-Prereq: 1005024
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/28887
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Reviewed-by: Vitaly Marin <mvitaly@us.ibm.com>
Reviewed-by: William G. Hoffa <wghoffa@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
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