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* Add Naples support to the kernelBrian Silver2014-06-231-0/+2
| | | | | | | | | Change-Id: Ie748454257938103bdb76d7ac1b5d425bc97d348 RTC: 107941 Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/11298 Tested-by: Jenkins Server Reviewed-by: Douglas R. Gilbert <dgilbert@us.ibm.com> Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
* Change copyright prolog for all files to Apache.Patrick Williams2014-05-2110-117/+117
| | | | | | | Change-Id: I5664587b4f889099290ef50d50fa9ce5e580e1eb Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/11167 Tested-by: Jenkins Server Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
* Use new scratch reg for hb_done and set early in IPLAndrew Geissler2014-03-131-6/+4
| | | | | | | | | | | | | | | | | This is to support using the scratch register for the power off message. I moved to a new scratch register since we were sharing with a SBE scratch reg that was needed early in HB IPL. NOTE! This will have a co-req with an FSP track so we'll need to coordinate. CMVC-Coreq: 917527 Change-Id: I5f81f15126d6ad8d2c9459c5afe730554256c037 RTC: 95818 Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/9220 Tested-by: Jenkins Server Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: MIKE J. JONES <mjjones@us.ibm.com> Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
* Workaround invalid SBE use of IPI inject registerDean Sanner2014-03-041-1/+3
| | | | | | | | | Change-Id: I40600399daf2ef563b534bd91143a4f45d00ff79 CQ: SW248610 Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/9273 Tested-by: Jenkins Server Reviewed-by: Douglas R. Gilbert <dgilbert@us.ibm.com> Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
* Handle pending interrupts across nodes in mpiplDoug Gilbert2014-03-021-0/+58
| | | | | | | | | RTC: 80988 Change-Id: I7ef9feaa3d163d6956576f30538e2fe001e892a1 Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/8441 Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Tested-by: Jenkins Server Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
* implement start_payload for multi-drawerDoug Gilbert2014-01-101-2/+4
| | | | | | | | RTC: 71994 Change-Id: I422f349d5588731a5e7cfc504d96e497958d6b95 Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/7426 Tested-by: Jenkins Server Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
* hbirt increase number of modules allowedDoug Gilbert2013-11-131-1/+6
| | | | | | | | Change-Id: I64a05ac460d75a8328a326d808e906dc0751a8d8 Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/7166 Tested-by: Jenkins Server Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
* Initial Support for Updating SBE SEEPROMMike Baiocchi2013-10-281-1/+1
| | | | | | | | | | | | | | | This initial commit will be used to create the new SBE directories and files. It also supports the usr functions to find and copy SBE PNOR images. NOTE: It will not enable Updating SBE SEEPROMs in the IPL. Change-Id: I3f545a134493c7595ce50fd885478bbe606de472 RTC: 47032 Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/6311 Tested-by: Jenkins Server Reviewed-by: ADAM R. MUHLE <armuhle@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
* Resolve testcase race conditions with SCAN.Patrick Williams2013-09-111-2/+2
| | | | | | | | | | | | | | A number of test cases were writing to the SCAN select register and if the SCAN device driver unit tests were running at the same time they would clobber each other. Moved the other test cases to utilize a core scratch register instead. Change-Id: I243500ce40cdb75e1052541056f9460e50e0bbcd Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/5977 Tested-by: Jenkins Server Reviewed-by: MIKE J. JONES <mjjones@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
* Ensure task_crash not optimized outMike Jones2013-08-291-2/+2
| | | | | | | | | | | | | | User space assert() calls the task_crash() macro to crash the thread, this writes to address NULL, but the write is optimized out. Therefore an assert does not cause the task to crash as intended. If istep code asserts, the istepdispatcher does not notice and Hostboot hangs instead of TIing. This is fixed with a volatile. Change-Id: Icc27d94d76e937000189655c2f8a640620456673 RTC: 80657 Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/5968 Tested-by: Jenkins Server Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
* Basic devtree supportDean Sanner2013-08-091-1/+4
| | | | | | | | | | Simple devtree support for Sapphire in SPless mode Change-Id: I4a70bfc5cd3eb3dbd1b443869c046c789f98cc95 Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/3739 Tested-by: Jenkins Server Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
* Use SBE Setting of Thread Count or FailMike Baiocchi2013-07-091-23/+28
| | | | | | | | | | | | | | This commit takes out the workaround of using a default setting of a thread count if the SBE didn't set the right value in a scratch register. The current SBE code now does this, and we will now fail if for some reason the value isn't set. This commit also includes sim action file updates to model this behavior. Change-Id: I83608c402fac675c0287fa3ce38cf75237bcff26 RTC: 63991 Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/5255 Tested-by: Jenkins Server Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
* Secureboot memory layout support.Patrick Williams2013-06-141-0/+1
| | | | | | | | | | | | | | | | * Start kernel in 1/4 cache mode per Secureboot. * Copy Secureboot header for base image for later use. * Blind-purge bottom half of cache. * Add bottom of cache into memory maps for 1/2 cache mode. RTC: 64762 Change-Id: I1b45f30a2d45c9709d4fd486cfe0ca2ce86b051c Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/3773 Reviewed-by: Michael Baiocchi <baiocchi@us.ibm.com> Tested-by: Jenkins Server Reviewed-by: ADAM R. MUHLE <armuhle@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
* New mm_block_map syscall.Patrick Williams2013-06-102-1/+18
| | | | | | | | RTC: 71081 Change-Id: Ic5531fbba92cfc7aad7d303f043d6a350483d63d Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/4607 Tested-by: Jenkins Server Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
* Tolerate memory UEs during dump extraction.Patrick Williams2013-06-061-1/+21
| | | | | | | | | | Change-Id: I0dc57ec047beb47b557b816162d619a5b2a54108 RTC: 64619 Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/4600 Tested-by: Jenkins Server Reviewed-by: ADAM R. MUHLE <armuhle@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
* Inter-processor communications for multinodeDoug Gilbert2013-05-161-1/+2
| | | | | | | | RTC: 63128 Change-Id: Ica27c7f714bc8b874c9bccb663a32d3cfba37c5a Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/4193 Tested-by: Jenkins Server Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
* AVP OCC Enable & Procedure RefreshAdam Muhle2013-05-151-0/+14
| | | | | | | | | | | | Refreshed OCC Procedures Enabled OCC in AVP mode for all processors Merged SLW and OCC to common HOMER image RTC:50987 Change-Id: I08d9128dfcb572367c145ee0296a48292584a480 Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/4340 Tested-by: Jenkins Server Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
* IBSCOM error path supportAdam Muhle2013-05-081-0/+11
| | | | | | | | | | | | | | | This commit updates IBSCOM to have error path support. It also updates the good-path test cases since there is limited good path support in simics. Full enablement will be done later. Change-Id: I5f9d66165db119473f606303a1026c8c71988785 RTC: 34743 Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/3972 Tested-by: Jenkins Server Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: Douglas R. Gilbert <dgilbert@us.ibm.com> Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
* Fixes for GCC 4.7Patrick Williams2013-04-171-2/+2
| | | | | | | Change-Id: Ief0b9202e13bd70cf0de84ca3cb20f5c6df4d3d8 Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/4035 Tested-by: Jenkins Server Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
* Allow winkle of all threads for multi-drawer add.Patrick Williams2013-04-081-0/+24
| | | | | | | | | | | RTC: 63124 Change-Id: I1ad1d6bdf6a2848b686b25504fabddddb701d440 Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/3813 Tested-by: Jenkins Server Reviewed-by: Douglas R. Gilbert <dgilbert@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: Michael Baiocchi <baiocchi@us.ibm.com> Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
* Update Core Scratch Reg 6 with L3 vs Mainstore for FSP to queryMissy Connell2013-03-261-2/+3
| | | | | | | | | RTC:64829 Change-Id: Ic8e7983f6838b79c359c4cee2647b7676493cb1e Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/3564 Tested-by: Jenkins Server Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
* Add system-wide constants to specify the maximum number of procs possible in ↵Mark Wenning2013-02-281-0/+18
| | | | | | | | | | the system Change-Id: I6759b15c3f31f9e8ba219b0f9661a6c947eb94d6 RTC: 61361 Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/3082 Tested-by: Jenkins Server Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
* Support for less than 8 threads per coreDan Crowell2013-02-082-3/+7
| | | | | | | | | | | Modified anywhere that we enable non-master threads to only touch the threads that we are told to update. Change-Id: I5b764e51d85a5c663ac76164e9465831ef0c167c RTC: 48808 Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/2877 Tested-by: Jenkins Server Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
* Remove support for P7.Patrick Williams2013-01-101-3/+1
| | | | | | | | | | Change-Id: I9186f42f85d6f6864b51b6935f5d4e5ca510ceb4 RTC: 39872 Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/2901 Tested-by: Jenkins Server Reviewed-by: ADAM R. MUHLE <armuhle@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
* ptmgr lacked support for physical mapped addrs.Patrick Williams2012-12-171-0/+1
| | | | | | | | | | | | | | | | Added a new access type of BYPASS_HRMOR that the ptmgr will support when a PTE is added, so that blocks can support addresses which do not have the HRMOR applied. This is needed so that mm_linear_map will work correctly when HRMOR != 0. Change-Id: Ie4599d63a4454f425e0a0964b02fec7075c4401e RTC: 60665 Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/2733 Tested-by: Jenkins Server Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
* Switch Interrupt Presenter to get ICPBAR value from an attributeDoug Gilbert2012-12-143-88/+59
| | | | | | | | Change-Id: I5d95f3e3e2d803f07c7d8f3bf2d8ee522e1b4519 Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/2406 Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com> Tested-by: Jenkins Server Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* Lockless trace implementationPatrick Williams2012-12-142-30/+67
| | | | | | | | | RTC: 35396 Change-Id: I96ea0d95606f04abb4dc2b0470345ca475b53912 Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/2520 Tested-by: Jenkins Server Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
* Expand memory footprint to full 8MB cache.Patrick Williams2012-11-141-3/+11
| | | | | | | | | | | | | | If fake PNOR isn't being used, we can expand our memory space to the full 8MB cache. There will be follow up work with RTC: 49137 to support 4MB degraded caches for bring-up. Change-Id: I1248efa37965f39ebab62aae556349c34aa24b66 RTC: 47356 Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/2319 Tested-by: Jenkins Server Reviewed-by: Melissa J. Connell <missyc@us.ibm.com> Reviewed-by: ADAM R. MUHLE <armuhle@us.ibm.com> Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
* Terminate Immediate on a shutdown and assertMissy Connell2012-11-091-0/+9
| | | | | | | | Change-Id: I37c8956afb11c69201f4936821cff5e153327780 RTC:43793 Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/2194 Tested-by: Jenkins Server Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
* Memory Leak task_endBill Schwartz2012-10-121-27/+31
| | | | | | | | Change-Id: Idb7a2d8d72a55f644efd0b2548eca5df5d062e6d RTC: 47491 Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/2011 Tested-by: Jenkins Server Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
* Extend VMM to 32MMissy Connell2012-10-091-0/+17
| | | | | | | | | | | | | | Add mmLinearMap to create block at a specified phys addr. Added iv_MaptoPhy in the block to indicate we are physically mapped block and to not apply the HRMOR. Change-Id: I75ddb19b82ae9a2035ff873edff8a34a33c74639 RTC:43401 Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/1846 Tested-by: Jenkins Server Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
* Support for Non-zero HRMORDan Crowell2012-09-161-23/+33
| | | | | | | | | | | | | | | | | | Changes to kernel code to support detection and use of HRMOR offset in memory Changes to tooling to handle the real memory offset New interface to retrieve the physical address that corresponds to a virtual address To test, run these commands before starting up Hostboot: system_cmp0.cpu0_0_05_0.write-reg HRMOR 0x8000000 proc_venicechip_cmp0.phys_mem.del-map p8Proc0.l3_cache_ram 0 0 RTC: 46032 Change-Id: I50ab248f941218a3a14a8f0fc12a551b56dc7cf3 Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/1553 Tested-by: Jenkins Server Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
* Allow processors on logical nodes != 0.Patrick Williams2012-09-061-28/+22
| | | | | | | | | | | | | | | | | Created per-node arrays of CPU objects rather than a single array for the entire system. These are created dynamically as CPUs are enabled. Also disabled support for P7 due to the PIR layout being different and hence would have needed two different sets of assembly code. We have been running exclusively on the P8 Mambo model for a while. RTC: 42815 Change-Id: Ib92de8a7c07c2e700a3b7f0c03c64d484b447ca2 Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/1630 Tested-by: Jenkins Server Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
* Write scratch register in start_payload / shutdown.Patrick Williams2012-09-041-25/+25
| | | | | | | | | | Change-Id: I47a8ad7914c6833c476a7944be5d352f45467f3a RTC: 47725 Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/1646 Tested-by: Jenkins Server Reviewed-by: Mark W. Wenning <wenning@us.ibm.com> Reviewed-by: Douglas R. Gilbert <dgilbert@us.ibm.com> Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
* Support for master winkle.Patrick Williams2012-08-101-0/+3
| | | | | | | | | RTC: 44730 Change-Id: Ifaeecc659e1bfd8ded4744dc591fc993471519ba Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/1471 Tested-by: Jenkins Server Reviewed-by: Mark W. Wenning <wenning@us.ibm.com> Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
* Stub function for master winkle.Patrick Williams2012-07-181-0/+12
| | | | | | | | | | | Task 45250 Change-Id: Icb27948fa68a58cf9ec79816c5ac76afc5b74e2a Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/1379 Tested-by: Jenkins Server Reviewed-by: Douglas R. Gilbert <dgilbert@us.ibm.com> Reviewed-by: Mark W. Wenning <wenning@us.ibm.com> Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
* cpu_spr_value syscall for SLW image build.Patrick Williams2012-07-181-23/+44
| | | | | | | | | | | | Task 44887 Change-Id: If87b6e80b974bb4cbff13844d8a3f055a17282d2 Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/1378 Tested-by: Jenkins Server Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: Douglas R. Gilbert <dgilbert@us.ibm.com> Reviewed-by: Mark W. Wenning <wenning@us.ibm.com> Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
* Support for core_activate via IPI.Patrick Williams2012-07-162-3/+18
| | | | | | | | RTC: 37009 Change-Id: I56669805c86d9659a20ad7c26e5e9860c7a248c7 Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/1087 Tested-by: Jenkins Server Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
* Istep sync point message supportTerry J. Opie2012-07-121-1/+1
| | | | | | | | | | | | | | | | - Refactor IStepDispatcher for more robust msg handling - Modify sptask to act like real Fsp - Move all Istep Mbox Msg handling to Initservice - Add send sync point interface - Add wait on sync point interface - Modify start_payload istep to use new interfaces - Fix for Istep.pm Change-Id: Ib28b89cd916b9c0a0d15016996dbf1b88a8f79eb RTC: 43554 Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/1255 Tested-by: Jenkins Server Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
* mboxdd setup ISRN and XIVR xscom registersDoug Gilbert2012-07-121-22/+24
| | | | | | | | | RTC: 44240 Change-Id: I8767265b5f5eccfda2c748c9b0d51027dffbb7eb Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/1250 Tested-by: Jenkins Server Reviewed-by: Douglas R. Gilbert <dgilbert@us.ibm.com> Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
* Live-lock issues in memory allocator.Patrick Williams2012-07-111-6/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | * Debug tool for PageManager. * Support PageMgr allocations of non-2^k size. * Switch page-allocation to always be in kernel-mode. While investigating issue 44511, I noticed two problesm with the memory page allocator (PageManager). First, the allocator did not support allocations of pages which were not a power of 2, which would result in pages appearing to "leak". Second, in situations where a large allocation was requested and there was not a large chunk available, the allocation would enter a live-lock condition where coalescing would never occur. Switched the PageManager so that all allocations happen in kernel space. This allows us to force memory-release operations on the syscall path when we are out of memory and also put in place a task_yield call which will allow coalescing to eventually occur. Issue 44523 is suppose to fully resolve any of these live-lock paths. RTC: 44511 Change-Id: Ifefd5d0996ee6914e291c862fac0c7b76980717f Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/1330 Tested-by: Jenkins Server Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
* Improve memory page manager for low memory situationsDoug Gilbert2012-07-111-22/+29
| | | | | | | | | RTC: 40831 Change-Id: I7889f91eec44a10d56ffc94e03c7557f8085100a Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/1272 Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com> Tested-by: Jenkins Server Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* Mailbox additional error handling for Hardware errors and Invalid messagesDoug Gilbert2012-07-092-44/+56
| | | | | | | | | RTC: 37990 Change-Id: I8378845ed412490a3bd214ac5198ea1fc9f19664 Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/1221 Tested-by: Jenkins Server Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
* Switch to using PNOR in SimicsDean Sanner2012-06-261-30/+37
| | | | | | | | | | | | | Switch to use manual PNOR images in simics Provided method for VPO to override Change-Id: I18195b645053f1ce90b4322ae2e09b6b08844331 Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/1241 Reviewed-by: ADAM R. MUHLE <armuhle@us.ibm.com> Reviewed-by: Thi N. Tran <thi@us.ibm.com> Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Tested-by: Jenkins Server
* Fix time constants in sys/time.hMike Jones2012-06-181-25/+25
| | | | | | | | | Change-Id: Id98582002c23504fbd7e2bfb31855d2e09724a51 Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/1201 Tested-by: Jenkins Server Reviewed-by: Andrew J. Geissler <andrewg@us.ibm.com> Reviewed-by: Mark W. Wenning <wenning@us.ibm.com> Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
* Shutdown interrupt sourcesDoug Gilbert2012-06-071-1/+0
| | | | | | | | | | RTC: 39878 Change-Id: I0c37a0dce8b818cf4a7b6fefe982b838dafcf917 Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/1074 Tested-by: Jenkins Server Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
* Support P8 memory map from PHYPPatrick Williams2012-06-011-1/+1
| | | | | | | | | Change-Id: I19e5c373713b6e8b12386266c5c2c3a015068d5a Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/1132 Tested-by: Jenkins Server Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: Douglas R. Gilbert <dgilbert@us.ibm.com> Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
* Fix IPC BAR scom addressDoug Gilbert2012-05-161-1/+1
| | | | | | | | | Change-Id: Ib3e13d892e58faa12082d6a09a1f6b504af44ae5 Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/1058 Reviewed-by: Thi N. Tran <thi@us.ibm.com> Tested-by: Jenkins Server Reviewed-by: Mark W. Wenning <wenning@us.ibm.com> Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
* INTR set IPCBAR scom reg on init and add INTR shutdown interfaceDoug Gilbert2012-05-111-0/+1
| | | | | | | | | | RTC: 39730 Change-Id: Ib548202f6f935b46cd92e0ddbf48d19b5ff6679a Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/977 Tested-by: Jenkins Server Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
* Allow kernel to shutdown-to-payload.Patrick Williams2012-04-241-2/+7
| | | | | | | | | | | | | | | This code is currently unused, due to InitService not having the payload address and the start_host_os IPL step being unimplemented. For testing purposes the 'shutdown' call in initservice.C can be changed to pass a non-zero base address (such as 256MB). RTC: 40871 Change-Id: I0f4b6bae62ede1853aabbcb28082300005e31897 Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/926 Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com> Tested-by: Jenkins Server Reviewed-by: Douglas R. Gilbert <dgilbert@us.ibm.com>
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