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* Setup INTP bars correctly when memory is swapped on master proccrgeddes2017-06-021-0/+5
| | | | | | | | | | | | | | | | In the event that no memory is detected behind proc0. We will attempt to use the memory behind a slave proc instead. When this occurs we must adjust the interrupt bars to account for this swap Change-Id: Ib37a190b7a7a2c655440ffd2bad56c351b4d4fa2 RTC: 173527 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/40820 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Martin Gloff <mgloff@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: William G. Hoffa <wghoffa@us.ibm.com>
* Map BAR attributes based on data from BootloaderDan Crowell2017-06-021-0/+61
| | | | | | | | | | | | | | | | | | | | | | | | | If the master processor has no memory behind it the entire memory map must be modified. Each processor has its own statically defined map that covers both memory and MMIOs. If the master has no memory, its memory map is swapped with another processor. Each processor gets a new effective fabric id that is then used to compute all of the BAR values for those processors. The SBE boots with a certain memory map programmed into the master processor. That value is then passed up through the bootloader into Hostboot. This value is compared to the BAR values that Hostboot assumes it is using. Based on that comparison, various attributes are computed to match the effective fabric positions. Change-Id: I2b0d1959c303df8c9c28c8f0a5b5be1e77aa154f RTC: 173528 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/40359 Tested-by: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: Martin Gloff <mgloff@us.ibm.com> Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: William G. Hoffa <wghoffa@us.ibm.com>
* Cleanup for SMT4/SMT8 read fuse bits and activate threadsCorey Swenson2017-05-151-2/+0
| | | | | | | | | | Change-Id: I9de1c4b08aceee76eed962413345c5e6d1444f23 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/39947 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Reviewed-by: Martin Gloff <mgloff@us.ibm.com> Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* Fix PVR check for Nimbus DD1Dan Crowell2017-05-111-2/+10
| | | | | | | | | | | | | | | | | | Added check for bit 18 to distinguish between Nimbus DD1.0 and Cumulus DD1.0 Consolidated Nimbus DD1 checking to a common function Added printk output that shows which CPU we're running on Modified some existing printk output to use fewer characters Change-Id: I1c42df0051fc2d9cc5fa54d95f68c3bd26b86462 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/39876 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com> Reviewed-by: Corey V. Swenson <cswenson@us.ibm.com> Reviewed-by: Martin Gloff <mgloff@us.ibm.com> Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* Handle SMT4/SMT8 fuse bitsCorey Swenson2017-04-281-0/+2
| | | | | | | | | | | Change-Id: I8fc108877714ff76103510b7801af72a94e5aae3 RTC:160720 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/39778 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Martin Gloff <mgloff@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* More istep debug outputDan Crowell2017-04-171-1/+16
| | | | | | | | | | | | | | | | Write current istep out to mbox scratch reg 5 Print istep out to simics console Change-Id: I14d8a9afba12b627a0b1880e0818b5b16f317d7c RTC: 171748 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/39292 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com> Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Thi N. Tran <thi@us.ibm.com> Reviewed-by: Dean Sanner <dsanner@us.ibm.com> Reviewed-by: William G. Hoffa <wghoffa@us.ibm.com>
* Create PVR routines to handle DD2 changesDan Crowell2017-03-091-0/+135
| | | | | | | | | | | | | | | Created new PVR_t structure that understands how to decode the PVR for Nimbus DD1 and future versions. Change-Id: Ie7e6f62d65fb1a3e11b1021f1600e7421b8c30a9 RTC: 160361 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/37303 Reviewed-by: Martin Gloff <mgloff@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: William G. Hoffa <wghoffa@us.ibm.com> Reviewed-by: Matthew A. Ploetz <maploetz@us.ibm.com>
* Multi-Proc Interrupt Support with Remote LSIsBill Hoffa2016-10-071-0/+5
| | | | | | | | | | | Change-Id: I8a981628cd3adc54ba581deb0ce8afb183febef3 RTC: 150562 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/29719 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Dean Sanner <dsanner@us.ibm.com> Reviewed-by: Prachi Gupta <pragupta@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* Log SBE Traces on error (simics only)Dan Crowell2016-09-281-0/+7
| | | | | | | | | | | | | | | A quick change to add a new magic instruction that collects the SBE traces any time we hit an error from the SBE. If multiple errors occur they will all be appended to the same file. Data will be saved to $sb/simics/sbetrace.hb.txt. Change-Id: I27575c1565c0089e847e19c3e51cb2926833e387 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/30206 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Reviewed-by: Martin Gloff <mgloff@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* Replace NAP with STOP instructionBrian Stegmiller2016-08-071-10/+1
| | | | | | | | | Change-Id: I58a382cfc285e37cc8748fe8e23f71c877850263 RTC: 130186 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/816 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* Add testcases for pirformat helper functionsBill Hoffa2016-05-241-7/+27
| | | | | | | | | | Change-Id: I10b2be1ea9d0dc4a46c6c473b03ee024c6bf0de6 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/24801 Reviewed-by: Andrew J. Geissler <andrewg@us.ibm.com> Tested-by: Jenkins Server Reviewed-by: Prachi Gupta <pragupta@us.ibm.com> Tested-by: FSP CI Jenkins Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* Add simics breakpoint for exceptionsDan Crowell2016-05-241-1/+3
| | | | | | | | | | | | | | | | | | | Created a new magic instruction handler that can be enabled via environment variable to stop the simulation for Hostboot exceptions. This is useful when we want to get a backtrace at the failing spot without recompiling code or having to manually insert breakpoints in simics directly. Enable the function by setting HB_BREAK_ON_ERROR The trigger call is MAGIC_BREAK_ON_ERROR Change-Id: I17e008281d010e3f8c5e5817e5f30fd0ccb624d0 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/24600 Tested-by: Jenkins Server Tested-by: FSP CI Jenkins Reviewed-by: William G. Hoffa <wghoffa@us.ibm.com> Reviewed-by: Marshall J. Wilks <mjwilks@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* Update PIR Structure to Match SpecificationBill Hoffa2016-05-171-20/+24
| | | | | | | | | | | - Change bit 24 to be reserved Change-Id: Ic471d37bb304eb3ac06a37603762b6088f6bb2cb CQ: SW352252 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/24410 Reviewed-by: Andrew J. Geissler <andrewg@us.ibm.com> Tested-by: Jenkins Server Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* Update constants and comments for P9 PIR formatDan Crowell2016-02-291-0/+167
| | | | | | | | | | | | | | | Implemented a set of macros and constants that can be used everywhere to translate a PIR into its component parts and pull out individual pieces of data from a complete PIR. Also added and updated the references to the old ATTR_FABRIC_NODE_ID with ATTR_FABRIC_GROUP_ID. Change-Id: If9735f53940e5849a648729e4bf8ca0cfbb09f6e RTC: 88055 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/706 Tested-by: Jenkins Server Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* HOSTBOOT: Support fused coresBrian Stegmiller2015-12-111-0/+34
| | | | | | | | | Change-Id: I2ad133be733ee9e41590b3b8bd60bd6abe69d1a9 RTC: 126786 Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/22054 Tested-by: Jenkins Server Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
* P9 page table changesCorey Swenson2015-12-111-0/+15
| | | | | | | | | | Change-Id: Ic5f234e0ce0747f887a706054f82372c9a96258c RTC:126640 Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/19041 Tested-by: Jenkins Server Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: WILLIAM G. HOFFA <wghoffa@us.ibm.com> Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
* Base kernel changes for Nimbus/CumulusCorey Swenson2015-12-111-2/+3
| | | | | | | | | Change-Id: Ic5dfde1e975453d760631335bab674919e1109e7 RTC: 126637 Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/18321 Tested-by: Jenkins Server Reviewed-by: Christian Geddes <crgeddes@us.ibm.com> Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
* Load PAYLOAD from FFS partition.Thi Tran2014-06-301-1/+5
| | | | | | | | Change-Id: Ib4f3b0631a9afb92fd5950b1636b8a3077684dbc Origin: Google Shared Technology Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/11553 Tested-by: Jenkins Server Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
* Change copyright prolog for all files to Apache.Patrick Williams2014-05-211-11/+11
| | | | | | | Change-Id: I5664587b4f889099290ef50d50fa9ce5e580e1eb Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/11167 Tested-by: Jenkins Server Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
* Force TIs for unhandled exceptionsPatrick Williams2013-12-091-0/+17
| | | | | | | | | | Change-Id: I743687d7072af303e62d638a7ee5ad6f89afbccb RTC: 89403 Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/7484 Tested-by: Jenkins Server Reviewed-by: Douglas R. Gilbert <dgilbert@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
* Fixed performance issues in SIMICS IPLStephen Cprek2013-10-311-0/+1
| | | | | | | | Change-Id: Iccce5b641d0e2dc414bacc143a6b3e186f4e49ab CQ: SW224728 Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/6960 Tested-by: Jenkins Server Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
* Update Core Scratch Reg 6 with L3 vs Mainstore for FSP to queryMissy Connell2013-03-261-0/+13
| | | | | | | | | RTC:64829 Change-Id: Ic8e7983f6838b79c359c4cee2647b7676493cb1e Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/3564 Tested-by: Jenkins Server Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
* Load a fake payloadPatrick Williams2013-03-261-0/+1
| | | | | | | | | | | | | | | | | Support loading a fake payload that simply naps all the threads. I am not enabling this via the simics_MACHINE.system.xml files because it causes drastic usability concerns for developers wanting to use the debug tools. When the payload is launched, the HRMOR changes, which means the debug tools no longer point at Hostboot. Change-Id: Ic899cf96af4d315f01c0ca4b7fc99e97c15d4dc1 RTC: 43029 Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/3642 Tested-by: Jenkins Server Reviewed-by: ADAM R. MUHLE <armuhle@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
* Support RPR register.Patrick Williams2013-01-141-1/+15
| | | | | | | | | | | | | | | | | | | | For P8 the priority of different threads has no effect unless the relative priority register is programmed to tell the relative scheduling weight of the different priorities. We will now be programming the RPR to give 32x performance boost to "high" priority threads relative to "low" priority. This means that when a thread is waiting on another, and thus has low priority, it will get 32x less dispatch cycles then the thread it is waiting on. Change-Id: I0d1d1052b12ab8bd5612aa4580cd85b5c238f885 Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/2888 Tested-by: Jenkins Server Reviewed-by: Douglas R. Gilbert <dgilbert@us.ibm.com> Reviewed-by: Mark W. Wenning <wenning@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
* Memory profiling tools.Patrick Williams2012-09-071-1/+2
| | | | | | | | | | Change-Id: I4a9cfc1f55c09ff6d02dce80889ac2e3150ab137 RTC: 44504 Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/1619 Tested-by: Jenkins Server Reviewed-by: Douglas R. Gilbert <dgilbert@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
* Set "high" thread priority as 2 rather than 3.Patrick Williams2012-09-051-24/+23
| | | | | | | | | | | | | | | | | | | | | The Power processor has instructions of the form 'or a,a,a' that allow code to change the priority of a hw-thread relative to the others. We initially used 'or 1,1,1' as low priority and 'or 3,3,3' as high priority. This is used in, for instance, spinlocks to reduce the priority of a hw-thread while waiting for another thread to perform an activity. This code originally came from HAL. In reading the Power ISA closer I realized that 'or 3,3,3' has no effect when in user-space code, which means that a spinlock-like effect in user code is going to end up with the thread stuck at low priority until the next context switch. To prevent this we are going to change from 1/3 to 1/2 as the priority levels. Change-Id: I60ee866cde37499106f5e1e1d68a0b5ddeedf403 Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/1569 Tested-by: Jenkins Server Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
* Support for master winkle.Patrick Williams2012-08-101-2/+12
| | | | | | | | | RTC: 44730 Change-Id: Ifaeecc659e1bfd8ded4744dc591fc993471519ba Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/1471 Tested-by: Jenkins Server Reviewed-by: Mark W. Wenning <wenning@us.ibm.com> Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
* cpu_spr_value syscall for SLW image build.Patrick Williams2012-07-181-22/+46
| | | | | | | | | | | | Task 44887 Change-Id: If87b6e80b974bb4cbff13844d8a3f055a17282d2 Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/1378 Tested-by: Jenkins Server Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: Douglas R. Gilbert <dgilbert@us.ibm.com> Reviewed-by: Mark W. Wenning <wenning@us.ibm.com> Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
* Support for core_activate via IPI.Patrick Williams2012-07-161-0/+6
| | | | | | | | RTC: 37009 Change-Id: I56669805c86d9659a20ad7c26e5e9860c7a248c7 Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/1087 Tested-by: Jenkins Server Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
* Initial attention handler support.Brad Bishop2012-07-161-1/+2
| | | | | | | | RTC: 40764 Change-Id: Ic5b5b3e80915cb4f0ee543baa6fe4abc51e07ad2 Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/1079 Tested-by: Jenkins Server Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
* Code optimizations.Patrick Williams2012-04-161-15/+27
| | | | | | | | | | | | | | - Reduce DCBZ and ICBI calls in memory copy and init functions. - Reduce strlen calls in trace. - Set thread to low priority while waiting on in-kernel barrier. Change-Id: Ic9c23b1e26797ff393e5862819830de60554747e Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/871 Tested-by: Jenkins Server Reviewed-by: Douglas R. Gilbert <dgilbert@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: Brian H. Horton <brianh@linux.ibm.com> Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
* Simics continuous traceMonte Copeland2012-01-111-0/+60
| | | | | | | | | Change-Id: I5f5d9c30b4cc0f0d8704fb99c10757e0f41018bf Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/603 Tested-by: Jenkins Server Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com> Reviewed-by: Mark W. Wenning <wenning@us.ibm.com> Reviewed-by: MIKE J. JONES <mjjones@us.ibm.com>
* Add copyright headers to all source files.Patrick Williams2011-08-241-0/+22
| | | | | | | Change-Id: I205f2409e56032cfc0aaf01d7e26d357f0b86373 Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/277 Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com> Tested-by: Jenkins Server
* Virtual File System module load and unloaddgilbert2011-08-171-0/+7
| | | | | | | | Change-Id: Iaa6a256a8a15ac48bfba5bc1cab292c5ac246166 Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/253 Tested-by: Jenkins Server Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* Update scratch SPR #s for P8.Patrick Williams2011-08-101-29/+0
| | | | | | | | Change-Id: Ia063a66b705b3272b7578ece420c84ac9c4c3d26 Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/224 Reviewed-by: Douglas R. Gilbert <dgilbert@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Tested-by: Jenkins Server
* Clean up mutex issues.Patrick Williams2011-08-091-5/+4
| | | | | | | | | | | | | - Final fix for mutex bug. - Document weak-consistency decisions in mutex code. - Prevent aggressive optimizations around lwsync/isync instrs. - Fix minor bug in futex_wait system call. - Optimize futex path with likely/unlikely hints. Change-Id: I26b54dee7e45bcb42195f730474b350b44f53cfc Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/233 Tested-by: Jenkins Server Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
* Add handling for HvEmu exception.Patrick Williams2011-08-011-11/+50
| | | | | | | | Change-Id: I03a7460b347b47f4653a6f457d1d7711fc0a0512 Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/209 Tested-by: Jenkins Server Reviewed-by: Douglas R. Gilbert <dgilbert@us.ibm.com> Reviewed-by: MATTHEW S. BARTH <msbarth@us.ibm.com>
* Shutdown and post status on HostBoot completionMike Jones2011-07-191-0/+35
| | | | | | | | Change-Id: If2ab46af85065b29695a1186ed331fd835944eb4 Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/204 Tested-by: Jenkins Server Reviewed-by: Mark W. Wenning <wenning@us.ibm.com> Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
* Move inline mtdec into arch/ppc.HPatrick Williams2011-04-211-0/+7
| | | | | | | | Change-Id: I65b2be9a5a5166cd946033e34cedd87345e55979 Reviewed-on: http://gfwr801.rchland.ibm.com:8080/gerrit/4 Tested-by: Jenkins Server Tested-by: Andrew J. Geissler <andrewg@us.ibm.com> Reviewed-by: Andrew J. Geissler <andrewg@us.ibm.com>
* VBU: dcbz cache lines after code image to ensure they are in the L3.Patrick Williams2011-04-071-0/+7
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* Merge of PowerHAL project up to commit:Patrick Williams2011-03-051-0/+174
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