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* p9_sbe_scominit_errors.xml -- add empty file to establish PPE mirrorJoe McGill2017-08-201-0/+27
* Add sbeError tag to all SBE related error xml filesRichard J. Knight2017-08-2013-0/+44
* Adding in writing to HRMOR for bootloaderCHRISTINA L. GRAVES2017-08-201-0/+11
* Level 2 HWP for p9_sbe_tp_chiplet_init3Anusha Reddy Rangareddygari2017-08-201-0/+17
* Level 2 HWP for p9_sbe_npll_setupAnusha Reddy Rangareddygari2017-08-201-3/+9
* Cache/Core: Istep4 procedure changes for model 9038 and aboveYue Du2017-08-203-4/+28
* Level 2 HWP for p9_sbe_nest_startclocks,p9_sbe_startclock_chipletsAnusha Reddy Rangareddygari2017-08-201-7/+1
* HWP's for p9_perv_sbe_cmn,p9_sbe_arrayinit,p9_sbe_tp_arrayinitAnusha Reddy Rangareddygari2017-08-202-14/+2
* HWP-CACHE/CORE:istep4 procedures updatesYue Du2017-08-201-0/+16
* p9_sbe_tp_switch_gears - error xml fileAnusha Reddy Rangareddygari2017-08-201-0/+41
* HWP-CORE/CACHE: Update Istep 4 procedures regressed on model 34Yue Du2017-08-203-4/+96
* p9_block_wakeup_intr Level 2Greg Still2017-08-201-0/+7
* p9_sbe_check_master_stop15 Level 2Greg Still2017-08-201-8/+27
* p9_sbe_select_ex Level 2Greg Still2017-08-201-5/+23
* p9_sbe_check_master_stop15 Level 1Greg Still2017-08-201-0/+48
* Level 2 HWP for p9_sbe_startclock_chipletsAnusha Reddy Rangareddygari2017-08-201-0/+37
* L1 and L2 for p9_l3_flush procedureCHRISTINA L. GRAVES2017-08-201-0/+62
* p9_sbe_select_ex Level 1Greg Still2017-08-201-0/+35
* Updates for p9_revert_sbe_mcs_setup, p9_sbe_mcs_setup (Level 2)Joe McGill2017-08-202-8/+2
* PPE-HWP: [Level 2] Cache/Core chiplet_reset/init/scan0+startclocksYue Du2017-08-203-0/+190
* p9_block_wakeup_intr Level 1Bilicon Patil2017-08-201-0/+35
* update p9_l2_flush HWP to build against current EKBJoe McGill2017-08-201-0/+33
* JET: Making HWP - proc_l2_flush, FAPI2.0 compliantBilicon Patil2017-08-201-0/+112
* Checking in the L2 p9_sbe_load_bootloader proceduresCHRISTINA L. GRAVES2017-08-201-0/+55
* Nest Level 2 SBE ProceduresJoe McGill2017-08-201-0/+38
* Makefile Infrastructure for SBE Level 2 HWPsSunil.Kumar2017-08-202-0/+85
* Level 2 Procedure -p9_sbe_tp_chiplet_init3Sunil.Kumar2017-08-201-0/+37
* Level 2 Procedure - p9_sbe_tp_arrayinitSunil.Kumar2017-08-201-0/+37
* Level 2 Procedure - p9_sbe_arrayinitSunil.Kumar2017-08-201-0/+37
* Shift HWP content to align with desired EKB layoutJoe McGill2017-08-201-0/+60
* HWP: [Level 2] p9_sbe_fabricint updateJoe McGill2017-08-201-55/+0
* p9_sbe_fabricinit L3 deliveryJoe McGill2017-08-201-0/+55
* PM: add p9_check_proc_config call to p9_pm_initGreg Still2017-08-206-93/+126
* BugFix: Fixed bug in FFDC collection path of pm_occ_gpe_resetPrem Shanker Jha2017-08-201-4/+9
* Level 3: For various PM HWPSangeetha T S2017-08-2017-157/+304
* Add ddr3 support back into mss_freqLuke Mulkey2017-08-191-0/+25
* Fix draminit_training error logging and unit testJacob Harvey2017-08-197-114/+214
* Replace TARGET_TYPE_MBA_CHIPLET to TARGET_TYPE_MBA, FW requestAndre Marin2017-08-183-99/+99
* p9c_mss_thermal_init required ATTRs were removed during the centaur attr purgeLuke Mulkey2017-08-182-6/+0
* Commenting unused centaur attributesLuke Mulkey2017-08-182-4/+210
* Eff_config, volt, freq for p9cLuke Mulkey2017-08-181-6/+4
* p9c_mss_draminitLuke Mulkey2017-08-182-65/+257
* L3 work for mss xmlsJacob Harvey2017-08-1851-506/+415
* Fix duplicate symbol error when linking mss and cen libsAndre Marin2017-08-186-197/+145
* Improve description of ATTR_EFF_RANK_GROUP_OVERRIDELouis Stermole2017-08-182-17/+52
* Changed API related to mss_memdiags ipl changeMatthew Hickman2017-08-185-9/+18
* PM: Level3 Special Wakeup Hardware ProcedurePrem Shanker Jha2017-08-1817-84/+683
* 24x7: Update of P9 proc config to HOMER.Prem Shanker Jha2017-08-184-0/+494
* Remove changing OITR and OIEPRBrian Vanderpool2017-08-181-4/+0
* Changed maint AUE and IAUE to recoverable during memdiagsMatthew Hickman2017-08-182-3/+5
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