summaryrefslogtreecommitdiffstats
path: root/src/import/chips/p9
Commit message (Expand)AuthorAgeFilesLines
* Update to allow DDR4-SORDIMM modules to be used [3].Evan Lojewski2019-02-131-1/+4
* Axone core initfile update to match Nimbus DD23Jenny Huynh2019-02-131-77/+568
* Added Alink changes in attributes and initfilesPretty Mariam Jacob2019-02-134-761/+618
* Memory Controller Axone initfiles - initialAdam Hale2019-02-1317-24/+1169
* Updates MCA write and read timingsStephen Glancy2019-02-138-13/+328
* Adds p9a_omi_train procedure(START)Alvin Wang2019-02-133-2/+124
* HW477626 Dangerous Elk - Reapply for all CDD12+ risk levelsJenny Huynh2019-02-131-4/+2
* PPB:New attribute ATTR_PMCR_MOST_RECENT_MODE for PMCR requestPrasad Bg Ranganath2019-02-132-1/+20
* SMF: Populates unsecure HOMER with SC2 instruction.Prem Shanker Jha2019-02-134-6/+90
* Disable maint address mode before rcd_load during NVDIMM post-restoreTsung Yeung2019-02-132-11/+67
* Adds workaround for LRDIMM to clear FIRsLi Meng2019-02-131-0/+6
* Fixes LRDIMM NTTM mode read timing for HW bugStephen Glancy2019-02-131-1/+7
* Adjust STR enter sequence to enable immediate entryTsung Yeung2019-02-133-21/+69
* Adds some BCW safe delay for LRDIMMLi Meng2019-02-121-3/+5
* Update p9a.omi_init.scom.initfileBen Gass2019-02-121-2/+0
* Move lpc_rw to a source filespashabk-in2019-02-121-1/+0
* p9_sbe_lpc_init: Skip final error check for Fleetwood GA1Joachim Fenkes2019-02-121-0/+2
* Revert "lpc_init: Correct LPC host controller timeout value"Jennifer A. Stofer2019-02-121-1/+1
* lpc_init: Correct LPC host controller timeout valueJoachim Fenkes2019-02-121-1/+1
* Introducing lpc utils source filespashabk-in2019-02-121-0/+1
* p9_sbe_lpc_init: Improve resetJoachim Fenkes2019-02-121-12/+16
* p9_sbe_lpc_init: Add final check for errorsJoachim Fenkes2019-02-122-0/+13
* p9_sbe_lpc_init: Fix timeout setupJoachim Fenkes2019-02-122-37/+27
* Update hardware procedure metadataAnusha Reddy Rangareddygari2019-02-122-2/+2
* p9_sbe_lpc_init: Fix LPC bus LRESET for DD2Joachim Fenkes2019-02-122-64/+111
* Do the real LPC reset for DD2CHRISTINA L. GRAVES2019-02-122-0/+32
* Adding in LPC and OPB timeout valuesCHRISTINA L. GRAVES2019-02-121-1/+15
* p9_sbe_lpc_init fix with GPIO resetCHRISTINA L. GRAVES2019-02-121-0/+32
* Fixing order of setting clock muxes & functional reset & removing sim only scomsCHRISTINA L. GRAVES2019-02-121-40/+5
* Adding in configurations for PNOR/LPC communicationCHRISTINA L. GRAVES2019-02-121-0/+40
* FAPI_INF entering and exiting message updatesAnusha Reddy Rangareddygari2019-02-121-2/+2
* Adding in LPC functional reset to sbe_lpc_initCHRISTINA L. GRAVES2019-02-122-7/+6
* Level 2 Procedure - p9_sbe_lpc_initSunil.Kumar2019-02-123-26/+68
* L1 Rev istep 0.(6-8,11,13,14),1.1,2.(1-13,15,18-20,22,26,27,30,32,34) V2Abhishek Agarwal2019-02-122-0/+117
* Use virtual address buffer to read mvpd ringsCorey Swenson2019-02-105-16/+72
* NVDIMM SBE Support to Trigger CSAVE - xip_customizeTsung Yeung2019-02-081-2/+3
* VDM(Part 1): Introduced new members in CME and CPMR image headersPrem Shanker Jha2019-02-081-1/+9
* Adds empty files for exp_draminit_mc and p9a_omi_trainAlvin Wang2019-02-062-0/+48
* Revert "Adds exp_draminit_mc"Jennifer A. Stofer2019-02-0511-119/+318
* Updates MWD_COARSE to run multiple patternsStephen Glancy2019-02-056-2/+142
* Adds exp_draminit_mcAlvin Wang2019-02-0513-331/+135
* P9 Obus MNFG CRC and ECC Error ThresholdChris Steffen2019-02-052-3/+149
* Adding p9a_ocmb_enableBen Gass2019-02-044-0/+277
* PM: OCC<>PGPE Interface for P9+Rahul Batra2019-01-301-2/+162
* PGPE: Write magic number in HcodeOCCShared structRahul Batra2019-01-301-1/+2
* Add missing Axone MC channel translations.Ben Gass2019-01-292-6/+34
* SMF: Defined new attribute containing unsecure HOMER memory's size.Prem Shanker Jha2019-01-291-1/+16
* Convert mss explorer and axone code to use attr accessorsLouis Stermole2019-01-291-0/+2
* eRepair(Zeppelin): Fix to invalidate centaur vpd recordsSumit Kumar2019-01-291-19/+1
* Additional core inits for Nimbus DD2.3 compatibility modesJenny Huynh2019-01-291-18/+107
OpenPOWER on IntegriCloud