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path: root/src/import/chips/p9/procedures
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* Add MSS restore_repairs functionLouis Stermole2017-02-287-6/+1113
* adjust SRAM timingsJoe McGill2017-02-281-19/+2
* Add attribute ATTR_EFF_RANK_GROUP_OVERRIDELouis Stermole2017-02-273-14/+176
* p9_rng_init_phase2 -- set NX RNG enable/security lock even if not mapping BARsJoe McGill2017-02-271-18/+18
* Adding in register_type to RDIMM decoderJacob Harvey2017-02-272-6/+56
* p9_mss_setup_bars - Setup MCFIR maskThi Tran2017-02-272-2/+79
* p9_start_cbs.C workaround for sbepibTimeout issueAnusha Reddy Rangareddygari2017-02-271-6/+25
* p9_pm_pstate_gpe_init and p9_pm_pba_init updates for PGPE bootingGreg Still2017-02-273-10/+76
* HB/IPL: ex_is_abomination workaround for hostbootYue Du2017-02-271-0/+2
* p9_pm_pstate_gpe_init Level 2Greg Still2017-02-274-0/+446
* OCC Flags/OCC Scratch UpdatesRahul Batra2017-02-271-6/+0
* Istep4: add enable auto special wakeup after core is upYue Du2017-02-271-3/+4
* cache/core/l2_stopclocks updatesYue Du2017-02-271-2/+2
* Cache HWP: DD1 VCS WorkaroundYue Du2017-02-271-1/+22
* istep 15 changesAmit Kumar2017-02-271-1/+5
* Fapi Implementation of Level2 HWP p9_stopclocksSoma BhanuTej2017-02-271-0/+1
* CORE/CACHE: core/cache/l2_stopclocks Level 2Yue Du2017-02-271-0/+8
* CORE/CACHE: add Level1 cache/l2/core stopclocks proceduresYue Du2017-02-271-10/+25
* Cache/Core: Istep4 procedure changes for model 9038 and aboveYue Du2017-02-271-72/+43
* p9_block_wakeup_intr Level 2 - fix PPE compilation issueGreg Still2017-02-271-1/+1
* HWP-CACHE/CORE:istep4 procedures updatesYue Du2017-02-271-21/+33
* HWP-CORE/CACHE: Update Istep 4 procedures regressed on model 34Yue Du2017-02-271-10/+53
* L2 stop_gpe_initAmit Kumar2017-02-271-2/+27
* PPE-HWP: [Level 2] Cache/Core chiplet_reset/init/scan0+startclocksYue Du2017-02-271-0/+182
* Removed p9_hcd_common.H because of bad mirrorCorey Swenson2017-02-271-288/+0
* Defer setup of MC multicast groups in async modeDean Sanner2017-02-272-0/+29
* Disable memory throttle change_after_syncJacob Harvey2017-02-276-36/+112
* Cleaning up and implementing L3 eff_config_thermalJacob Harvey2017-02-279-287/+508
* PM: add ATTR_PGPE_HCODE_FUNCTION_ENABLE attribute to control PGPE opsGreg Still2017-02-271-0/+27
* Adding in default raw card informationJacob Harvey2017-02-276-23/+92
* p9_sbe_chiplet_reset: Change NX_1 hang pulse period to 68sJoachim Fenkes2017-02-231-0/+1
* Procedures modified for DD1 changesSunil.Kumar2017-02-231-1/+2
* p9_sbe_chiplet_reset Level 2 update: set EC/core multicast reg3=group3Joe Dery2017-02-231-7/+7
* Fixed even/odd EX multicast setup checking ATTR_PG_EPxx clockdomainsJoe Dery2017-02-231-1/+0
* Level 2 HWP for p9_sbe_chiplet_resetAnusha Reddy Rangareddygari2017-02-231-1/+2
* IPL updates -- IPL_flow_v180Anusha Reddy Rangareddygari2017-02-231-1/+2
* Level 2 HWP for p9_sbe_chiplet_resetAnusha Reddy Rangareddygari2017-02-231-2/+0
* partial good/hang pulse updates to support all sim models/clock ratiosJoe McGill2017-02-231-0/+1
* IPL optimized codesAnusha Reddy Rangareddygari2017-02-231-5/+5
* Level 2 HWP for p9_sbe_chiplet_resetAnusha Reddy Rangareddygari2017-02-231-1/+6
* Level 2 HWPs for new IPL changesAnusha Reddy Rangareddygari2017-02-231-1/+6
* Level 2 HWP for p9_sbe_chiplet_resetAnusha Reddy Rangareddygari2017-02-231-1/+0
* Level 2 HWP for p9_sbe_chiplet_resetAnusha Reddy Rangareddygari2017-02-231-1/+5
* Level 2 HWP for p9_sbe_chiplet_resetAnusha Reddy Rangareddygari2017-02-231-2/+1
* Level 2 HWP for p9_sbe_chiplet_resetAnusha Reddy Rangareddygari2017-02-231-0/+1
* Level 2 HWP for p9_sbe_chiplet_resetAnusha Reddy Rangareddygari2017-02-231-1/+1
* Level 2 Procedure - p9_sbe_chiplet_resetSunil.Kumar2017-02-231-23/+55
* PERV SBE: Level 1 Procedure - p9_sbe_chiplet_resetAbhishek Agarwal2017-02-231-0/+78
* p9.fbc.ioo_tl.scom.initfile update for nvlinkdchowe2017-02-232-14/+47
* Level 2 p9_cpu_special_wakeupGreg Still2017-02-233-0/+81
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