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path: root/src/import/chips/p9/procedures
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* PM: Added hcode image build support for SGPE and CME.Prem Shanker Jha2016-03-219-98/+781
* Added IO GCR Access and GCR Register DetailsChris Steffen2016-03-181-0/+3890
* Nest Level 2 SBE ProceduresJoe McGill2016-03-181-0/+252
* Change procedure include pathsBrian Silver2016-03-1815-22/+22
* Fix read pointer delay to write to the proper registerBrian Silver2016-03-181-11/+11
* Add ability to disable port fails for trainingBrian Silver2016-03-182-0/+7
* Modify spd_decoder, eff_config, unit tests. Modify dependent filesAndre Marin2016-03-183-6/+6
* PM:Temp fix for build failure due to missing dependency of p9_hcode_image_build.Prem Shanker Jha2016-03-171-0/+66
* PM: Added hcode image build support for SGPE and CME.Prem Shanker Jha2016-03-171-0/+321
* Updated IO Regs to Drop Y and added Scom Access MethodChris Steffen2016-03-171-4/+4
* Add p9_mss_dump_regs wrapper, remove from proceduresBrian Silver2016-03-142-9/+0
* L2 HWPs - Fix TODOs in p9_mss_eff_grouping HWPThi Tran2016-03-144-305/+55
* Fix all incorrect copyright prologsStephen Cprek2016-03-102-2/+2
* P9 I/O X Trainadv L2Chris Steffen2016-03-106-32/+94
* P9 I/O Xbus Linktrain Fix + Updated WrapperChris Steffen2016-03-101-36/+48
* I/O Xbus Dccal CommitChris Steffen2016-03-103-0/+659
* p9_io_xbus_pre_trainadv Level 1Chris Steffen2016-03-103-0/+156
* p9_io_xbus_post_trainadv Level 1Chris Steffen2016-03-103-0/+160
* P9 I/O Xbus Link Training Level 2 CommitChris Steffen2016-03-103-0/+224
* L2 HWPs - p9_mss_setup_barsThi Tran2016-03-102-165/+1064
* L2 HWP p9_io_xbus_scominit with hwinit enabledSumit Kumar2016-03-092-43/+38
* IfCompiler: Make sure all the define statements are uniquePrachi Gupta2016-03-092-40/+75
* Initial checkin of pstate and ./pk support codes and creation of ./ppe dir.Claus Michael Olsen2016-03-082-0/+2112
* L2 stop_gpe_initAmit Kumar2016-03-052-0/+109
* Level 2 p9_pm_pba_initGreg Still2016-03-051-0/+130
* Added IO GCR Access and GCR Register DetailsChris Steffen2016-03-031-0/+31
* L2 HWPs -- p9_smp_link_layer and p9_fab_iovalidJoe McGill2016-03-033-0/+393
* L2 for psi scom initCHRISTINA L. GRAVES2016-03-033-0/+193
* Added IO GCR Access and GCR Register DetailsChris Steffen2016-03-031-0/+300
* Add read pointer delay configBrian Silver2016-03-021-0/+11
* Change WC to follow the new register block patternBrian Silver2016-03-021-7/+0
* Level 2 HWP p9_chiplet_enable_ridi.CSunil.Kumar2016-03-022-12/+61
* Level 2 p9_pm_pba_initGreg Still2016-03-023-120/+743
* Include fapi2.H into p9_pm_set_home_bar.Hcrgeddes2016-03-021-2/+2
* regression updates -- hostboot isteps and multi-chipJoe McGill2016-03-021-13/+12
* Level 2 HWP for p9_sbe_chiplet_resetAnusha Reddy Rangareddygari2016-03-021-0/+7
* p9_sbe_select_ex Level 2Greg Still2016-03-021-1/+26
* p9_xip_customize HWP - L2Prachi Gupta2016-03-021-41/+233
* Remove duplicate set of fabric topology attributesJoe McGill2016-03-021-28/+1
* Power Management Platform and Frequency AttributesGreg Still2016-03-021-20/+0
* p9_sbe_setup_boot_freq Level 2 - Setup boot frequencySudheendra K Srivathsa2016-03-021-0/+10
* FBC Level 1 proceduresJoe McGill2016-03-021-10/+0
* Nest Level 2 SBE ProceduresJoe McGill2016-03-021-0/+9
* Add base FAPI2 attribute definitionsJoe McGill2016-03-021-7/+0
* Makefile Infrastructure for SBE Level 2 HWPsSunil.Kumar2016-03-021-0/+357
* Level 2 Procedure - p9_start_cbsSunil.Kumar2016-03-011-0/+42
* Level 2 p9_pm_pba_initGreg Still2016-03-011-4/+4
* HWP-CORE/CACHE: Update Istep 4 procedures regressed on model 34Yue Du2016-03-011-10/+53
* L2 stop_gpe_initAmit Kumar2016-03-011-3/+28
* PPE-HWP: [Level 2] Cache/Core chiplet_reset/init/scan0+startclocksYue Du2016-03-011-0/+176
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