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path: root/src/import/chips/p9/procedures/hwp/perv
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* Adding trace in FAPI_ASSERTSachin Gupta2017-09-081-2/+2
* p9_sbe_tracearray: Add chip type detection to support changed p9c MC tracesJoachim Fenkes2017-09-081-47/+88
* permit IPL of Centaur with no attached DIMMs, MBAsJoe McGill2017-09-051-1/+5
* resolve Zeppelin DMI channel framelock issuesJoe McGill2017-08-301-74/+269
* p9_cen_framelock -- 2nd versionJin Song Jiang2017-08-303-0/+1686
* Optimise RamCore put_reg & get_regspashabk-in2017-08-291-261/+194
* p9_cen_ref_clk_enable -- p9 initial versionPeng Fei GOU2017-08-222-11/+93
* initial release for missing istep s0 proceduresJoe McGill2017-08-223-0/+155
* p9_sbe_common -- update TP LFIR to match RAS XML v95Joe McGill2017-08-141-1/+1
* Enable skipping sbefifo reset during p9_start_cbsMatt K. Light2017-08-141-2/+10
* L3 Update - p9_ram_core HWPsThi Tran2017-08-0714-137/+164
* Remove p9_sbe_check_master_stop15 from HostbootDan Crowell2017-07-273-261/+0
* p9_mem_pll_initf: Level 3Joachim Fenkes2017-07-262-3/+3
* TP, Nest FIR updates -- DD2 updates to match RAS XMLJoe McGill2017-07-253-2/+14
* p9_sbe_check_master_stop15: Level 3Joachim Fenkes2017-07-242-9/+15
* Optimized PPE FFDC collection frameworkAmit Tendolkar2017-07-241-6/+16
* p9_sbe_tracearray: Nimbus DD2 updatesJoachim Fenkes2017-07-201-59/+132
* Create dmi.pll.scan.initfileBen Gass2017-07-193-3/+14
* updates for thread control, ramming with STOP enabledJoe McGill2017-07-191-1/+9
* mc_pll_bucket attributeAnusha Reddy Rangareddygari2017-07-111-0/+7
* p9_spr_name_map.H -- update clocks-off spy definition for LPIDRJoe McGill2017-07-111-1/+1
* p9_mem_pll_reset: Level 3Joachim Fenkes2017-07-101-5/+5
* p9_{mem,sbe_chiplet}_pll_setup: Level 3Joachim Fenkes2017-06-301-4/+6
* Propagate "fused_core" IPL option into PU chipJoachim Fenkes2017-06-231-1/+17
* add support for OBUS PLL bucketsJoe McGill2017-06-221-3/+26
* P9_start_cbs updatesAnusha Reddy Rangareddygari2017-06-201-1/+5
* p9_sbe_tracearray: Level 3Joachim Fenkes2017-06-192-36/+33
* p9_pre_poweron, p9_set_fsi_gp_shadow: Merge flush values, fix ROOT_CTRL2(5)Joachim Fenkes2017-06-131-2/+2
* future proof EC feature attributes, add missing P9N DD2 initsJoe McGill2017-06-071-5/+5
* Adding a no error condition to the SBE_EXTRACT_RC for user returnElizabeth Liner2017-06-071-0/+2
* p9_sbe_common: Level 3Joachim Fenkes2017-06-052-21/+48
* p9_extract_sbe_rc: Level 3Joachim Fenkes2017-05-312-34/+71
* p9_start_cbs: Level 3Joachim Fenkes2017-05-312-4/+4
* Fix DEC/HDEC bit length.LiuYangFan2017-05-311-3/+3
* P9 L2err line delete HWPChen Qian2017-05-241-0/+33
* Tracearray HWP L2spashabk-in2017-05-245-364/+186
* Trace Array on SBE L2spashabk-in2017-05-242-14/+339
* L1 - trace array on SBEShakeeb2017-05-246-136/+426
* FAPI2 - Enable register ffdc supportRichard J. Knight2017-05-241-1/+0
* Add p9_proc_gettracearray procedureJoachim Fenkes2017-05-243-0/+639
* support chip swap in memory map via FBC XOR mask programmingJoe McGill2017-05-221-1/+16
* security -- split p9_chiplet_scominit and p9_chiplet_enable_ridi istepsJoe McGill2017-05-225-7/+194
* p9_nv_ref_clk_enable -- shift NV refclock field programmingJoe McGill2017-05-061-4/+4
* p9_sbe_chiplet_reset: Revert NX_1 hang pulse back to 34sJoachim Fenkes2017-05-031-1/+0
* Additional checks in p9_extract_sbe_rcSoma BhanuTej2017-04-282-3/+29
* Updates to p9_extract_sbe_rcSoma BhanuTej2017-04-132-158/+190
* literal definitionsAnusha Reddy Rangareddygari2017-04-071-4/+5
* Fix for read modify write.Santosh Balasubramanian2017-04-071-0/+4
* Fixed blue waterfall workaround bugsStephen Glancy2017-04-021-1/+0
* support customization of Nimbus DD1 PCI reference clock speedJoe McGill2017-03-291-0/+13
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