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path: root/src/import/chips/p9/procedures/hwp/nest
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* p9_htm_setup (L2) - Part 1: New files to be mirrored to HBThi Tran2016-06-1411-1147/+320
* Attribute Review - NestThi Tran2016-06-132-31/+30
* Changes in ecc data fixing so reading and writing worksCHRISTINA L. GRAVES2016-06-092-6/+32
* Translate logical mca regisers in mcs chiplet as mca target typeBen Gass2016-06-011-0/+39
* p9_scomoverride_chiplets -- remove workaround for HW354978Joe McGill2016-05-241-30/+0
* L2 - Fabric updates for multi-chip supportJoe McGill2016-05-245-0/+192
* ADU: Support PMISC NHTM control operationsThi Tran2016-05-203-17/+43
* Fix HB build failure and incorrect HWP level lableThi Tran2016-05-193-2/+3
* Changing error messages to save SBE spaceCHRISTINA L. GRAVES2016-05-181-33/+2
* L2 - Fabric updates for multi-chip supportJoe McGill2016-05-186-1945/+602
* Per Sachin's request for SBE code I changed FAPI_INF traces to FAPI_DBGCHRISTINA L. GRAVES2016-05-181-2/+2
* Fix for run_ipl for JoshCHRISTINA L. GRAVES2016-05-181-10/+0
* Change CL DMA read ttype value to 6 instead of 3CHRISTINA L. GRAVES2016-05-181-1/+1
* Remove chiplet null check in p9_build_smp_fbc_nohp.CThi Tran2016-05-181-22/+25
* L2 - p9_build_smp HWPsThi Tran2016-05-189-164/+3405
* Fix all incorrect copyright prologsStephen Cprek2016-05-182-2/+2
* Fix for data not being written correctly and for an error Dean sawCHRISTINA L. GRAVES2016-05-181-28/+21
* p9_adu_access and p9_adu_setup L2 proceduresCHRISTINA L. GRAVES2016-05-183-0/+949
* L2 - Fabric updates for multi-chip supportJoe McGill2016-05-1312-1425/+926
* change epsilon attribute definitions from arrays to scalarsJoe McGill2016-05-121-7/+13
* L2 HWPs - p9_throttle_syncThi Tran2016-05-061-12/+9
* L2 HWPs - p9_throttle_syncThi Tran2016-05-061-0/+44
* L2 - Fabric updates for multi-chip supportJoe McGill2016-05-057-0/+1843
* p9_mss_setup_bars L2 -- use vector in place of mapJoe McGill2016-05-041-18/+11
* Add relative position functionsBrian Silver2016-04-226-8/+6
* L2 p9_pcie_scominit -- correct CPLT_CONF1 WOR_CLEAR usageJoe McGill2016-04-211-4/+4
* L2 HWPs - p9_throttle_syncThi Tran2016-04-212-41/+212
* Bootloader needs to dcbz the cache before using itMarty Gloff2016-03-291-1/+2
* Adding in the exception vectorCHRISTINA L. GRAVES2016-03-291-0/+55
* PCIE phase1/phase2 initialization procedure.Gou Peng Fei2016-03-283-5/+592
* L2 HWPs - Fix TODOs in p9_mss_eff_grouping HWPThi Tran2016-03-144-305/+55
* L2 HWPs - p9_mss_setup_barsThi Tran2016-03-102-165/+1064
* L2 - p9_mss_eff_grouping HWP (p9_opt_memmap)Thi Tran2016-03-014-1822/+2080
* p9_scomoverride_chiplets - drop O,X,PCI syncclk_muxsel for HW354978Joe McGill2016-03-011-4/+33
* L2 HWPs -- p9_smp_link_layer and p9_fab_iovalidJoe McGill2016-02-267-29/+427
* L2 - p9_build_smp HWPsThi Tran2016-02-263-41/+1236
* L2 for psi scom initCHRISTINA L. GRAVES2016-02-222-7/+7
* Checking in change of HWP level from 1 to 2Joshua Hannan2016-02-221-2/+2
* Remove duplicate set of fabric topology attributesJoe McGill2016-02-221-5/+5
* Fix all incorrect copyright prologsStephen Cprek2016-02-1911-11/+11
* p9_exit_cache_contained procedure (Level 2)Thi Tran2016-02-192-14/+33
* Updates for p9_revert_sbe_mcs_setup, p9_sbe_mcs_setup (Level 2)Joe McGill2016-02-195-58/+429
* p9_chiplet_scominit Level 1Michael Dye2016-02-193-0/+134
* p9_htm_setup procedure (Level 1)Thi Tran2016-02-196-0/+1439
* p9_setup_bars L1 deliveryJoe McGill2016-02-193-0/+162
* p9_psi_scominit procedure (Level 1)Thi Tran2016-02-193-0/+158
* p9_mss_setup_bars procedure (Level 1)Thi Tran2016-02-193-0/+334
* PCIE Level 1 proceduresJoe McGill2016-02-197-76/+162
* FBC Level 1 proceduresJoe McGill2016-02-199-0/+491
* p9_throttle_sync procedure (Level 1)Thi Tran2016-02-193-0/+193
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