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* Updated proc_pcie_config to support cache inject attributesRicardo Mata Jr2019-03-191-11/+32
| | | | | | | | | | | | | | | | Change-Id: Ifa41c6a67aeaae23cc08b27e0b0e55ed975f923a CQ: SW458737 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/73255 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/73288 Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
* SW442214 - Turn off Cache Inject for FleetwoodRicardo Mata2018-08-241-8/+21
| | | | | | | | | | | | | | | Change-Id: I88d9f7fcd4822f5be624ed6d4bef6f473a73983e Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/65016 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Kevin F. Reick <reick@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/65026 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com> Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com>
* Updated pcie_scominit and pcie_config to manage systems not using PEC STACK0.Ricardo Mata2018-04-111-1/+57
| | | | | | | | | | | | | | | | | | | Defect SW417485 used to track these changes. Change-Id: I945ccd7726e2938fa07e8e3b118fc17e97111544 CQ: SW417485 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/56909 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Reviewed-by: Thi N. Tran <thi@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/56910 Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com> CI-Ready: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* p9_pcie_config -- MCD disable updatesJoe McGill2018-01-241-5/+10
| | | | | | | | | | | | | | | | | | set INTWR/TCE disable_vg and disable_scope_group switches when MCD is off Change-Id: I80ed40f6bd2fd52345c477d6e03cf5e1a22c31e9 CQ: SW414510 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/52447 Reviewed-by: Thi N. Tran <thi@us.ibm.com> Reviewed-by: Ricardo Mata <ricmata@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/52461 Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com> Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com>
* MCD disable workaround for HW423589 (option1)Joe McGill2017-12-221-0/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | chip_ec_attributes.xml add ATTR_CHIP_EC_FEATURE_HW423589_OPTION1, defines set of chips which need MCD disable for HW423589 (applied to Nimbus EC20 and 22+) p9.cxa.scom.initfile p9.int.scom.initfile p9.l2.scan.initfile p9.l3.scan.initfile p9.mmu.scom.initfile p9.ncu.scan.initfile p9.npu.scom.initfile p9.nx.scom.initfile p9.trace.scan.initfile p9.vas.scom.initfile p9_pcie_config.C set unit scope disable dials p9_sbe_scominit.C p9_pm_pba_init.C set PBA unit scope disable dial p9_pm_set_homer_bar.C change PBA0 default command scope from GROUP to NODAL p9.fbc.ab_hp.scom.initfile disable group master setup p9_setup_bars.C p9_setup_bars_defs.H skip MCD setup for HW423589_OPTION1 Change-Id: I402701bdd3266e19dbbe8c717b8a54942e3c9ee2 CQ: HW423589 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/48961 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Dean Sanner <dsanner@us.ibm.com> Reviewed-by: Thi N. Tran <thi@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/48964 Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com> Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com>
* Chip address extension workaround for HW423589 (option2), part1Joe McGill2017-12-101-2/+35
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | chip_ec_attributes.xml nest_attributes.xml p9_sbe_attributes.xml add ATTR_CHIP_EC_FEATURE_EXTENDED_ADDRESSING_MODE, defines set of chips which physically support the feature add ATTR_CHIP_EC_FEATURE_HW423589_OPTION2, defines set of chips which need extended address workaround for MCD issue (applied only to Nimbus EC 21) add ATTR_MAX_INTERLEAVE_GROUP_SIZE, to restrict maximum size of memory groups formed. Written by p9_mss_eff_grouping. For HW423589_OPTION2, this will default to 512GB add ATTR_FABRIC_ADDR_EXTENSION_[GROUP|CHIP]_ID, to hold extended address configuration. Written by p9_sbe_fabricinit (SBE) and p9_mss_eff_grouping (HB). For HW423589_OPTION2, this will default to 0b0000_111, consuming all chip ID bits for extended addressing. p9_fbc_utils.C p9_fbc_utils.H extend p9_fbc_utils_get_chip_base_address to support address extension, now outputs set of ranges in each msel based on ATTR_FABRIC_ADDR_EXTENSION[GROUP|CHIP]_ID maintain original function for PPE platform which requires knowledge of non-aliased base addresses only, for code size p9_mss_eff_grouping.C p9_mss_eff_grouping_errors.xml set ATTR_FABRIC_ADDR_EXTENSION[GROUP|CHIP]_ID for HB platform restrict size of groups formed for HW423589_OPTION2 p9_sbe_fabricinit.C set ATTR_FABRIC_ADDR_EXTENSION[GROUP|CHIP]_ID for SBE platform configure FBC/NMMU extended addressing registers p9_setup_bars.C p9_setup_bars_defs.H p9_setup_bars_errors.xml add general purpose support for extended address mode for HW423589_OPTION2, configure static MCD setup p9_hcode_image_defines.H p9_hcode_image_build.C customize SGPE image with address extension configuration to apply p9.cxa.scom.initfile p9.int.scom.initfile p9.l2.scom.initfile p9.l3.scom.initfile p9.ncu.scom.initfile p9.nx.scom.initfile p9.trace.scan.initfile p9.vas.scom.initfile p9_hcd_cache_scominit.C p9_hcd_cache_scominit.c p9_pcie_config.C set unit address extension configuration on supported chips p9_rng_init_phase2.C p9_sbe_scominit.C p9c_set_inband_addr.C p9_sbe_load_bootloader.C p9_sbe_mcs_setup.C adapt to alterations in p9_fbc_utils_get_chip_base_address Change-Id: I614d566c073f1169f04f647057e6e85889f1c237 CQ: HW423589 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/48576 Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Gregory S. Still <stillgs@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/48893 Reviewed-by: Hostboot Team <hostboot@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Tested-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* Added CI throttling support, HW init updates, and fixed a bug with tce arb.Ricardo Mata2017-11-211-3/+22
| | | | | | | | | | | | | | | | | | Change-Id: Id71511d75e526e567fd8ba6b56551adfe2806fa4 CQ: SW407851 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/49390 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Thi N. Tran <thi@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/49392 Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* PHB4 init updates per Ross Leaven's requestRicardo Mata2017-07-101-3/+19
| | | | | | | | | | | | | | | Change-Id: Iee96c7640b52e624ef54ebe676bda4a185af4241 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/42838 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-by: Jenny Huynh <jhuynh@us.ibm.com> Reviewed-by: Prachi Gupta <pragupta@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/42840 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com> Reviewed-by: Dean Sanner <dsanner@us.ibm.com>
* L3 update -- p9_pcie_configJoe McGill2017-06-111-126/+222
| | | | | | | | | | | | | | | | | | | | update owner comments address remaining todo items define constants to replace hardcoded bit definitions cleanup trace messages Change-Id: Ibc075046d4494d3ec5bf85780ee58c919c6b68a2 CQ: HW363246 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/41116 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Matt K. Light <mklight@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/41127 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* support chip swap in memory map via FBC XOR mask programmingJoe McGill2017-05-221-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | p9_sbe_fabricinit.C p9.fbc.ab_hp.scom.initfile set PB_CFG_XLATE_ADDR_TO_ID based on XOR of effective & absolute FBC group/chip ID attribute values, prior to island mode FBC init cleanup register/field constant todos p9_fbc_utils.C parametrize p9_fbc_utils_get_chip_base_address to support calculation of origin address based on: - effective FBC group/chip ID attributes (EFF_FBC_GRP_CHIP_IDS) - effective FBC drawer origin -- effective FBC group ID + chip ID=0 (EFF_FBC_GRP_ID_ONLY) - absolute FBC group/chip ID attributes (ABS_FBC_GRP_CHIP_IDS) p9_sbe_mcs_setup.C (MCS BAR for HB dcbz support) set p9_fbc_utils_get_chip_base_address call to use EFF_FBC_GRP_ID_ONLY configures BAR address based on drawer base + HRMOR p9_sbe_load_bootloader.C set p9_fbc_utils_get_chip_base_address call for bootloader load to use EFF_FBC_GRP_ID_ONLY (drawer) store XSCOM/LPC BAR into bootloader config data structure in exception vector (based on chip offset) p9_mss_eff_grouping.C (MCS/HTM BARs) p9_pcie_config.C (PCIE MMIO BARs) p9_rng_init_phase2.C / p9_hcode_image_build.C (NX RNG BAR) p9_sbe_scominit.C (XSCOM/LPC BARs) p9_setup_bars.C (MCD, FSP/PSI/NPU/INT MMIO BARs) set p9_fbc_utils_get_chip_base_address call to use EFF_FBC_GRP_CHIP_IDS p9_setup_sbe_config.C p9_sbe_attr_setup.C transmit ATTR_PROC_EFF_FABRIC_[GROUP/CHIP]_ID via scratch6 mailbox p9_xip_customize.C init ATTR_PROC_EFF_FABRIC_[GROUP_CHIP]_ID to zero in image Change-Id: I3f30bc81a986872c2e7f47422b96bf7bf7c59b06 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/37261 Reviewed-by: Matt K. Light <mklight@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Thi N. Tran <thi@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/37777 Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* PCI FIR initialization updatesJoe McGill2017-01-171-65/+71
| | | | | | | | | | | | | | | Change-Id: I11fe29dca7e9c253e1d1c06251663530995e6ca3 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/33671 Reviewed-by: Thi N. Tran <thi@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Dev-Ready: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-by: Zane C. Shelley <zshelle@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/33672 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com> Reviewed-by: William G. Hoffa <wghoffa@us.ibm.com>
* FIR updatesJoe McGill2016-09-161-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | p9.cme.scan.initfile add CME LFIR settings add EQ pervasive LFIR/XFIR settings p9.npu.scom.initfile update NPU_0/NPU_1 LFIR settings p9.psi.scom.initfile add PSI LFIR settings p9_sbe_scominit add LPC LFIR settings update placeholder for pervasive LFIR/XFIR settings (for Nest/XBUS/MC/OBUS/PCIE) p9_sbe_tp_chiplet_init3 update TP pervasive LFIR settings p9_pcie_config fix bug affecting PHBBAR programming (causing invalid BAR matches) p9_pcie_scominit update PEC LFIR settings p9_setup_bars_defs update MCD LFIR settings Change-Id: I8aaf7f40e96cde2fbd6e44fd0451e0add6584b77 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/29197 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/29232 Reviewed-by: Hostboot Team <hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* L2 HWP -- p9_setup_barsJoe McGill2016-08-251-37/+68
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | p9_setup_bars initial relase -- program FSP/PSI/NPU BARs & configure MCD nest_attributes proc_setup_bars_attributes adjust scope of BAR base address attributes from chip->system change to reflect offset from base of chip address range, rather than absolute address p9_fbc_utils modify p9_fbc_utils_get_chip_base_address() to output base of each on chip region, consider policy affecting placement of mirrrored memory p9_mss_eff_grouping p9_sbe_load_bootloader p9_sbe_mcs_setup adapt to p9_fbc_utils_get_chip_base_address() changes p9_sbe_scominit adapt to p9_fbc_utils_get_chip_base_address() / attribute scope changes add placeholder for FIR register initialization p9_pcie_config adapt to p9_fbc_utils_get_chip_base_address() / attribute scope changes skip programming of INT resources Change-Id: I62e1766fbe8366168cc3f1b9b43c64f48659aec0 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/27841 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Reviewed-by: Peng Fei Gou <shgoupf@cn.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Thi N. Tran <thi@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/27850 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* Update prologs of mirrored files to apache licenseStephen Cprek2016-08-051-8/+14
| | | | | | | | Change-Id: I25a782f6f8af801beb35f541f6076c482b78bf8e Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/27920 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Reviewed-by: Matthew A. Ploetz <maploetz@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* Made updates to reflect p9_io_intialization V1.3 doc.Ricardo Mata2016-08-011-58/+63
| | | | | | | | | | | | Change-Id: I0286b68bf4923d24fc4464713401a2ed806120be Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/27383 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/27385 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
* PCIE phase1/phase2 initialization procedure.Gou Peng Fei2016-03-281-2/+252
| | | | | | | | | | | | | | | | | | | Changes included: 1) p9_pcie_scominit for phase1. 2) p9_pcie_config for phase2. 3) Add attribute values for phase1. Change-Id: Id9afc0edaa716b0fdc22ac9035ad4b8ebfecb38f Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/20885 Tested-by: Jenkins Server Tested-by: Hostboot CI Tested-by: PPE CI Reviewed-by: Thi N. Tran <thi@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/20841 Tested-by: FSP CI Jenkins Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* Fix all incorrect copyright prologsStephen Cprek2016-02-191-1/+1
| | | | | | | | | | | | | Change-Id: Ie5a6f67a1f0dfbd86c8facee2b635e388d692589 Original-Change-Id: I293e79b5a37bf4180f6dd19d259fac3434327fb3 Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/22759 Tested-by: Jenkins Server Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-by: PRACHI GUPTA <pragupta@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/23105 Reviewed-by: Christian Geddes <crgeddes@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* PCIE Level 1 proceduresJoe McGill2016-02-191-25/+11
| | | | | | | | | | | | | | | Shells for p9_pcie_scominit, p9_pcie_config, p9_pcie_hotplug_control Supporting attribute definitions Change-Id: Ifdfee9a0aee08624fdc279355a5f46e0049417e7 Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/21599 Tested-by: Jenkins Server Reviewed-by: Thi N. Tran <thi@us.ibm.com> Reviewed-by: CHRISTINA L. GRAVES <clgraves@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/23166 Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Tested-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* Shift HWP content to align with desired EKB layoutJoe McGill2016-02-191-0/+59
Change-Id: I0e43617142a9ce830bf990987fa57bbb81537bce Original-Change-Id: Id22bf63b31e0631685139b9695c5a443cf4f2298 Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/20714 Tested-by: Jenkins Server Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/23148 Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Tested-by: Daniel M. Crowell <dcrowell@us.ibm.com>
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