Chip address extension workaround for HW423589 (option2), part1

chip_ec_attributes.xml
nest_attributes.xml
p9_sbe_attributes.xml
  add ATTR_CHIP_EC_FEATURE_EXTENDED_ADDRESSING_MODE, defines
    set of chips which physically support the feature
  add ATTR_CHIP_EC_FEATURE_HW423589_OPTION2, defines set of chips
    which need extended address workaround for MCD issue (applied only
    to Nimbus EC 21)
  add ATTR_MAX_INTERLEAVE_GROUP_SIZE, to restrict maximum size of
    memory groups formed.  Written by p9_mss_eff_grouping.  For
    HW423589_OPTION2, this will default to 512GB
  add ATTR_FABRIC_ADDR_EXTENSION_[GROUP|CHIP]_ID, to hold
    extended address configuration.  Written by p9_sbe_fabricinit (SBE)
    and p9_mss_eff_grouping (HB).  For HW423589_OPTION2, this will
    default to 0b0000_111, consuming all chip ID bits for extended
    addressing.

p9_fbc_utils.C
p9_fbc_utils.H
  extend p9_fbc_utils_get_chip_base_address to support address
  extension, now outputs set of ranges in each msel based on
  ATTR_FABRIC_ADDR_EXTENSION[GROUP|CHIP]_ID

  maintain original function for PPE platform which requires
  knowledge of non-aliased base addresses only, for code size

p9_mss_eff_grouping.C
p9_mss_eff_grouping_errors.xml
  set ATTR_FABRIC_ADDR_EXTENSION[GROUP|CHIP]_ID for HB platform
  restrict size of groups formed for HW423589_OPTION2

p9_sbe_fabricinit.C
  set ATTR_FABRIC_ADDR_EXTENSION[GROUP|CHIP]_ID for SBE platform
  configure FBC/NMMU extended addressing registers

p9_setup_bars.C
p9_setup_bars_defs.H
p9_setup_bars_errors.xml
  add general purpose support for extended address mode
  for HW423589_OPTION2, configure static MCD setup

p9_hcode_image_defines.H
p9_hcode_image_build.C
  customize SGPE image with address extension configuration to apply

p9.cxa.scom.initfile
p9.int.scom.initfile
p9.l2.scom.initfile
p9.l3.scom.initfile
p9.ncu.scom.initfile
p9.nx.scom.initfile
p9.trace.scan.initfile
p9.vas.scom.initfile
p9_hcd_cache_scominit.C
p9_hcd_cache_scominit.c
p9_pcie_config.C
  set unit address extension configuration on supported chips

p9_rng_init_phase2.C
p9_sbe_scominit.C
p9c_set_inband_addr.C
p9_sbe_load_bootloader.C
p9_sbe_mcs_setup.C
  adapt to alterations in p9_fbc_utils_get_chip_base_address

Change-Id: I614d566c073f1169f04f647057e6e85889f1c237
CQ: HW423589
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/48576
Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Gregory S. Still <stillgs@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/48893
Reviewed-by: Hostboot Team <hostboot@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Tested-by: Daniel M. Crowell <dcrowell@us.ibm.com>

1 files changed, 35 insertions, 2 deletions

diff --git a/src/import/chips/p9/procedures/hwp/nest/p9_pcie_config.C b/src/import/chips/p9/procedures/hwp/nest/p9_pcie_config.C
index 95d9ace99..9026870ba 100644
--- a/src/import/chips/p9/procedures/hwp/nest/p9_pcie_config.C
+++ b/src/import/chips/p9/procedures/hwp/nest/p9_pcie_config.C
@@ -41,7 +41,9 @@
 
 #include <p9_misc_scom_addresses.H>
 #include <p9_misc_scom_addresses_fld.H>
-
+#include <p9n2_misc_scom_addresses.H>
+#include <p9n2_misc_scom_addresses_fld.H>
+#include <p9_fbc_utils.H>
 
 //------------------------------------------------------------------------------
 // Constant definitions
@@ -86,11 +88,13 @@ fapi2::ReturnCode p9_pcie_config(
     fapi2::ATTR_PROC_PCIE_BAR_SIZE_Type l_bar_sizes;
     fapi2::ATTR_CHIP_EC_FEATURE_HW363246_Type l_hw363246;
     fapi2::ATTR_CHIP_EC_FEATURE_HW410503_Type l_hw410503;
+    fapi2::ATTR_CHIP_EC_FEATURE_EXTENDED_ADDRESSING_MODE_Type l_extended_addressing_mode;
     fapi2::Target<fapi2::TARGET_TYPE_SYSTEM> FAPI_SYSTEM;
 
     fapi2::buffer<uint64_t> l_buf = 0;
     uint8_t l_attr_proc_pcie_iovalid_enable = 0;
-    uint64_t l_base_addr_nm0, l_base_addr_nm1, l_base_addr_m, l_base_addr_mmio;
+    std::vector<uint64_t> l_base_addr_nm0, l_base_addr_nm1, l_base_addr_m;
+    uint64_t l_base_addr_mmio;
 
     auto l_pec_chiplets_vec = i_target.getChildren<fapi2::TARGET_TYPE_PEC>(
                                   fapi2::TARGET_STATE_FUNCTIONAL);
@@ -138,6 +142,11 @@ fapi2::ReturnCode p9_pcie_config(
                            l_hw363246),
              "Error from FAPI_ATTR_GET (ATTR_CHIP_EC_FEATURE_HW363246)");
 
+    FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_EC_FEATURE_EXTENDED_ADDRESSING_MODE,
+                           i_target,
+                           l_extended_addressing_mode),
+             "Error from FAPI_ATTR_GET (ATTR_CHIP_EC_FEATURE_EXTENDED_ADDRESSING_MODE)");
+
     // initialize functional PEC chiplets
     for (auto l_pec_chiplet : l_pec_chiplets_vec)
     {
@@ -153,6 +162,30 @@ fapi2::ReturnCode p9_pcie_config(
                                l_attr_proc_pcie_iovalid_enable));
         FAPI_DBG("l_attr_proc_pcie_iovalid_enable: %#x", l_attr_proc_pcie_iovalid_enable);
 
+        // configure extended addressing facility
+        if (l_extended_addressing_mode)
+        {
+            uint8_t l_addr_extension_group_id;
+            uint8_t l_addr_extension_chip_id;
+            FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_FABRIC_ADDR_EXTENSION_GROUP_ID,
+                                   FAPI_SYSTEM,
+                                   l_addr_extension_group_id),
+                     "Error from FAPI_ATTR_GET (ATTR_FABRIC_ADDR_EXTENSION_GROUP_ID)");
+            FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_FABRIC_ADDR_EXTENSION_CHIP_ID,
+                                   FAPI_SYSTEM,
+                                   l_addr_extension_chip_id),
+                     "Error from FAPI_ATTR_GET (ATTR_FABRIC_ADDR_EXTENSION_CHIP_ID)");
+
+            FAPI_TRY(fapi2::getScom(l_pec_chiplet, P9N2_PEC_ADDREXTMASK_REG, l_buf),
+                     "Error from getScom (P9N2_PEC_ADDREXTMASK_REG)");
+            l_buf.insertFromRight<P9N2_PEC_ADDREXTMASK_REG_PE,
+                                  P9N2_PEC_ADDREXTMASK_REG_PE_LEN>(
+                                      (l_addr_extension_group_id << 3) |
+                                      l_addr_extension_chip_id);
+            FAPI_TRY(fapi2::putScom(l_pec_chiplet, P9N2_PEC_ADDREXTMASK_REG, l_buf),
+                     "Error from putScom (P9N2_PEC_ADDREXTMASK_REG)");
+        }
+
         // Phase2 init step 1
         // NestBase+0x00
         // Set bits 00:03 = 0b0001 Set hang poll scale