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path: root/src/import/chips/p9/procedures/hwp/memory
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* Change R17/R16 bits for 1R DIMM config depending on slot configsBrian Silver2016-12-161-4/+4
* Add settings for DDR 2N modeBrian Silver2016-12-145-21/+55
* Add Memory Subsystem FIR supportBrian Silver2016-12-0818-81/+1088
* Add rank config MRW override to plug rulesBrian Silver2016-12-084-27/+220
* Add EC workaround for PHY training bad bit processingBrian Silver2016-12-072-1/+31
* Add common functionality between RCD and data buffer control word APIAndre Marin2016-12-076-304/+400
* Adds WR VREF error loggingStephen Glancy2016-12-073-24/+120
* Add a common MRS engine to set up CCS instructions and UTs.Andre Marin2016-12-065-222/+390
* Add DDR4 data buffer control words (BCWs) infrastructure & UT's.Andre Marin2016-12-069-18/+814
* Fixing bulk_pwr_throttles calculationsJacob Harvey2016-12-0510-96/+411
* Add to the scom blastah unit testsBrian Silver2016-12-051-0/+3
* Memory lab tool updates for mss_check_bandwidth and mss_power_controlsMichael Pardeik2016-12-051-1/+1
* Added error count mode 2 to MCBIST labStephen Glancy2016-11-152-0/+17
* Add LRDIMM to translation register infrastructure and unit tests.Andre Marin2016-11-143-721/+1388
* Change mss_scrub timeout to account for slow MCBISTBrian Silver2016-11-141-1/+1
* deplib of p9_mss_bulk_pwr_throttles for p9_mss_eff_config_thermalMatt K. Light2016-11-111-0/+1
* Added default values if no power_curve attrsJacob Harvey2016-11-113-20/+87
* Change memdiags interfaces for PRDBrian Silver2016-11-113-75/+39
* Add EC feature levels to MSS workaroundsBrian Silver2016-11-118-89/+295
* Fix RCW infrastructure for LRDIMM and RDIMMsAndre Marin2016-11-1012-240/+484
* Enable read VREF calibrationBrian Silver2016-11-097-64/+186
* sector buffer,pulse mode attributesAnusha Reddy Rangareddygari2016-11-081-0/+60
* Add DP16 workarounds for Nimbus DD1.0Brian Silver2016-11-085-3/+300
* Change dll cal poll; look for invalid rather than successBrian Silver2016-11-071-2/+2
* Update mss_decode_shadow_regs to use library MRS decodersLouis Stermole2016-11-0410-138/+581
* Change mss training to fail on any disabled bitsBrian Silver2016-11-041-4/+2
* Added WR VREF latch commandStephen Glancy2016-11-0412-16/+837
* Change lab memory init to poll, remove read phaseBrian Silver2016-11-043-6/+59
* Add LRDIMM SPD revision tableAndre Marin2016-11-041-82/+264
* Add raw card A1 (0x20) to SPD processingBrian Silver2016-11-043-17/+65
* Power Thermal initJacob Harvey2016-11-037-38/+259
* Implement L2 eff_config_thermal, bulk_pwr_throttleJacob Harvey2016-11-0115-317/+737
* Change bad bit processing to process bad bit attributesBrian Silver2016-10-316-101/+451
* Add magic port capabilties for DDR PHYBrian Silver2016-10-314-21/+138
* Fixed CL and timing bugs, unit test augmentationsStephen Glancy2016-10-3114-761/+1844
* Change ADR output registers for init during resetBrian Silver2016-10-301-2/+2
* Change parity error FIR clear from after MRS to beforeBrian Silver2016-10-301-3/+4
* Implement p9_mss_throttle_memJacob Harvey2016-10-283-17/+72
* Add mss throttle files L1Andre Marin2016-10-282-0/+109
* Started implementation of bulk_pwr_throttlesJacob Harvey2016-10-279-525/+632
* Modifying ATTRs for memory power thermalJacob Harvey2016-10-251-31/+46
* Fixed 1R WR DQS update issueStephen Glancy2016-10-251-1/+27
* Implement MRW attributes; dram_clks, db_util, 2n_modeBrian Silver2016-10-251-8/+5
* Fix p9_mss_utils_to_throttle, create throttles API, attribute cleanupAndre Marin2016-10-251-20/+39
* Fix throttle procedure & MSS attribute clean upAndre Marin2016-10-251-9/+10
* Add mss throttle files L1Andre Marin2016-10-251-0/+81
* Modifying ATTRs for memory power thermalJacob Harvey2016-10-243-19/+93
* Add mss throttle files L1Andre Marin2016-10-242-0/+110
* Add remaining DP16 duty cycle registersBrian Silver2016-10-211-1/+12
* Add ATTR_MSS_MRW_POWER_CONTROL_REQUESTEDJacob Harvey2016-10-201-2/+25
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