| Commit message (Expand) | Author | Age | Files | Lines |
* | Revert "Adds exp_draminit_mc" | Jennifer A. Stofer | 2019-02-05 | 1 | -1/+1 |
* | Adds exp_draminit_mc | Alvin Wang | 2019-02-05 | 1 | -2/+2 |
* | Moves fir reg to generic folder | Alvin Wang | 2018-12-17 | 1 | -1/+1 |
* | Updates training steps factory to be LRDIMM capable | Stephen Glancy | 2018-10-15 | 1 | -1/+6 |
* | Moves count_dimm to be in the memory generic folder | Stephen Glancy | 2018-04-05 | 1 | -1/+1 |
* | Updates training advanced and adds custom WR CTR | Stephen Glancy | 2018-01-13 | 1 | -2/+2 |
* | Worksaround AWAN simulation failure | Stephen Glancy | 2017-11-27 | 1 | -1/+3 |
* | Updates dramint training structure | Stephen Glancy | 2017-11-10 | 1 | -1/+7 |
* | Move around recording bad bits to prevent reconfig | Jacob Harvey | 2017-10-11 | 1 | -1/+6 |
* | Updates error paths for PRD FIR checking | Stephen Glancy | 2017-10-02 | 1 | -1/+1 |
* | Implementing draminit_training_adv | Jacob Harvey | 2017-08-29 | 1 | -1/+5 |
* | Fix draminit_training error logging and unit test | Jacob Harvey | 2017-08-19 | 1 | -74/+18 |
* | L3 draminit and mss_lib | Jacob Harvey | 2017-07-26 | 1 | -13/+15 |
* | Set HB to ignore draminit_training fails | Jacob Harvey | 2017-06-30 | 1 | -21/+59 |
* | Added register reset functionality for DD2 | Stephen Glancy | 2017-06-07 | 1 | -2/+7 |
* | Turn off PHY refresh for RD_CNTR - RD_VREF | Jacob Harvey | 2017-06-07 | 1 | -0/+4 |
* | Remove ZQCAL redundant CCS inst, move to draminit_training | Andre Marin | 2017-05-25 | 1 | -21/+24 |
* | L3 procedure work for p9_mss_draminit_training | Jacob Harvey | 2017-04-07 | 1 | -2/+2 |
* | Disable RTT_WR during WR_LEVEL cal step, and set equivalent terminations | Louis Stermole | 2017-03-15 | 1 | -34/+2 |
* | Updates to run HW VREF cal by default | Stephen Glancy | 2017-03-01 | 1 | -6/+2 |
* | Set MSS blue waterfall workaround to only run after coarse rd/wr cal step | Louis Stermole | 2017-02-10 | 1 | -2/+7 |
* | Add DP16 API and unit testing needed to set PBA mode for LRDIMMs | Andre Marin | 2017-02-07 | 1 | -2/+1 |
* | Added periodic cal fix - fixes bad delays | Stephen Glancy | 2017-01-30 | 1 | -0/+4 |
* | Move SEQ ODT Write Configuration from draminit_training to scominit | Andre Marin | 2017-01-16 | 1 | -7/+5 |
* | Fixed WR VREF settings bug | Stephen Glancy | 2017-01-04 | 1 | -0/+1 |
* | Add Memory Subsystem FIR support | Brian Silver | 2016-12-08 | 1 | -1/+6 |
* | Added WR VREF latch command | Stephen Glancy | 2016-11-04 | 1 | -1/+1 |
* | Change bad bit processing to process bad bit attributes | Brian Silver | 2016-10-31 | 1 | -0/+21 |
* | Add disabled bit processing for DDR PHY initial calibration | Brian Silver | 2016-10-19 | 1 | -2/+21 |
* | Changes to limit DLL cal on spare DP8, stop CSS before starting | Brian Silver | 2016-10-16 | 1 | -9/+6 |
* | Add register API for PHY Rank Pair registers | Louis Stermole | 2016-09-20 | 1 | -1/+1 |
* | Change SEQ timings, SEQ ODT, WC config and DQS polarity | Brian Silver | 2016-09-12 | 1 | -5/+0 |
* | Add implementation of ATTR_MSS_MRW_PERIODIC_MEMCAL_MODE_OPTIONS | Brian Silver | 2016-08-17 | 1 | -2/+3 |
* | Update prologs of mirrored files to apache license | Stephen Cprek | 2016-08-05 | 1 | -8/+14 |
* | Change procedures to support unpopulated MC | Brian Silver | 2016-07-13 | 1 | -0/+9 |
* | Update error handling for IPL procedures | Brian Silver | 2016-06-10 | 1 | -35/+1 |
* | Add eff_config functionality needed for RIT, fix cas_latency bug & attr files | Andre Marin | 2016-05-19 | 1 | -2/+2 |
* | Change PHY PC, RC and DP16 register blocks to functional API | Brian Silver | 2016-05-04 | 1 | -1/+1 |
* | Change draminit_mc mcbist subtest to perform compares rather than ECC | Brian Silver | 2016-04-21 | 1 | -1/+4 |
* | Add phy control error checking, clean up dp16, apb | Brian Silver | 2016-03-22 | 1 | -1/+1 |
* | Change procedure include paths | Brian Silver | 2016-03-18 | 1 | -1/+1 |
* | Add ability to disable port fails for training | Brian Silver | 2016-03-18 | 1 | -0/+4 |
* | Add p9_mss_dump_regs wrapper, remove from procedures | Brian Silver | 2016-03-14 | 1 | -2/+0 |
* | Change WC to follow the new register block pattern | Brian Silver | 2016-03-02 | 1 | -7/+0 |
* | Add dump_regs for PHY registers | Brian Silver | 2016-02-22 | 1 | -2/+2 |
* | Change polling to include probes, add granular training controls | Brian Silver | 2016-02-22 | 1 | -10/+49 |
* | Add PHY RC class, update setup cal for 2D wc/rc | Brian Silver | 2016-02-22 | 1 | -1/+0 |
* | Changes related to model 31, attr changes for sim latencies | Brian Silver | 2016-02-22 | 1 | -1/+3 |
* | Added mss::get/putScom | Brian Silver | 2016-02-22 | 1 | -3/+3 |
* | Initial commit of memory subsystem | Brian Silver | 2016-02-22 | 1 | -3/+129 |