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path: root/src/import/chips/p9/procedures/hwp/memory/lib
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* Fix fapi2::current_err bug in checker.HJacob Harvey2017-01-125-103/+101
* Add rdtag change delay API and unit tests.Andre Marin2017-01-121-27/+68
* Add state machine for mrep and dwl training and unit testsAndre Marin2017-01-064-1/+465
* Default Enable Address hash in ECCShelton Leung2017-01-041-1/+3
* Change sf_read to run multiple ports to end of MCBIST rangeBrian Silver2017-01-045-55/+210
* Change MCBIST error message to reflect bits checkedBrian Silver2017-01-041-1/+1
* Fixed WR VREF settings bugStephen Glancy2017-01-043-44/+45
* Add missing raw card reference (C2) for RDIMMs and UTsAndre Marin2017-01-042-0/+28
* Add MSS customization support from CRP0 Lx MVPDJoe McGill2017-01-048-128/+191
* Add BCW API for rank presence, buffer training, mrep timing and UTs.Andre Marin2017-01-034-66/+490
* Move MRS attributes to eff_config to calc LRDIMMsJacob Harvey2017-01-0311-148/+739
* Add read cmd, precharge all cmd, and read cmd CCS instruction and unit testsAndre Marin2017-01-034-72/+383
* Updating shmoo to use per-lane failsStephen Glancy2016-12-211-0/+8
* Improve detection and description for MEMVPD_POS issuesDan Crowell2016-12-201-4/+5
* Add minor minor version feature support to getecidBrian Silver2016-12-191-10/+21
* Change R17/R16 bits for 1R DIMM config depending on slot configsBrian Silver2016-12-161-4/+4
* Add settings for DDR 2N modeBrian Silver2016-12-145-21/+55
* Add Memory Subsystem FIR supportBrian Silver2016-12-0812-63/+982
* Add rank config MRW override to plug rulesBrian Silver2016-12-084-27/+220
* Add EC workaround for PHY training bad bit processingBrian Silver2016-12-072-1/+31
* Add common functionality between RCD and data buffer control word APIAndre Marin2016-12-076-304/+400
* Adds WR VREF error loggingStephen Glancy2016-12-073-24/+120
* Add a common MRS engine to set up CCS instructions and UTs.Andre Marin2016-12-065-222/+390
* Add DDR4 data buffer control words (BCWs) infrastructure & UT's.Andre Marin2016-12-068-15/+794
* Fixing bulk_pwr_throttles calculationsJacob Harvey2016-12-055-49/+360
* Add to the scom blastah unit testsBrian Silver2016-12-051-0/+3
* Memory lab tool updates for mss_check_bandwidth and mss_power_controlsMichael Pardeik2016-12-051-1/+1
* Added error count mode 2 to MCBIST labStephen Glancy2016-11-152-0/+17
* Add LRDIMM to translation register infrastructure and unit tests.Andre Marin2016-11-143-721/+1388
* Added default values if no power_curve attrsJacob Harvey2016-11-112-9/+54
* Change memdiags interfaces for PRDBrian Silver2016-11-113-75/+39
* Add EC feature levels to MSS workaroundsBrian Silver2016-11-118-89/+295
* Fix RCW infrastructure for LRDIMM and RDIMMsAndre Marin2016-11-1012-240/+484
* Enable read VREF calibrationBrian Silver2016-11-097-64/+186
* sector buffer,pulse mode attributesAnusha Reddy Rangareddygari2016-11-081-0/+60
* Add DP16 workarounds for Nimbus DD1.0Brian Silver2016-11-084-3/+297
* Change dll cal poll; look for invalid rather than successBrian Silver2016-11-071-2/+2
* Update mss_decode_shadow_regs to use library MRS decodersLouis Stermole2016-11-0410-138/+581
* Change mss training to fail on any disabled bitsBrian Silver2016-11-041-4/+2
* Added WR VREF latch commandStephen Glancy2016-11-0411-15/+836
* Change lab memory init to poll, remove read phaseBrian Silver2016-11-042-1/+25
* Add LRDIMM SPD revision tableAndre Marin2016-11-041-82/+264
* Add raw card A1 (0x20) to SPD processingBrian Silver2016-11-042-17/+64
* Power Thermal initJacob Harvey2016-11-033-33/+222
* Implement L2 eff_config_thermal, bulk_pwr_throttleJacob Harvey2016-11-018-232/+576
* Change bad bit processing to process bad bit attributesBrian Silver2016-10-315-101/+430
* Add magic port capabilties for DDR PHYBrian Silver2016-10-313-6/+117
* Fixed CL and timing bugs, unit test augmentationsStephen Glancy2016-10-3111-714/+1811
* Change ADR output registers for init during resetBrian Silver2016-10-301-2/+2
* Started implementation of bulk_pwr_throttlesJacob Harvey2016-10-275-507/+499
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