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path: root/src/import/chips/p9/procedures/hwp/memory/lib/workarounds/dp16_workarounds.H
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* Adds read wr_vref function to support P9 NVDIMM post restoreTsung Yeung2018-02-181-12/+0
* Updates WR VREF for characterization resultsStephen Glancy2018-01-131-1/+235
* Updates dramint training structureStephen Glancy2017-11-101-1/+1
* Set blue waterfall range to 1-4 for all freqsJacob Harvey2017-11-021-0/+18
* Update HPW Level for MSS API libraryAndre Marin2017-11-011-3/+3
* Increment red_waterfall for low vdn fixJacob Harvey2017-09-261-0/+45
* Remove reset_dll from scominit, enable delay line tap pointsAndre Marin2017-07-251-50/+0
* Fixes DQS align workaround formattingStephen Glancy2017-06-131-1/+1
* Remove ZQCAL redundant CCS inst, move to draminit_trainingAndre Marin2017-05-251-1/+1
* Added DQS alignment workaroundStephen Glancy2017-05-121-0/+148
* Change RD_CTR workaround val and update attr nameJacob Harvey2017-05-031-2/+2
* Added read ctr bad delay workaroundStephen Glancy2017-04-271-0/+76
* Updates to run HW VREF cal by defaultStephen Glancy2017-03-011-0/+27
* Added periodic cal fix - fixes bad delaysStephen Glancy2017-01-301-0/+67
* Add MSS customization support from CRP0 Lx MVPDJoe McGill2017-01-041-51/+2
* Add Memory Subsystem FIR supportBrian Silver2016-12-081-0/+20
* Add EC feature levels to MSS workaroundsBrian Silver2016-11-111-8/+26
* Add DP16 workarounds for Nimbus DD1.0Brian Silver2016-11-081-1/+118
* Added WR VREF latch commandStephen Glancy2016-11-041-2/+77
* Added WR VREF workaround for error logicStephen Glancy2016-10-071-1/+14
* Changes related to PHY register review, Round 3Louis Stermole2016-09-201-0/+9
* Add SEQ timing parameters, DP16 RD Diag config 5 initsBrian Silver2016-09-141-0/+9
* Change SEQ timings, SEQ ODT, WC config and DQS polarityBrian Silver2016-09-121-0/+44
* Add empty files for PHY SEQ, workarounds for mirroringBrian Silver2016-09-061-0/+24
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