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path: root/src/import/chips/p9/procedures/hwp/memory/lib/phy/write_cntrl.H
Commit message (Expand)AuthorAgeFilesLines
* Moves conversions to be in the generic code spaceStephen Glancy2018-08-201-2/+2
* Adds PDA supportStephen Glancy2017-11-211-0/+73
* Fix tWLDQSEN and IPW_WR_WR timing parameters for MSS trainingLouis Stermole2017-11-211-0/+6
* L3 support for ddr_phy_reset, termination_controlJacob Harvey2017-07-191-21/+21
* Added register reset functionality for DD2Stephen Glancy2017-06-071-15/+79
* Move scom API to share among controllersAndre Marin2017-03-181-1/+1
* Change accesses to IS_SIM to use mss accessorJacob Harvey2017-03-161-8/+8
* Fixed register values for RD VREFStephen Glancy2017-02-111-3/+3
* Added WR VREF latch commandStephen Glancy2016-11-041-4/+2
* Added WR VREF register API and reset proceduresStephen Glancy2016-09-261-1/+13
* Change WR_CNTR_FW valuesBrian Silver2016-09-251-1/+4
* Changes related to PHY register reviewBrian Silver2016-09-031-1/+1
* Update prologs of mirrored files to apache licenseStephen Cprek2016-08-051-8/+14
* Change PHY PC, RC and DP16 register blocks to functional APIBrian Silver2016-05-041-1/+22
* Change include paths in memory/lib, testsBrian Silver2016-04-211-1/+1
* Change PHY WC register block to functional APIBrian Silver2016-04-211-283/+316
* Change WC to follow the new register block patternBrian Silver2016-04-011-0/+440
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