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path: root/src/import/chips/p9/procedures/hwp/memory/lib/phy/phy_cntrl.C
Commit message (Expand)AuthorAgeFilesLines
* Updates MCA write and read timingsStephen Glancy2019-02-131-3/+3
* L3 work for mss xmlsJacob Harvey2017-08-181-12/+11
* L3 support for ddr_phy_reset, termination_controlJacob Harvey2017-07-191-4/+20
* Move index API to generic/memory folderAndre Marin2017-05-121-1/+1
* Move scom API to share among controllersAndre Marin2017-03-181-1/+1
* Add pos API to be shared among controllers, move generic files to utilsAndre Marin2017-03-151-1/+1
* Add c_str generic API and update makefilesAndre Marin2017-02-101-2/+2
* Add settings for DDR 2N modeBrian Silver2016-12-141-1/+4
* Update mss_decode_shadow_regs to use library MRS decodersLouis Stermole2016-11-041-0/+42
* Change DDR4 latency switch to always use MR0 A12Brian Silver2016-09-081-2/+3
* Change PHY to use GPO, RLO, WLO from VPDBrian Silver2016-09-081-0/+108
* Add phy_cntrl.C empty for mirroringBrian Silver2016-09-061-0/+24
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