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path: root/src/import/chips/p9/procedures/hwp/memory/lib/phy/mss_lrdimm_training.H
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* Fixed the ccs port merge conflicts and added lab codeMatthew Hickman2019-05-131-21/+18
* Updates CCS to run with quad encoded chip selectStephen Glancy2019-04-101-2/+1
* Fixes LRDIMM CKE issueStephen Glancy2019-03-131-0/+1
* Fixes MPR read ODT valuesStephen Glancy2019-03-131-0/+27
* Add new algorithm for MREP and error logshlimeng2019-02-221-95/+64
* Updates LRDIMM flags to be HB compatibleStephen Glancy2019-01-151-0/+4
* Adds MRD coarseStephen Glancy2018-12-141-4/+1
* Adds LRDIMM MWD fine training stepLi Meng2018-12-141-1/+0
* Adds LRDIMM MWD coarse training stepLi Meng2018-12-131-45/+0
* Adds LRDIMM MRD - DRAM to buffer RD calibrationStephen Glancy2018-12-051-45/+1
* Adds LRDIMM DWL training stepStephen Glancy2018-11-291-52/+12
* Updates LRDIMM code to utilize board swizzlingStephen Glancy2018-11-091-0/+105
* Adds MREP training for LRDIMMStephen Glancy2018-10-291-5/+342
* Fixes b-side bug in MPR write functionStephen Glancy2018-10-291-0/+126
* Adds code to run MPR writes on all ranks in a rank pairStephen Glancy2018-10-291-0/+23
* Updates training steps factory to be LRDIMM capableStephen Glancy2018-10-151-0/+9
* Adds skeleton code for LRDIMMStephen Glancy2018-09-181-0/+242
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