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path: root/src/import/chips/p9/procedures/hwp/memory/lib/phy/ddr_phy.C
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* Moves blame a FIR API to genericStephen Glancy2019-04-151-1/+1
* Fix c_str and pos DIMM specializationAndre A. Marin2019-04-021-2/+2
* Fixes LRDIMM eff_config bugsStephen Glancy2018-11-051-3/+3
* Updates rank API to work with LRDIMM'sStephen Glancy2018-10-161-25/+25
* Updates the training advanced algorithmStephen Glancy2018-06-211-7/+25
* Moves count_dimm to be in the memory generic folderStephen Glancy2018-04-051-2/+2
* Updates error logging to log target with FIRsStephen Glancy2018-01-251-1/+1
* Updates training advanced and adds custom WR CTRStephen Glancy2018-01-131-1/+44
* Change ZQ cal fail action to deconfigure MCBIST instead of MCALouis Stermole2017-12-221-1/+1
* Add Vreg==1 trigger to DLL workaroundLouis Stermole2017-11-271-8/+2
* Updates dramint training structureStephen Glancy2017-11-101-346/+38
* Fix sim problems on awanJacob Harvey2017-11-021-4/+8
* Move around recording bad bits to prevent reconfigJacob Harvey2017-10-111-5/+0
* Updates error paths for PRD FIR checkingStephen Glancy2017-10-021-1/+10
* Increment red_waterfall for low vdn fixJacob Harvey2017-09-261-6/+30
* Modify enum to get around compile issuesaravnair-in2017-09-081-1/+1
* Add FIR checking to training error checkingJacob Harvey2017-09-071-2/+12
* Fix rdvref, wrvref error handlingJacob Harvey2017-09-051-71/+62
* Add in ATTR_BAD_BIT_DQMAP functionsJacob Harvey2017-09-051-11/+4
* Implementing draminit_training_advJacob Harvey2017-08-291-17/+74
* Fix draminit_training error logging and unit testJacob Harvey2017-08-191-28/+128
* L3 work for mss xmlsJacob Harvey2017-08-181-4/+4
* Added ATTR_MSS_VPD_MT_WINDAGE_RD_CTR support after SYSCLK_RESET.Andre Marin2017-07-271-3/+0
* Remove reset_dll from scominit, enable delay line tap pointsAndre Marin2017-07-251-3/+0
* Fix logic bug for dll workaround in ddr_phy.CAndre Marin2017-07-201-1/+1
* L3 support for ddr_phy_reset, termination_controlJacob Harvey2017-07-191-21/+33
* Fix draminit_training wrapper and functionJacob Harvey2017-06-251-27/+51
* Fixed DLL workarounds to always runStephen Glancy2017-06-201-15/+2
* Fixes bug where WR VREF would never be runStephen Glancy2017-06-191-2/+3
* Add init of blue waterfall range to phy_scominitLouis Stermole2017-06-151-0/+3
* L3 RAS for draminit_training, eff_config, libJacob Harvey2017-06-111-26/+26
* Added register reset functionality for DD2Stephen Glancy2017-06-071-0/+49
* Turn off PHY refresh for RD_CNTR - RD_VREFJacob Harvey2017-06-071-10/+19
* Remove ZQCAL redundant CCS inst, move to draminit_trainingAndre Marin2017-05-251-54/+53
* Add DLL workaround and unit testsAndre Marin2017-05-121-16/+41
* Added DQS alignment workaroundStephen Glancy2017-05-121-10/+29
* Fixes RD VREF runtime calculationStephen Glancy2017-05-071-1/+2
* Added read ctr bad delay workaroundStephen Glancy2017-04-271-5/+35
* Fix up setup_cal and vref attrsJacob Harvey2017-04-171-23/+23
* L3 procedure work for p9_mss_draminit_trainingJacob Harvey2017-04-071-19/+29
* Move find API to share among memory controllersAndre Marin2017-03-221-1/+1
* Move scom API to share among controllersAndre Marin2017-03-181-1/+1
* Disable RTT_WR during WR_LEVEL cal step, and set equivalent terminationsLouis Stermole2017-03-151-19/+337
* Change accesses to IS_SIM to use mss accessorJacob Harvey2017-03-101-18/+18
* Updates to run HW VREF cal by defaultStephen Glancy2017-03-011-0/+3
* Add workaround for DDRPHY ODT config register erratum (ODT2, ODT3 bits swapped)Louis Stermole2017-02-211-0/+2
* Fix 1R dual-drop bugsLouis Stermole2017-02-101-42/+12
* Map from Centaur canonical rank numbering to NimbusBrian Silver2017-02-071-75/+105
* Add DP16 API and unit testing needed to set PBA mode for LRDIMMsAndre Marin2017-02-071-2/+2
* Fixed WR VREF settings bugStephen Glancy2017-01-041-41/+34
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