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path: root/src/import/chips/p9/procedures/hwp/memory/lib/dimm
Commit message (Expand)AuthorAgeFilesLines
* Updates error paths for PRD FIR checkingStephen Glancy2017-10-023-12/+10
* Add Write CRC attributes to xml and eff_dimmAndre Marin2017-09-252-0/+108
* Modify VPD decoder to take into account deconfigured portsAndre Marin2017-09-251-42/+56
* Updates RCD power settingsStephen Glancy2017-09-181-2/+69
* Skip ports without DIMMs for VPD collectionJacob Harvey2017-09-181-0/+5
* Fix order of sequence for register control words, and CKE levelsAndre Marin2017-09-053-18/+51
* Implementing draminit_training_advJacob Harvey2017-08-292-4/+89
* Adds DDR4 hybrid NV-RDIMM supportStephen Glancy2017-08-292-28/+1
* Fix draminit_training error logging and unit testJacob Harvey2017-08-191-2/+36
* L3 work for mss xmlsJacob Harvey2017-08-183-7/+8
* Change tREFI calc to be 99% of calculated result to stay within lab marginAndre Marin2017-08-071-4/+5
* L3 draminit and mss_libJacob Harvey2017-07-2628-278/+393
* L3 support for ddr_phy_reset, termination_controlJacob Harvey2017-07-246-7/+7
* L3 support for ddr_phy_reset, termination_controlJacob Harvey2017-07-1913-33/+21
* Add in RCD attributes for DD2 debugJacob Harvey2017-07-112-5/+123
* Turn off A17 if not neededJacob Harvey2017-06-253-8/+117
* Fixes DD2 training bugStephen Glancy2017-06-231-28/+36
* Fix CSID: 2 slave ranks, termination in RCBCXJacob Harvey2017-06-222-37/+131
* Fixes RCW timing in draminitStephen Glancy2017-06-201-5/+7
* Modify DRAM_LPASR to be set based on MRW REFRESH_RATE_REQUEST attrAndre Marin2017-06-151-3/+22
* Fix tREFI calculation to use MRW REFRESH REQUEST RATE as opposed to TEMP RANGEAndre Marin2017-06-142-5/+17
* Double POR timings (tMOD, tMRD, and tZQ) for more margin per labAndre Marin2017-06-142-9/+17
* L3 RAS for draminit_training, eff_config, libJacob Harvey2017-06-112-38/+27
* Fixed CSID value for DD2Stephen Glancy2017-06-071-1/+5
* Remove ZQCAL redundant CCS inst, move to draminit_trainingAndre Marin2017-05-255-63/+213
* Add PHY sequencer refresh settings after draminitAndre Marin2017-05-122-14/+34
* Added read ctr bad delay workaroundStephen Glancy2017-04-271-0/+1
* Fix up setup_cal and vref attrsJacob Harvey2017-04-172-5/+5
* L3 procedure work for p9_mss_draminit_trainingJacob Harvey2017-04-072-64/+184
* Add empty zqcal files for HB to mirrorAndre Marin2017-04-062-0/+48
* Add base spd decoder to share among controllersAndre Marin2017-03-272-15/+18
* Fixing tfaw and trrd calculationsJacob Harvey2017-03-231-67/+176
* Move find API to share among memory controllersAndre Marin2017-03-221-1/+1
* Move scom API to share among controllersAndre Marin2017-03-181-1/+1
* Fix add rtt_wr eff_dimm unit tests and header file fixAndre Marin2017-03-161-9/+12
* Update mss_eff_config to L3Jacob Harvey2017-03-161-41/+133
* Disable RTT_WR during WR_LEVEL cal step, and set equivalent terminationsLouis Stermole2017-03-152-2/+392
* Add pos API to be shared among controllers, move generic files to utilsAndre Marin2017-03-1512-12/+12
* Deconfigure MCA if there is a VPD load errorLouis Stermole2017-03-081-21/+39
* Clean up RC0E in mss::eff_dimmJacob Harvey2017-03-031-14/+35
* Add c_str generic API and update makefilesAndre Marin2017-03-032-2/+2
* Add DP16 API and unit testing needed to set PBA mode for LRDIMMsAndre Marin2017-03-031-56/+67
* Add BCW API for rank presence, buffer training, mrep timing and UTs.Andre Marin2017-03-031-0/+449
* Add common functionality between RCD and data buffer control word APIAndre Marin2017-03-031-0/+347
* Another dummy commit to fix a mirror problemDan Crowell2017-03-032-811/+0
* Disable PPR and sPPR mode in draminit to comply w/JEDEC PORAndre Marin2017-03-013-12/+16
* Updates to run HW VREF cal by defaultStephen Glancy2017-03-012-0/+59
* Simplify spd factory mapping to share among controllersAndre Marin2017-03-012-121/+70
* Add attribute ATTR_EFF_RANK_GROUP_OVERRIDELouis Stermole2017-02-271-14/+63
* Adding in default raw card informationJacob Harvey2017-02-271-3/+4
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