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path: root/src/import/chips/p9/procedures/hwp/memory/lib/dimm/eff_dimm.H
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* Move pre_eff_config specific code to chip specific foldersAndre Marin2019-07-291-1/+1
* Updates RCW's attributes for quad encoded CS modeStephen Glancy2019-04-161-0/+14
* Adds SI setting for 4R and dual-drop LRDIMM configsStephen Glancy2019-03-011-4/+44
* Updates MCA write and read timingsStephen Glancy2019-02-131-0/+39
* Updates MWD_COARSE to run multiple patternsStephen Glancy2019-02-051-1/+22
* Fixes LRDIMM eff_config bugsStephen Glancy2018-11-051-1/+211
* Remove Nimbus dependencies from the SPD decoderAndre Marin2018-07-311-35/+108
* Updates the training advanced algorithmStephen Glancy2018-06-211-0/+7
* Updates training advanced and adds custom WR CTRStephen Glancy2018-01-131-0/+7
* Updates WR VREF for characterization resultsStephen Glancy2018-01-131-9/+16
* Add Write CRC attributes to xml and eff_dimmAndre Marin2017-09-251-0/+18
* Implementing draminit_training_advJacob Harvey2017-08-291-0/+14
* Adds DDR4 hybrid NV-RDIMM supportStephen Glancy2017-08-291-6/+0
* L3 work for mss xmlsJacob Harvey2017-08-181-4/+5
* Add in RCD attributes for DD2 debugJacob Harvey2017-07-111-1/+18
* Fix CSID: 2 slave ranks, termination in RCBCXJacob Harvey2017-06-221-0/+20
* Fix tREFI calculation to use MRW REFRESH REQUEST RATE as opposed to TEMP RANGEAndre Marin2017-06-141-2/+2
* Add PHY sequencer refresh settings after draminitAndre Marin2017-05-121-0/+6
* Fix up setup_cal and vref attrsJacob Harvey2017-04-171-2/+2
* Add base spd decoder to share among controllersAndre Marin2017-03-271-1/+1
* Updates to run HW VREF cal by defaultStephen Glancy2017-03-011-0/+12
* Simplify spd factory mapping to share among controllersAndre Marin2017-03-011-37/+31
* Fixing raw card setting for DIMMsJacob Harvey2017-02-211-12/+18
* Disabling temp_refresh_modeJacob Harvey2017-02-101-6/+0
* Implement BC attributes and make eff_dimm classJacob Harvey2017-01-251-1/+1237
* Add in empty eff_dimm files for mirroring purposesJacob Harvey2017-01-131-0/+24
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