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path: root/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs_load_ddr4.H
Commit message (Expand)AuthorAgeFilesLines
* Updates CCS to run with quad encoded chip selectStephen Glancy2019-04-101-3/+3
* HB Improvements: Fix compiler warnings on modern compilersLuis Fernandez2019-03-261-5/+6
* Adds LRDIMM DWL training stepStephen Glancy2018-11-291-0/+68
* Fixes HB compile errorStephen Glancy2018-01-181-14/+35
* Updates WR VREF for characterization resultsStephen Glancy2018-01-131-1/+92
* Adds PDA supportStephen Glancy2017-11-211-0/+357
* L3 draminit and mss_libJacob Harvey2017-07-261-26/+61
* L3 support for ddr_phy_reset, termination_controlJacob Harvey2017-07-191-1/+1
* Turn off A17 if not neededJacob Harvey2017-06-251-4/+29
* Disable RTT_WR during WR_LEVEL cal step, and set equivalent terminationsLouis Stermole2017-03-151-1/+217
* Add pos API to be shared among controllers, move generic files to utilsAndre Marin2017-03-151-1/+1
* Disable PPR and sPPR mode in draminit to comply w/JEDEC PORAndre Marin2017-03-011-0/+2
* Add c_str generic API and update makefilesAndre Marin2017-02-101-2/+2
* Add read cmd, precharge all cmd, and read cmd CCS instruction and unit testsAndre Marin2017-01-031-48/+180
* Add a common MRS engine to set up CCS instructions and UTs.Andre Marin2016-12-061-93/+363
* Update mss_decode_shadow_regs to use library MRS decodersLouis Stermole2016-11-041-14/+173
* Change DRAM output impedance value to be from MSS_VPD_MT_DRAM_DRV_IMP_DQ_DQSLouis Stermole2016-08-251-1/+1
* Add mrs_one_shot to the MSS Lab codeBrian Silver2016-08-121-152/+249
* Create MRS data structuresBrian Silver2016-08-071-0/+579
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