diff options
Diffstat (limited to 'src')
29 files changed, 4437 insertions, 2672 deletions
diff --git a/src/usr/hwpf/hwp/bus_training/edi_regs.h b/src/usr/hwpf/hwp/bus_training/edi_regs.h index 7dfdf3206..64ad59973 100644 --- a/src/usr/hwpf/hwp/bus_training/edi_regs.h +++ b/src/usr/hwpf/hwp/bus_training/edi_regs.h @@ -1,26 +1,25 @@ -/* IBM_PROLOG_BEGIN_TAG - * This is an automatically generated prolog. - * - * $Source: src/usr/hwpf/hwp/bus_training/edi_regs.h $ - * - * IBM CONFIDENTIAL - * - * COPYRIGHT International Business Machines Corp. 2012 - * - * p1 - * - * Object Code Only (OCO) source materials - * Licensed Internal Code Source Materials - * IBM HostBoot Licensed Internal Code - * - * The source code for this program is not published or other- - * wise divested of its trade secrets, irrespective of what has - * been deposited with the U.S. Copyright Office. - * - * Origin: 30 - * - * IBM_PROLOG_END_TAG - */ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/usr/hwpf/hwp/bus_training/edi_regs.h $ */ +/* */ +/* IBM CONFIDENTIAL */ +/* */ +/* COPYRIGHT International Business Machines Corp. 2012,2014 */ +/* */ +/* p1 */ +/* */ +/* Object Code Only (OCO) source materials */ +/* Licensed Internal Code Source Materials */ +/* IBM HostBoot Licensed Internal Code */ +/* */ +/* The source code for this program is not published or otherwise */ +/* divested of its trade secrets, irrespective of what has been */ +/* deposited with the U.S. Copyright Office. */ +/* */ +/* Origin: 30 */ +/* */ +/* IBM_PROLOG_END_TAG */ //----------------------------------------------------- // ____ ____ _ ______ ______ // / __ \/ __ \ / | / / __ \/_ __/ @@ -42,7 +41,7 @@ //----------------------------------------------------- // Constant file for edi_reg_attribute.txt_fixed // File generated at 16:23 on 8/31/2011 using system_pervasive/common/tools/CreateConstantsH.pl -// $Id: edi_regs.h,v 1.9 2012/07/28 04:03:12 jmcgill Exp $ +// $Id: edi_regs.h,v 1.10 2014/02/20 13:27:29 varkeykv Exp $ // $URL: $ // // *!************************************************************************** @@ -474,14 +473,14 @@ tx_mode_pl, ei4_rx_fir_mask_pb, ei4_rx_fir_error_inject_pb, ei4_rx_fir_msg_pb, + ei4_rx_dcd_adj_pl, NUM_REGS } GCR_sub_registers; // merged ei4 and edi ext addresses const uint32_t GCR_sub_reg_ext_addr[] = { 0x080, 0x081, 0x082, 0x085, 0x086, 0x087, 0x088, 0x08A, 0x08B, 0x08C, 0x08D, 0x08E, 0x08F, 0x180, 0x181, 0x182, 0x183, 0x184, 0x185, 0x186, 0x188, 0x189, 0x18A, 0x18B, 0x18C, 0x192, 0x193, 0x194, 0x198, 0x199, 0x19A, 0x19B, 0x19C, 0x19D, 0x19F, 0x1A0, 0x1A3, 0x1A4, 0x1A5, 0x1A6, 0x1A7, 0x1D0, 0x1D1, 0x1D2, 0x1D3, 0x1D4, 0x1D5, 0x1D6, 0x1D7, 0x1D8, 0x1D9, 0x1DA, 0x1DB, 0x1DC, 0x1E0, 0x1E1, 0x1E2, 0x1E3, 0x1E4, 0x1E5, 0x1E6, 0x1E7, 0x1E8, 0x1E9, 0x000, 0x001, 0x002, 0x003, 0x005, 0x008, 0x009, 0x00A, 0x00B, 0x00C, 0x00D, 0x00E, 0x00F, 0x010, 0x011, 0x012, 0x013, 0x014, 0x016, 0x018, 0x019, 0x01A, 0x01B, 0x01C, 0x01D, 0x01E, 0x01F, 0x020, 0x021, 0x022, 0x023, 0x024, 0x025, 0x026, 0x027, 0x028, 0x029, 0x02A, 0x02B, 0x02C, 0x02D, 0x100, 0x101, 0x102, 0x103, 0x104, 0x105, 0x106, 0x107, 0x108, 0x109, 0x10A, 0x10B, 0x10C, 0x10D, 0x10F, 0x110, 0x111, 0x112, 0x113, 0x114, 0x117, 0x11A, 0x11B, 0x11C, 0x11D, 0x11E, 0x11F, 0x120, 0x121, 0x122, 0x123, 0x124, 0x125, 0x126, 0x127, 0x128, 0x129, 0x12A, 0x12B, 0x12C, 0x12D, 0x12E, 0x12F, 0x130, 0x131, 0x132, 0x133, 0x134, 0x135, 0x137, 0x138, 0x139, 0x13A, 0x13B, 0x13C, 0x13D, 0x13E, 0x13F, 0x140, 0x141, 0x142, 0x143, 0x145, 0x146, 0x147, 0x148, 0x149, 0x14A, 0x14B, 0x14C, 0x14D, 0x14E, 0x14F, 0x150, 0x151, 0x152, 0x153, 0x154, 0x155, 0x157, 0x158, 0x159, 0x15A, 0x15B, 0x15C, 0x15D, 0x15E, 0x15F, 0x160, 0x161, 0x162, 0x168, 0x169, 0x16A, 0x16B, 0x16C, 0x16D, 0x16E, 0x16F, 0x170, 0x171, 0x172, 0x173, 0x174, 0x175, 0x176, 0x177, 0x178, 0x1F0, 0x1F1, 0x1F2, 0x1F3, 0x1FF, - 0x080, 0x081, 0x082, 0x085, 0x086, 0x087, 0x088, 0x08A, 0x08B, 0x08C, 0x08D, 0x180, 0x181, 0x182, 0x183, 0x184, 0x185, 0x186, 0x188, 0x189, 0x18A, 0x18B, 0x18C, 0x192, 0x193, 0x194, 0x198, 0x19D, 0x19F, 0x1A0, 0x1A1, 0x1A2, 0x1A3, 0x1A4, 0x1A5, 0x1A6, 0x1A7, 0x1A8, 0x1C7, 0x1C8, 0x1C9, 0x1CA, 0x1CB, 0x1CC, 0x1CD, 0x1CE, 0x1CF, 0x1D0, 0x1D1, 0x1D2, 0x1D3, 0x1D4, 0x1D6, 0x1D7, 0x1D8, 0x1D9, 0x1DB, 0x1DC, 0x000, 0x001, 0x002, 0x005, 0x008, 0x009, 0x00A, 0x00C, 0x00D, 0x00E, 0x00F, 0x016, 0x017, 0x018, 0x019, 0x01A, 0x01B, 0x01C, 0x01D, 0x01E, 0x01F, 0x020, 0x021, 0x022, 0x023, 0x024, 0x025, 0x026, 0x027, 0x028, 0x029, 0x02B, 0x02C, 0x02D, 0x100, 0x101, 0x102, 0x103, 0x104, 0x105, 0x106, 0x107, 0x108, 0x109, 0x10A, 0x10B, 0x10C, 0x10F, 0x110, 0x111, 0x112, 0x113, 0x114, 0x117, 0x11A, 0x11B, 0x11C, 0x11D, 0x11E, 0x11F, 0x120, 0x121, 0x122, 0x123, 0x124, 0x125, 0x126, 0x127, 0x128, 0x129, 0x12A, 0x12B, 0x12C, 0x12D, 0x12E, 0x12F, 0x130, 0x131, 0x132, 0x133, 0x134, 0x135, 0x136, 0x137, 0x139, 0x13A, 0x13B, 0x13C, 0x13D, 0x13E, 0x13F, 0x140, 0x142, 0x146, 0x147, 0x148, 0x149, 0x14E, 0x151, 0x152, 0x153, 0x154, 0x155, 0x156, 0x157, 0x158, 0x159, 0x15A, 0x15B, 0x15C, 0x15D, 0x15F, 0x160, 0x161, 0x162, 0x163, 0x164, 0x165, 0x166, 0x167, 0x169, 0x16A, 0x16B, 0x16C, 0x16D, 0x171, 0x172, 0x173, 0x175, 0x176, 0x177, 0x1F0, 0x1F1, 0x1F2, 0x1F3, 0x1FF -}; + 0x080, 0x081, 0x082, 0x085, 0x086, 0x087, 0x088, 0x08A, 0x08B, 0x08C, 0x08D, 0x180, 0x181, 0x182, 0x183, 0x184, 0x185, 0x186, 0x188, 0x189, 0x18A, 0x18B, 0x18C, 0x192, 0x193, 0x194, 0x198, 0x19D, 0x19F, 0x1A0, 0x1A1, 0x1A2, 0x1A3, 0x1A4, 0x1A5, 0x1A6, 0x1A7, 0x1A8, 0x1C7, 0x1C8, 0x1C9, 0x1CA, 0x1CB, 0x1CC, 0x1CD, 0x1CE, 0x1CF, 0x1D0, 0x1D1, 0x1D2, 0x1D3, 0x1D4, 0x1D6, 0x1D7, 0x1D8, 0x1D9, 0x1DB, 0x1DC, 0x000, 0x001, 0x002, 0x005, 0x008, 0x009, 0x00A, 0x00C, 0x00D, 0x00E, 0x00F, 0x016, 0x017, 0x018, 0x019, 0x01A, 0x01B, 0x01C, 0x01D, 0x01E, 0x01F, 0x020, 0x021, 0x022, 0x023, 0x024, 0x025, 0x026, 0x027, 0x028, 0x029, 0x02B, 0x02C, 0x02D, 0x100, 0x101, 0x102, 0x103, 0x104, 0x105, 0x106, 0x107, 0x108, 0x109, 0x10A, 0x10B, 0x10C, 0x10F, 0x110, 0x111, 0x112, 0x113, 0x114, 0x117, 0x11A, 0x11B, 0x11C, 0x11D, 0x11E, 0x11F, 0x120, 0x121, 0x122, 0x123, 0x124, 0x125, 0x126, 0x127, 0x128, 0x129, 0x12A, 0x12B, 0x12C, 0x12D, 0x12E, 0x12F, 0x130, 0x131, 0x132, 0x133, 0x134, 0x135, 0x136, 0x137, 0x139, 0x13A, 0x13B, 0x13C, 0x13D, 0x13E, 0x13F, 0x140, 0x142, 0x146, 0x147, 0x148, 0x149, 0x14E, 0x151, 0x152, 0x153, 0x154, 0x155, 0x156, 0x157, 0x158, 0x159, 0x15A, 0x15B, 0x15C, 0x15D, 0x15F, 0x160, 0x161, 0x162, 0x163, 0x164, 0x165, 0x166, 0x167, 0x169, 0x16A, 0x16B, 0x16C, 0x16D, 0x171, 0x172, 0x173, 0x175, 0x176, 0x177, 0x1F0, 0x1F1, 0x1F2, 0x1F3, 0x1FF,0x02E}; //merged ei4 and edi const char* const GCR_sub_reg_names[] = { "TX Lane Mode Reg", @@ -895,7 +894,8 @@ const char* const GCR_sub_reg_names[] = { "Per-Bus FIR Error Source-Isolation Reg", "Per-Bus FIR Error Source-Isolation Mask Reg", "Per-Bus FIR Error Injection Reg", - "Per-Bus FIR Register Write Alias" + "Per-Bus FIR Register Write Alias", + "RX Clock Duty Cycle Adjust register" }; // tx_mode_pl Register field name data value Description diff --git a/src/usr/hwpf/hwp/bus_training/gcr_funcs.C b/src/usr/hwpf/hwp/bus_training/gcr_funcs.C index 95e563a41..e02218179 100644 --- a/src/usr/hwpf/hwp/bus_training/gcr_funcs.C +++ b/src/usr/hwpf/hwp/bus_training/gcr_funcs.C @@ -20,7 +20,7 @@ /* Origin: 30 */ /* */ /* IBM_PROLOG_END_TAG */ -// $Id: gcr_funcs.C,v 1.10 2014/02/06 10:27:48 jaswamin Exp $ +// $Id: gcr_funcs.C,v 1.12 2014/03/10 16:29:43 varkeykv Exp $ // *!*************************************************************************** // *! (C) Copyright International Business Machines Corp. 1997, 1998 // *! All Rights Reserved -- Property of IBM @@ -35,58 +35,63 @@ // *! BACKUP NAME : Swaminathan, Janani Email: jaswamin@in.ibm.com // *! // *!*************************************************************************** -// CHANGE HISTORY: +// CHANGE HISTORY: //------------------------------------------------------------------------------ // Version:|Author: | Date: | Comment: // --------|--------|--------|-------------------------------------------------- // 1.0 |varkeykv|01/19/12| Initial check in to solve hostboot linker //------------------------------------------------------------------------------ -#include "gcr_funcs.H" +#include <gcr_funcs.H> + using namespace fapi; ReturnCode GCR_read(const Target& chip_target, io_interface_t interface,GCR_sub_registers target_io_reg, uint32_t group_address, uint32_t lane_address, ecmdDataBufferBase &databuf_16bit) { - ReturnCode rc; - uint32_t rc_ecmd=0; - ecmdDataBufferBase set_bits(16), clear_bits(16); - rc_ecmd|=set_bits.flushTo0(); - rc_ecmd|=clear_bits.flushTo1(); + ReturnCode rc; + uint32_t rc_ecmd=0; + ecmdDataBufferBase set_bits(16), clear_bits(16); + rc_ecmd|=set_bits.flushTo0(); + rc_ecmd|=clear_bits.flushTo1(); - if(rc_ecmd){ + if(rc_ecmd) + { FAPI_ERR("Unexpected error in buffer manipulation\n"); rc.setEcmdError(rc_ecmd); - } - else{ - rc=doGCRop(chip_target, interface, gcr_op_read, target_io_reg, group_address, lane_address, set_bits, clear_bits, databuf_16bit); + } + else + { + rc=doGCRop(chip_target, interface, gcr_op_read, target_io_reg, group_address, lane_address, set_bits, clear_bits, databuf_16bit); if(!rc.ok()) { FAPI_ERR("Unexpected error while performing GCR OP \n"); } - } + } - return rc; + return rc; } //------------------------------------------------------------------------------------------------------------------------------------ // GCR SCOM WRITE - main api for write - do not use doGCRop directly //------------------------------------------------------------------------------------------------------------------------------------ ReturnCode GCR_write(const Target& chip_target, io_interface_t interface, GCR_sub_registers target_io_reg, uint32_t group_address, uint32_t lane_address, ecmdDataBufferBase set_bits, ecmdDataBufferBase clear_bits, int skipCheck,int bypass_rmw) { - ReturnCode rc; - uint32_t rc_ecmd=0; - ecmdDataBufferBase databuf_16bit(16); - rc_ecmd|=databuf_16bit.flushTo0(); - skipCheck=1; //forcing this argument to one as this is redundant. - if(rc_ecmd){ + ReturnCode rc; + uint32_t rc_ecmd=0; + ecmdDataBufferBase databuf_16bit(16); + rc_ecmd|=databuf_16bit.flushTo0(); + skipCheck=1; // This is redundant -- forcing to 1 + if(rc_ecmd) + { FAPI_ERR("Unexpected error in buffer manipulation\n"); rc.setEcmdError(rc_ecmd); - } - else{ - rc=doGCRop(chip_target, interface, gcr_op_write, target_io_reg, group_address, lane_address, set_bits, clear_bits, databuf_16bit, skipCheck,bypass_rmw); + } + else + { + rc=doGCRop(chip_target, interface, gcr_op_write, target_io_reg, group_address, lane_address, set_bits, clear_bits, databuf_16bit, skipCheck,bypass_rmw); if(!rc.ok()) { FAPI_ERR("Unexpected error while performing GCR OP \n"); } - } - return rc; + } + return rc; } // UPPER LAYER FUNCTIONS @@ -94,22 +99,23 @@ ReturnCode GCR_write(const Target& chip_target, io_interface_t interface, GCR_s //------------------------------------------------------------------------------------------------------------------------------------ // generate the 64 bit scom address for the GCR //------------------------------------------------------------------------------------------------------------------------------------ -uint64_t scom_address_64bit(uint32_t gcr_addr, uint64_t gcr_data) { - uint32_t rc_ecmd=0; - ecmdDataBufferBase reg_scom_address(64), temp(64); - temp.flushTo0(); - temp.setDoubleWord(0,gcr_data); +uint64_t scom_address_64bit(uint32_t gcr_addr, uint64_t gcr_data) +{ + uint32_t rc_ecmd=0; + ecmdDataBufferBase reg_scom_address(64), temp(64); + temp.flushTo0(); + temp.setDoubleWord(0,gcr_data); - // 64 bit address - rc_ecmd|= reg_scom_address.setWord(0,temp.getWord(0)); - rc_ecmd |= reg_scom_address.setWord(1,gcr_addr); - rc_ecmd |= reg_scom_address.setBit(0); + // 64 bit address + rc_ecmd|= reg_scom_address.setWord(0,temp.getWord(0)); + rc_ecmd |= reg_scom_address.setWord(1,gcr_addr); + rc_ecmd |= reg_scom_address.setBit(0); - if(rc_ecmd) - { - FAPI_ERR("io_run_training: Unexpected failure in scom_address_64bit helper func"); - } - return(reg_scom_address.getDoubleWord(0)); + if(rc_ecmd) + { + FAPI_ERR("io_run_training: Unexpected failure in scom_address_64bit helper func"); + } + return(reg_scom_address.getDoubleWord(0)); } @@ -126,140 +132,147 @@ uint64_t scom_address_64bit(uint32_t gcr_addr, uint64_t gcr_data) { /* gcr2 readvalid 39 1 # read data valid bit */ /*************************************************************************************************************************/ -ReturnCode doGCRop(const Target& chip_target, io_interface_t interface, gcr_op read_or_write, GCR_sub_registers target_io_reg, uint32_t group_address, uint32_t lane_address, ecmdDataBufferBase set_bits, ecmdDataBufferBase clear_bits, ecmdDataBufferBase &databuf_16bit, int skipCheck,int bypass_rmw) { +ReturnCode doGCRop(const Target& chip_target, + io_interface_t interface, + gcr_op read_or_write, + GCR_sub_registers target_io_reg, + uint32_t group_address, + uint32_t lane_address, + ecmdDataBufferBase set_bits, + ecmdDataBufferBase clear_bits, + ecmdDataBufferBase &databuf_16bit, + int skipCheck, + int bypass_rmw) +{ ReturnCode rc; uint32_t rc_ecmd=0; uint64_t scom_address64=0; ecmdDataBufferBase getscom_data64(64), putscom_data64(64), local_data16(16); - rc_ecmd |=getscom_data64.flushTo0(); - rc_ecmd |=putscom_data64.flushTo0(); - rc_ecmd |=local_data16.flushTo0(); + + do + { + rc_ecmd |=getscom_data64.flushTo0(); + rc_ecmd |=putscom_data64.flushTo0(); + rc_ecmd |=local_data16.flushTo0(); - // Generate the gcr2_register_data putscom data - /* gcr2 reg_addr 12 9 # gcr ring (register) address (ext_addr) */ - // align the extended address to bit (12:20) - rc_ecmd |= getscom_data64.insert( GCR_sub_reg_ext_addr[target_io_reg], 12, 9, 23 ); - FAPI_DBG("Register Extended address = %x\n",GCR_sub_reg_ext_addr[target_io_reg]); + // Generate the gcr2_register_data putscom data + /* gcr2 reg_addr 12 9 # gcr ring (register) address (ext_addr) */ + // align the extended address to bit (12:20) + rc_ecmd |= getscom_data64.insert( GCR_sub_reg_ext_addr[target_io_reg], 12, 9, 23 ); + FAPI_DBG("Register Extended address = %x\n",GCR_sub_reg_ext_addr[target_io_reg]); - const char *temp; - temp=GCR_sub_reg_names[target_io_reg]; - if(temp[0] == 'T' ) - { - // This is a TX register/field need to set the TX bit - rc_ecmd |= getscom_data64.setBit( 21 ); // does not include leading TX bit now since we are using only RX - } - /* gcr2 group 22 5 # does NOT include tx/rx as leading bit */ - // align the group address to bit (22:26) - rc_ecmd |= getscom_data64.insert( group_address, 22, 5, 27); // does not include leading TX bit now since we are using only RX + const char *temp; + temp=GCR_sub_reg_names[target_io_reg]; + if(temp[0] == 'T' ) + { + // This is a TX register/field need to set the TX bit + rc_ecmd |= getscom_data64.setBit( 21 ); // does not include leading TX bit now since we are using only RX + } + /* gcr2 group 22 5 # does NOT include tx/rx as leading bit */ + // align the group address to bit (22:26) + rc_ecmd |= getscom_data64.insert( group_address, 22, 5, 27); // does not include leading TX bit now since we are using only RX - /* gcr2 lane 27 5 # lane address */ - // align the lane address to bit (27:31) - rc_ecmd |= getscom_data64.insert( lane_address, 27, 5, 27 ); - if(rc_ecmd) - { - FAPI_ERR("IO gcr_funcs: DataBuffer operation error occurred\n"); - rc.setEcmdError(rc_ecmd); - } - else - { + /* gcr2 lane 27 5 # lane address */ + // align the lane address to bit (27:31) + rc_ecmd |= getscom_data64.insert( lane_address, 27, 5, 27 ); + if(rc_ecmd) + { + FAPI_ERR("IO gcr_funcs: DataBuffer operation error occurred\n"); + rc.setEcmdError(rc_ecmd); + break; + } + FAPI_DBG("ei_reg_addr_GCR_scom[interface]=%x\n",ei_reg_addr_GCR_scom[interface]); scom_address64 =scom_address_64bit(ei_reg_addr_GCR_scom[interface], getscom_data64.getDoubleWord(0)); - if(!bypass_rmw){ + if(!bypass_rmw) + { rc = fapiGetScom( chip_target, scom_address64, getscom_data64 ); } - else{ - getscom_data64.flushTo0(); + else + { + getscom_data64.flushTo0(); } + if(!rc.ok()) { FAPI_ERR("IO gcr_funcs:GETSCOM error occurred ********\n"); - FAPI_ERR( "IO GCR FUNCS \tRead GCR %s, @ = %llX, Data = %08X%08X Failed group_address=%d\n", - GCR_sub_reg_names[target_io_reg], scom_address64, getscom_data64.getWord(0), getscom_data64.getWord(1),group_address); - + FAPI_ERR( "IO GCR FUNCS \tRead GCR %s, @ = %llX, Data = %08X%08X Failed group_address=%d\n", + GCR_sub_reg_names[target_io_reg], scom_address64, getscom_data64.getWord(0), getscom_data64.getWord(1),group_address); + break; } - else - { - FAPI_DBG( "\tRead GCR2 %s: GETSCOM 0x%llX %08X%08X \n", - GCR_sub_reg_names[target_io_reg], scom_address64, getscom_data64.getWord(0), getscom_data64.getWord(1) ); - rc_ecmd|=getscom_data64.extract( local_data16, 48, 16 ); // return data on read ops -- for 54/52 onwards + FAPI_DBG( "\tRead GCR2 %s: GETSCOM 0x%llX %08X%08X \n", + GCR_sub_reg_names[target_io_reg], scom_address64, getscom_data64.getWord(0), getscom_data64.getWord(1) ); + rc_ecmd|=getscom_data64.extract( local_data16, 48, 16 ); // return data on read ops -- for 54/52 onwards - if(rc_ecmd) - { - FAPI_ERR("IO gcr_funcs: DataBuffer operation error occurred\n"); - rc.setEcmdError(rc_ecmd); - } - else - { - // register write operation - if (read_or_write == gcr_op_read) { - databuf_16bit = local_data16; - } - else - { // write - // write operation - putscom_data64 = getscom_data64; - - // clear the desired bits first - databuf_16bit = databuf_16bit & clear_bits; + if(rc_ecmd) + { + FAPI_ERR("IO gcr_funcs: DataBuffer operation error occurred\n"); + rc.setEcmdError(rc_ecmd); + break; + } + // register write operation + if (read_or_write == gcr_op_read) + { + databuf_16bit = local_data16; + break; + } + // write operation + putscom_data64 = getscom_data64; + + // clear the desired bits first + databuf_16bit = databuf_16bit & clear_bits; - // now set desired bits - databuf_16bit = databuf_16bit | set_bits; - - // data is now 64 bits and only last 16 bits are used 48:63 = 16bits # data - rc_ecmd|=putscom_data64.insert( databuf_16bit, 48, 16); //-- for model 54/52 onwards - - if(rc_ecmd) - { - FAPI_ERR("IO gcr_funcs: DataBuffer operation error occurred"); - rc.setEcmdError(rc_ecmd); - } - else - { - FAPI_DBG( "\tWrite GCR2 %s: PUTSCOM 0x%llX 0x%08X%08X", - GCR_sub_reg_names[target_io_reg], scom_address64, putscom_data64.getWord(0), putscom_data64.getWord(1) ); - rc = fapiPutScom( chip_target, scom_address64, putscom_data64); - if(!rc.ok()) - { - FAPI_ERR("IO gcr_funcs: PUTSCOM error occurred\n"); - } - else - { - // check the write - if(!skipCheck){ - rc = fapiGetScom( chip_target, scom_address64, getscom_data64 ); - } - if(!rc.ok()){ - FAPI_ERR("IO gcr_funcs: GETSCOM error occurred\n"); - return(rc); - } - rc_ecmd=local_data16.insert(getscom_data64,0,16,48); //-- for 54/52 onwards - if(rc_ecmd) - { - FAPI_ERR("IO gcr_funcs: DataBuffer operation error occurred\n"); - rc.setEcmdError(rc_ecmd); - } - else{ - if ( !skipCheck ) - { //add skipCheck for tx_err_inj since self resetting -- djd 2/11/11 - if ( local_data16 != databuf_16bit ) - { - FAPI_ERR( "\t %s VALIDATE write failed: read=0x%04X write=%04X\n", - GCR_sub_reg_names[target_io_reg], local_data16.getHalfWord(0), databuf_16bit.getHalfWord(0) ); - ecmdDataBufferBase &READ_BUF=local_data16; - ecmdDataBufferBase &WRITE_BUF=databuf_16bit; - FAPI_SET_HWP_ERROR(rc, IO_GCR_WRITE_MISMATCH_RC); - } - } + // now set desired bits + databuf_16bit = databuf_16bit | set_bits; + + // data is now 64 bits and only last 16 bits are used 48:63 = 16bits # data + rc_ecmd|=putscom_data64.insert( databuf_16bit, 48, 16); //-- for model 54/52 onwards + + if(rc_ecmd) + { + FAPI_ERR("IO gcr_funcs: DataBuffer operation error occurred"); + rc.setEcmdError(rc_ecmd); + break; + } + FAPI_DBG( "\tWrite GCR2 %s: PUTSCOM 0x%llX 0x%08X%08X", + GCR_sub_reg_names[target_io_reg], scom_address64, putscom_data64.getWord(0), putscom_data64.getWord(1) ); + rc = fapiPutScom( chip_target, scom_address64, putscom_data64); + if(!rc.ok()) + { + FAPI_ERR("IO gcr_funcs: PUTSCOM error occurred\n"); + break; + } + // check the write + if(!skipCheck) + { + rc = fapiGetScom( chip_target, scom_address64, getscom_data64 ); + } + if(!rc.ok()) + { + FAPI_ERR("IO gcr_funcs: GETSCOM error occurred\n"); + break; + } + rc_ecmd=local_data16.insert(getscom_data64,0,16,48); //-- for 54/52 onwards + if(rc_ecmd) + { + FAPI_ERR("IO gcr_funcs: DataBuffer operation error occurred\n"); + rc.setEcmdError(rc_ecmd); + break; + } + if ( !skipCheck ) + { + //add skipCheck for tx_err_inj since self resetting -- djd 2/11/11 + if ( local_data16 != databuf_16bit ) + { + FAPI_ERR( "\t %s VALIDATE write failed: read=0x%04X write=%04X\n", + GCR_sub_reg_names[target_io_reg], local_data16.getHalfWord(0), databuf_16bit.getHalfWord(0) ); + ecmdDataBufferBase &READ_BUF=local_data16; + ecmdDataBufferBase &WRITE_BUF=databuf_16bit; + FAPI_SET_HWP_ERROR(rc, IO_GCR_WRITE_MISMATCH_RC); + } + } - } - } - - } - } - } - } - } - + }while(0); return(rc); } diff --git a/src/usr/hwpf/hwp/bus_training/gcr_funcs.H b/src/usr/hwpf/hwp/bus_training/gcr_funcs.H index 52da6623f..16e6743c7 100644 --- a/src/usr/hwpf/hwp/bus_training/gcr_funcs.H +++ b/src/usr/hwpf/hwp/bus_training/gcr_funcs.H @@ -5,7 +5,7 @@ /* */ /* IBM CONFIDENTIAL */ /* */ -/* COPYRIGHT International Business Machines Corp. 2012,2013 */ +/* COPYRIGHT International Business Machines Corp. 2012,2014 */ /* */ /* p1 */ /* */ @@ -20,127 +20,130 @@ /* Origin: 30 */ /* */ /* IBM_PROLOG_END_TAG */ -// $Id: gcr_funcs.H,v 1.19 2013/06/06 20:40:52 cswenson Exp $
-// *!***************************************************************************
-// *! (C) Copyright International Business Machines Corp. 1997, 1998
-// *! All Rights Reserved -- Property of IBM
-// *! *** IBM Confidential ***
-// *!***************************************************************************
-// *! FILENAME : gcr_funcs.H
-// *! TITLE :
-// *! DESCRIPTION :
-// *! CONTEXT :
-// *!
-// *! OWNER NAME : Varghese, Varkey Email: varkeykv@in.ibm.com
-// *! BACKUP NAME : Swaminathan, Janani Email: jaswamin@in.ibm.com
-// *!
-// *!***************************************************************************
-// CHANGE HISTORY:
-//------------------------------------------------------------------------------
-// Version:|Author: | Date: | Comment:
-// --------|--------|--------|--------------------------------------------------
-// 1.0 |jaswamin|09/13/11|
-// 2.0 |varkeykv|01/12/12| Post GFW review changes
-//------------------------------------------------------------------------------
-
-#ifndef GCR_FUNCS
-#define GCR_FUNCS
-
-/* Include some system headers */
-#include <list>
-#include <stdint.h>
-#include <fapi.H>
-using namespace fapi;
-
-#include "edi_regs.h"
-
-
-enum io_interface_t { CP_PSI,
- CP_FABRIC_X0,
- CP_FABRIC_A0,
- CP_IOMC0_P0,
- CP_IOMC1_P0,
- S1_FABRIC_SX0,
- S1_FABRIC_SA0,
- CEN_DMI,
- };
-
-// P8 chip interfaces
-const uint32_t NUM_INTERFACES=21;
-const char * const io_interface_name[NUM_INTERFACES] = { "CP_PSI",
- "CP_FABRIC_X0",
- "CP_FABRIC_A0",
- "CP_IOMC0_P0",
- "CP_IOMC1_P0",
- "S1_FABRIC_SX0",
- "S1_FABRIC_SA0",
- "CEN_DMI" };
-// EDI register addresses for CP
-const uint32_t ei_reg_addr_GCR_scom[NUM_INTERFACES] = { 0x00000000,
- 0x0401103F,
- 0x08010c3f,
- 0x02011a3F,
- 0x02011e3F,
- 0x03010c3f,
- 0x08010c3f,
- 0x0201043F };
-const uint32_t ei_reg_addr_Mode_scom[NUM_INTERFACES]= { 0x00000000,
- 0x04011020,
- 0x08010c20,
- 0x02011a20,
- 0x02011e20,
- 0x03010c20,
- 0x08010c20,
- 0x02010420 };
-
-
-// Register type
-typedef enum { tx_per_lane, tx_per_group, tx_per_pack, tx_per_bus, rx_per_lane, rx_per_group, rx_per_pack, rx_per_bus, num_register_type } register_type;
-
-typedef enum { gcr_op_read, gcr_op_write } gcr_op;
-
-
-// Lane Bit Defintions
-// 0x00 (lane 0), 0x01 (lane 1) , etc
-const uint8_t SELECT_ALL_LANES=0x1F; // The lane address is a 5 bit value 0b 11111 selects all lanes
-
-// Group Bit Definitions 0x00 group 0 , 0x01 group1 , etc
-const uint8_t RX_GROUP_BROADCAST =0x0F ; // (Write Only) The group address is a 6 bit value to select all groups ,
-const uint8_t TX_GROUP_BROADCAST =0x2F ; // (Write Only) The group address is a 6 bit value to select all groups ,
-
-// ROUTINES
-//------------------------------------------------------------------------------------------------------------------------------------
-// generate the 64 bit scom address for the GCR
-//------------------------------------------------------------------------------------------------------------------------------------
-uint64_t scom_address_64bit(uint32_t gcr_addr, uint64_t gcr_data );
-
-//------------------------------------------------------------------------------------------------------------------------------------
-// handle GCR operations - do not use directly!
-// use GCR_read and GCR_write for reg access - not this function!!!!
-//------------------------------------------------------------------------------------------------------------------------------------
-ReturnCode doGCRop(const Target& chip_target, io_interface_t interface,
- gcr_op read_or_write, GCR_sub_registers target_io_reg,
- uint32_t group_address, uint32_t lane_address,
- ecmdDataBufferBase set_bits, ecmdDataBufferBase clear_bits,
- ecmdDataBufferBase &databuf_16bit, int skipCheck=0,int bypass_rmw=0);
-
-//------------------------------------------------------------------------------------------------------------------------------------
-// GCR SCOM READ - main api for read - do not use doGCRop directly
-//------------------------------------------------------------------------------------------------------------------------------------
-ReturnCode GCR_read(const Target& chip_target, io_interface_t interface,
- GCR_sub_registers target_io_reg, uint32_t group_address,
- uint32_t lane_address, ecmdDataBufferBase &databuf_16bit);
-
-//------------------------------------------------------------------------------------------------------------------------------------
-// GCR SCOM WRITE - main api for write - do not use doGCRop directly
-//------------------------------------------------------------------------------------------------------------------------------------
-ReturnCode GCR_write(const Target& chip_target, io_interface_t interface,
- GCR_sub_registers target_io_reg, uint32_t group_address,
- uint32_t lane_address, ecmdDataBufferBase set_bits,
- ecmdDataBufferBase clear_bits, int skipCheck=0,int bypass_rmw=0);
-
-
-
-
-#endif
-
+// $Id: gcr_funcs.H,v 1.22 2014/03/07 13:13:29 varkeykv Exp $ +// *!*************************************************************************** +// *! (C) Copyright International Business Machines Corp. 1997, 1998 +// *! All Rights Reserved -- Property of IBM +// *! *** IBM Confidential *** +// *!*************************************************************************** +// *! FILENAME : gcr_funcs.H +// *! TITLE : +// *! DESCRIPTION : +// *! CONTEXT : +// *! +// *! OWNER NAME : Varghese, Varkey Email: varkeykv@in.ibm.com +// *! BACKUP NAME : Swaminathan, Janani Email: jaswamin@in.ibm.com +// *! +// *!*************************************************************************** +// CHANGE HISTORY: +//------------------------------------------------------------------------------ +// Version:|Author: | Date: | Comment: +// --------|--------|--------|-------------------------------------------------- +// 1.0 |jaswamin|09/13/11| +// 2.0 |varkeykv|01/12/12| Post GFW review changes +//------------------------------------------------------------------------------ + +#ifndef GCR_FUNCS +#define GCR_FUNCS + +/* Include some system headers */ +#include <list> +#include <stdint.h> +#include <fapi.H> +using namespace fapi; + +#include "edi_regs.h" + + +enum io_interface_t { CP_PSI, + CP_FABRIC_X0, + CP_FABRIC_A0, + CP_IOMC0_P0, + CP_IOMC1_P0, + S1_FABRIC_SX0, + S1_FABRIC_SA0, + CEN_DMI, + }; + +// P8 chip interfaces +const uint32_t NUM_INTERFACES=21; +const char * const io_interface_name[NUM_INTERFACES] = { "CP_PSI", + "CP_FABRIC_X0", + "CP_FABRIC_A0", + "CP_IOMC0_P0", + "CP_IOMC1_P0", + "S1_FABRIC_SX0", + "S1_FABRIC_SA0", + "CEN_DMI" }; +// EDI register addresses for CP +const uint32_t ei_reg_addr_GCR_scom[NUM_INTERFACES] = { 0x00000000, + 0x0401103F, + 0x08010c3f, + 0x02011a3F, + 0x02011e3F, + 0x03010c3f, + 0x08010c3f, + 0x0201043F }; +const uint32_t ei_reg_addr_Mode_scom[NUM_INTERFACES]= { 0x00000000, + 0x04011020, + 0x08010c20, + 0x02011a20, + 0x02011e20, + 0x03010c20, + 0x08010c20, + 0x02010420 }; + + +// Register type +typedef enum { tx_per_lane, tx_per_group, tx_per_pack, tx_per_bus, rx_per_lane, rx_per_group, rx_per_pack, rx_per_bus, num_register_type } register_type; + +typedef enum { gcr_op_read, gcr_op_write } gcr_op; + + const uint32_t num_rxlanes_per_group[NUM_INTERFACES] ={1,20,24,24,24,20,24,18 }; +const uint32_t num_txlanes_per_group[NUM_INTERFACES] ={1,20,24,17,17,20,24,24 }; +const uint32_t num_groups_per_bus[NUM_INTERFACES] = { 1,4,1,1,1,4,1,1}; + +// Lane Bit Defintions +// 0x00 (lane 0), 0x01 (lane 1) , etc +const uint8_t SELECT_ALL_LANES=0x1F; // The lane address is a 5 bit value 0b 11111 selects all lanes + +// Group Bit Definitions 0x00 group 0 , 0x01 group1 , etc +const uint8_t RX_GROUP_BROADCAST =0x0F ; // (Write Only) The group address is a 6 bit value to select all groups , +const uint8_t TX_GROUP_BROADCAST =0x2F ; // (Write Only) The group address is a 6 bit value to select all groups , + +// ROUTINES +//------------------------------------------------------------------------------------------------------------------------------------ +// generate the 64 bit scom address for the GCR +//------------------------------------------------------------------------------------------------------------------------------------ +uint64_t scom_address_64bit(uint32_t gcr_addr, uint64_t gcr_data ); + +//------------------------------------------------------------------------------------------------------------------------------------ +// handle GCR operations - do not use directly! +// use GCR_read and GCR_write for reg access - not this function!!!! +//------------------------------------------------------------------------------------------------------------------------------------ +ReturnCode doGCRop(const Target& chip_target, io_interface_t interface, + gcr_op read_or_write, GCR_sub_registers target_io_reg, + uint32_t group_address, uint32_t lane_address, + ecmdDataBufferBase set_bits, ecmdDataBufferBase clear_bits, + ecmdDataBufferBase &databuf_16bit, int skipCheck=0,int bypass_rmw=0); + +//------------------------------------------------------------------------------------------------------------------------------------ +// GCR SCOM READ - main api for read - do not use doGCRop directly +//------------------------------------------------------------------------------------------------------------------------------------ +ReturnCode GCR_read(const Target& chip_target, io_interface_t interface, + GCR_sub_registers target_io_reg, uint32_t group_address, + uint32_t lane_address, ecmdDataBufferBase &databuf_16bit); + +//------------------------------------------------------------------------------------------------------------------------------------ +// GCR SCOM WRITE - main api for write - do not use doGCRop directly +//------------------------------------------------------------------------------------------------------------------------------------ +ReturnCode GCR_write(const Target& chip_target, io_interface_t interface, + GCR_sub_registers target_io_reg, uint32_t group_address, + uint32_t lane_address, ecmdDataBufferBase set_bits, + ecmdDataBufferBase clear_bits, int skipCheck=0,int bypass_rmw=0); + + + + +#endif + diff --git a/src/usr/hwpf/hwp/bus_training/gcr_funcs_errors.xml b/src/usr/hwpf/hwp/bus_training/gcr_funcs_errors.xml new file mode 100644 index 000000000..bc5206236 --- /dev/null +++ b/src/usr/hwpf/hwp/bus_training/gcr_funcs_errors.xml @@ -0,0 +1,39 @@ +<!-- IBM_PROLOG_BEGIN_TAG --> +<!-- This is an automatically generated prolog. --> +<!-- --> +<!-- $Source: src/usr/hwpf/hwp/bus_training/gcr_funcs_errors.xml $ --> +<!-- --> +<!-- IBM CONFIDENTIAL --> +<!-- --> +<!-- COPYRIGHT International Business Machines Corp. 2014 --> +<!-- --> +<!-- p1 --> +<!-- --> +<!-- Object Code Only (OCO) source materials --> +<!-- Licensed Internal Code Source Materials --> +<!-- IBM HostBoot Licensed Internal Code --> +<!-- --> +<!-- The source code for this program is not published or otherwise --> +<!-- divested of its trade secrets, irrespective of what has been --> +<!-- deposited with the U.S. Copyright Office. --> +<!-- --> +<!-- Origin: 30 --> +<!-- --> +<!-- IBM_PROLOG_END_TAG --> +<!-- $Id: gcr_funcs_errors.xml,v 1.2 2014/03/18 14:56:22 jgrell Exp $ --> + +<!-- Error definitions for gcr_func HWPS --> +<hwpErrors> +<!-- *********************************************************************** --> + <hwpError> + <rc>IO_GCR_WRITE_MISMATCH_RC</rc> + <description>IO GCR write operation failed to readback data that was written</description> + <ffdc>READ_BUF</ffdc> + <ffdc>WRITE_BUF</ffdc> + <callout> + <procedure>CODE</procedure> + <priority>HIGH</priority> + </callout> + </hwpError> +</hwpErrors> + diff --git a/src/usr/hwpf/hwp/bus_training/io_cleanup.C b/src/usr/hwpf/hwp/bus_training/io_cleanup.C index 14e5f0d76..b8a6a2b64 100644 --- a/src/usr/hwpf/hwp/bus_training/io_cleanup.C +++ b/src/usr/hwpf/hwp/bus_training/io_cleanup.C @@ -5,7 +5,7 @@ /* */ /* IBM CONFIDENTIAL */ /* */ -/* COPYRIGHT International Business Machines Corp. 2013 */ +/* COPYRIGHT International Business Machines Corp. 2013,2014 */ /* */ /* p1 */ /* */ @@ -20,308 +20,294 @@ /* Origin: 30 */ /* */ /* IBM_PROLOG_END_TAG */ -// $Id: io_cleanup.C,v 1.3 2013/12/12 08:41:30 varkeykv Exp $
-// *!***************************************************************************
-// *! (C) Copyright International Business Machines Corp. 1997, 1998
-// *! All Rights Reserved -- Property of IBM
-// *! *** IBM Confidential ***
-// *!***************************************************************************
-// *! FILENAME : io_cleanup.C
-// *! TITLE :
-// *! DESCRIPTION : Cleanup procedure for re-init loop
-// *! CONTEXT :
-// *!
-// *! OWNER NAME : Varghese, Varkey Email: varkey.kv@in.ibm.com
-// *! BACKUP NAME : Janani Swaminathan Email: jaswamin@in.ibm.com
-// *!
-// *!***************************************************************************
-// CHANGE HISTORY:
-//------------------------------------------------------------------------------
-// Version:|Author: | Date: | Comment:
-// --------|--------|--------|--------------------------------------------------
-// 1.0 |varkeykv|07/30/11|Initial check in .
-//------------------------------------------------------------------------------
-#include <fapi.H>
-#include "io_cleanup.H"
-#include "gcr_funcs.H"
-
-
-
-extern "C" {
- using namespace fapi;
-// For clearing the FIR mask , used by io run training
-// As per Irving , it should be ok to clear all FIRs here since we will scom init , also we dont touch mask values
-ReturnCode clear_fir_reg(const Target &i_target,fir_io_interface_t i_chip_interface){
- ReturnCode rc;
- ecmdDataBufferBase data(64);
- FAPI_INF("io_cleanup:In the Clear FIR RW register function ");
-
- // use FIR AND mask register to un-mask selected bits
- rc = fapiPutScom(i_target, fir_rw_reg_addr[i_chip_interface], data);
- if (!rc.ok())
- {
- FAPI_ERR("Error writing FIR mask register (=%08X)!",
- fir_rw_reg_addr[i_chip_interface]);
- }
- return(rc);
-}
-
-/*
- from Megan's ipl1.sh
-
- istep -s0..11
-## forcing channel fail
-getscom pu 02011C4A -pall -call -vs1
- getscom cen 0201080A -pall -call -vs1
- putscom pu 02011C4A 8000000480400000 -pall -call
- putscom cen 0201080A 8000000000000000 -pall -call
- getscom pu 02011C4A -pall -call -vs1
- getscom cen 0201080A -pall -call -vs1
-## masking fir bit
-putscom pu.mcs 2011843 FFFFFFFFFFFFFFFF -all
-### IO reset
-iotk put rx_fence=1 -t=p8:bmcs
-iotk put rx_fence=1 -t=cn
-iotk put ioreset_hard_bus0=111111 -t=p8:bmcs
-iotk put ioreset_hard_bus0=111111 -t=cn
-
-#exit
-##clear_fir
-./clear_fir.pl
-### Reload
-istep proc_dmi_scominit
-istep dmi_scominit
-##checking Zcal
-iotk get tx_zcal_p_4x -t=p8:bmcs
-iotk get tx_zcal_p_4x -t=cn
-iotk get tx_zcal_sm_min_val -t=p8:bmcs
-iotk get tx_zcal_sm_min_val -t=cn
-iotk get tx_zcal_sm_max_val -t=p8:bmcs
-iotk get tx_zcal_sm_max_val -t=cn
-### Loading Zcal
-iotk put tx_zcal_p_4x=00100
-iotk put tx_zcal_sm_min_val=0010101
-iotk put tx_zcal_sm_max_val=1000110
-## Runing Zcal
-istep dmi_io_dccal
-## forcing channel fail
- getscom pu 02011C4A -pall -call -vs1
- getscom cen 0201080A -pall -call -vs1
- putscom pu 02011C4A 8000000480400000 -pall -call
- putscom cen 0201080A 8000000000000000 -pall -call
- getscom pu 02011C4A -pall -call -vs1
- getscom cen 0201080A -pall -call -vs1
-
-
-
-
-
-*/
-
-ReturnCode do_cleanup(const Target &master_target,io_interface_t master_interface,uint32_t master_group,const Target &slave_target,io_interface_t slave_interface,uint32_t slave_group)
-{
- ReturnCode rc;
- uint32_t rc_ecmd = 0;
- uint8_t chip_unit = 0;
- // uint8_t link_fir_unmask_data = 0x8F;
- ecmdDataBufferBase data(64);
- ecmdDataBufferBase reg_data(16),set_bits(16),clear_bits(16),temp_bits(16);
-
- //iotk put rx_fence=1 -t=p8:bmcs
- // No other field in this reg , so no need for RMW
- rc_ecmd = temp_bits.setBit(0);
- if(rc_ecmd)
- {
- rc.setEcmdError(rc_ecmd);
- return(rc);
- }
- rc=GCR_write(master_target, master_interface, rx_fence_pg, master_group,0, temp_bits, temp_bits,1,1);
- if(rc) return rc;
-
- //iotk put rx_fence=1 -t=cn
- rc=GCR_write(slave_target, slave_interface, rx_fence_pg, slave_group,0, temp_bits, temp_bits,1,1);
- if(rc) return rc;
-
- rc = FAPI_ATTR_GET(ATTR_CHIP_UNIT_POS,
- &master_target,
- chip_unit);
- if (!rc.ok())
- {
- FAPI_ERR("Error retreiving MCS chiplet number!");
- return rc;
- }
-
- // swizzle to DMI number
- if (master_interface == CP_IOMC0_P0)
- {
- chip_unit = 3-(chip_unit % 4);
- // swap 0 and 1 due to Clock group swap in layout
- if(chip_unit==1){
- chip_unit=0;
- }
- else if(chip_unit==0){
- chip_unit=1;
- }
-
-
- FAPI_DBG("CHIP UNIT IS %d",chip_unit);
-
- }
- rc = fapiGetScom(master_target, scom_mode_pb_reg_addr[FIR_CP_IOMC0_P0], data);
- if (!rc.ok())
- {
- FAPI_ERR("Error Reading SCOM mode PB register for ioreset_hard_bus0 on master side(=%08X)!",
- scom_mode_pb_reg_addr[FIR_CP_IOMC0_P0]);
- return rc;
- }
-
- rc_ecmd = data.setBit(2+chip_unit,1); // Scom_mode_pb ,ioreset starts at bit 2
- if(rc_ecmd)
- {
- rc.setEcmdError(rc_ecmd);
- return(rc);
- }
- FAPI_DBG("Writing the Hard reset on PU ");
- // use FIR AND mask register to un-mask selected bits
- rc = fapiPutScom(master_target, scom_mode_pb_reg_addr[FIR_CP_IOMC0_P0], data);
- if (!rc.ok())
- {
- FAPI_ERR("Error writing SCOM mode PB register for ioreset_hard_bus0 on master side(=%08X)!",
- scom_mode_pb_reg_addr[FIR_CP_IOMC0_P0]);
- return rc;
- }
-
- rc_ecmd = data.flushTo0();
- if(rc_ecmd)
- {
- rc.setEcmdError(rc_ecmd);
- return(rc);
- }
- // Centaur is always bus0 in reset register
- if(slave_interface == CEN_DMI){
- chip_unit=0;
- }
- rc = fapiGetScom(slave_target, scom_mode_pb_reg_addr[FIR_CEN_DMI], data);
- if (!rc.ok())
- {
- FAPI_ERR("Error Reading SCOM mode PB register for ioreset_hard_bus0 on Slave side(=%08X)!",
- scom_mode_pb_reg_addr[FIR_CEN_DMI]);
- return rc;
- }
- rc_ecmd = data.setBit(2+chip_unit,1); // Scom_mode_pb ,ioreset starts at bit 2
- if(rc_ecmd)
- {
- rc.setEcmdError(rc_ecmd);
- return(rc);
- }
- // use FIR AND mask register to un-mask selected bits
- rc = fapiPutScom(slave_target, scom_mode_pb_reg_addr[FIR_CEN_DMI], data);
- if (!rc.ok())
- {
- FAPI_ERR("Error writing SCOM mode PB register for ioreset_hard_bus0 on Slave side(=%08X)!",
- scom_mode_pb_reg_addr[FIR_CEN_DMI]);
- return rc;
- }
-
-
- // NOW We clear FIRS.. need to see if we need to do this or some other procedure will do this . Bellows/Irving to respond
-
- rc = clear_fir_reg(slave_target,FIR_CEN_DMI);
- if(rc)
- {
- return(rc);
- }
- rc = clear_fir_reg(master_target,FIR_CP_IOMC0_P0);
- if(rc)
- {
- return(rc);
- }
- return rc;
-}
-
-// Determines if target is a master...
-static ReturnCode isChipMaster(const Target& chip_target, io_interface_t chip_interface,uint32_t current_group, bool & masterchip_found ) {
- ReturnCode rc;
- ecmdDataBufferBase mode_data(16);
- masterchip_found=false;
-
- // Check if rx_master_mode bit is set for chip
- // Read rx_master_mode for chip
- if(chip_interface==CP_FABRIC_X0)
- {
- rc=GCR_read(chip_target , chip_interface, ei4_rx_mode_pg, current_group,0, mode_data);
- }
- else
- {
- rc=GCR_read(chip_target , chip_interface, rx_mode_pg, current_group,0, mode_data);
- }
- if (rc) {
- FAPI_ERR("io_cleanup: Error reading master mode bit\n");
- }
- else
- {
- // Check if chip is master
- if (mode_data.isBitSet(0)) {
- FAPI_DBG("This chip is a master\n");
- masterchip_found =true;
- }
- }
- return(rc);
-}
-
-
-// Cleans up for Centaur Reconfig or Abus hot plug case
-ReturnCode io_cleanup(const Target &master_target,const Target &slave_target){
- ReturnCode rc;
- io_interface_t master_interface,slave_interface;
- uint32_t master_group=0;
- uint32_t slave_group=0;
- // const uint32_t max_group=4; // Num of X bus groups in one bus
-
- bool is_master=false;
-
-
- // This is a DMI/MC bus
- if( (master_target.getType() == fapi::TARGET_TYPE_MCS_CHIPLET )&& (slave_target.getType() == fapi::TARGET_TYPE_MEMBUF_CHIP)){
- FAPI_DBG("This is a DMI bus using base DMI scom address");
- master_interface=CP_IOMC0_P0; // base scom for MC bus
- slave_interface=CEN_DMI; // Centaur scom base
- master_group=3; // Design requires us to do this as per scom map and layout
- slave_group=0;
- rc=isChipMaster(master_target,master_interface,master_group,is_master);
- if(rc.ok()){
- if(!is_master)
- {
- FAPI_DBG("DMI Bus ..target swap performed");
- rc=do_cleanup(slave_target,slave_interface,slave_group,master_target,master_interface,master_group);
- if(rc) return rc;
- }
- else
- {
- rc=do_cleanup(master_target,master_interface,master_group,slave_target,slave_interface,slave_group);
- if(rc) return rc;
- }
- }
- }
- //This is an A Bus
- else if( (master_target.getType() == fapi::TARGET_TYPE_ABUS_ENDPOINT )&& (slave_target.getType() == fapi::TARGET_TYPE_ABUS_ENDPOINT)){
- FAPI_DBG("This is an A Bus training invocation");
- master_interface=CP_FABRIC_A0; // base scom for A bus , assume translation to A1 by PLAT
- slave_interface=CP_FABRIC_A0; //base scom for A bus
- master_group=0; // Design requires us to do this as per scom map and layout
- slave_group=0;
- rc=isChipMaster(master_target,master_interface,master_group,is_master);
- if(rc.ok()){
- // Now only for DMI
- }
- }
- else{
- FAPI_ERR("Invalid io_cleanup HWP invocation . Pair of targets dont belong to DMI or A bus instances");
- FAPI_SET_HWP_ERROR(rc, IO_RUN_TRAINING_INVALID_INVOCATION_RC);
- }
- return rc;
-}
-
-
-
-} // extern
+// $Id: io_cleanup.C,v 1.5 2014/03/13 16:01:03 varkeykv Exp $ +// *!*************************************************************************** +// *! (C) Copyright International Business Machines Corp. 1997, 1998 +// *! All Rights Reserved -- Property of IBM +// *! *** IBM Confidential *** +// *!*************************************************************************** +// *! FILENAME : io_cleanup.C +// *! TITLE : +// *! DESCRIPTION : Cleanup procedure for re-init loop +// *! CONTEXT : +// *! +// *! OWNER NAME : Varghese, Varkey Email: varkey.kv@in.ibm.com +// *! BACKUP NAME : Janani Swaminathan Email: jaswamin@in.ibm.com +// *! +// *!*************************************************************************** +// CHANGE HISTORY: +//------------------------------------------------------------------------------ +// Version:|Author: | Date: | Comment: +// --------|--------|--------|-------------------------------------------------- +// 1.0 |varkeykv|07/30/11|Initial check in . +//------------------------------------------------------------------------------ +#include <fapi.H> +#include "io_cleanup.H" +#include "gcr_funcs.H" + + + +extern "C" { + using namespace fapi; +// For clearing the FIR mask , used by io run training +// As per Irving , it should be ok to clear all FIRs here since we will scom init , also we dont touch mask values +ReturnCode clear_fir_reg(const Target &i_target,fir_io_interface_t i_chip_interface){ + ReturnCode rc; + ecmdDataBufferBase data(64); + FAPI_INF("io_cleanup:In the Clear FIR RW register function "); + + // use FIR AND mask register to un-mask selected bits + rc = fapiPutScom(i_target, fir_rw_reg_addr[i_chip_interface], data); + if (!rc.ok()) + { + FAPI_ERR("Error writing FIR mask register (=%08X)!", + fir_rw_reg_addr[i_chip_interface]); + } + return(rc); +} + +/* + from Megan's ipl1.sh + + istep -s0..11 +## forcing channel fail +getscom pu 02011C4A -pall -call -vs1 + getscom cen 0201080A -pall -call -vs1 + putscom pu 02011C4A 8000000480400000 -pall -call + putscom cen 0201080A 8000000000000000 -pall -call + getscom pu 02011C4A -pall -call -vs1 + getscom cen 0201080A -pall -call -vs1 +## masking fir bit +putscom pu.mcs 2011843 FFFFFFFFFFFFFFFF -all +### IO reset +iotk put rx_fence=1 -t=p8:bmcs +iotk put rx_fence=1 -t=cn +iotk put ioreset_hard_bus0=111111 -t=p8:bmcs +iotk put ioreset_hard_bus0=111111 -t=cn + +#exit +##clear_fir +./clear_fir.pl +### Reload +istep proc_dmi_scominit +istep dmi_scominit +##checking Zcal +iotk get tx_zcal_p_4x -t=p8:bmcs +iotk get tx_zcal_p_4x -t=cn +iotk get tx_zcal_sm_min_val -t=p8:bmcs +iotk get tx_zcal_sm_min_val -t=cn +iotk get tx_zcal_sm_max_val -t=p8:bmcs +iotk get tx_zcal_sm_max_val -t=cn +### Loading Zcal +iotk put tx_zcal_p_4x=00100 +iotk put tx_zcal_sm_min_val=0010101 +iotk put tx_zcal_sm_max_val=1000110 +## Runing Zcal +istep dmi_io_dccal +## forcing channel fail + getscom pu 02011C4A -pall -call -vs1 + getscom cen 0201080A -pall -call -vs1 + putscom pu 02011C4A 8000000480400000 -pall -call + putscom cen 0201080A 8000000000000000 -pall -call + getscom pu 02011C4A -pall -call -vs1 + getscom cen 0201080A -pall -call -vs1 +*/ + +ReturnCode do_cleanup(const Target &master_target,io_interface_t master_interface,uint32_t master_group,const Target &slave_target,io_interface_t slave_interface,uint32_t slave_group) +{ + ReturnCode rc; + uint32_t rc_ecmd = 0; + uint8_t chip_unit = 0; + ecmdDataBufferBase data(64); + ecmdDataBufferBase reg_data(16),set_bits(16),clear_bits(16),temp_bits(16); + + //iotk put rx_fence=1 -t=p8:bmcs + // No other field in this reg , so no need for RMW + rc_ecmd = temp_bits.setBit(0); + if(rc_ecmd) + { + rc.setEcmdError(rc_ecmd); + return(rc); + } + rc=GCR_write(master_target, master_interface, rx_fence_pg, master_group,0, temp_bits, temp_bits,1,1); + if(rc) return rc; + + //iotk put rx_fence=1 -t=cn + rc=GCR_write(slave_target, slave_interface, rx_fence_pg, slave_group,0, temp_bits, temp_bits,1,1); + if(rc) return rc; + + rc = FAPI_ATTR_GET(ATTR_CHIP_UNIT_POS, + &master_target, + chip_unit); + if (!rc.ok()) + { + FAPI_ERR("Error retreiving MCS chiplet number!"); + return rc; + } + + // swizzle to DMI number + if (master_interface == CP_IOMC0_P0) + { + chip_unit = 3-(chip_unit % 4); + // swap 0 and 1 due to Clock group swap in layout + if(chip_unit==1){ + chip_unit=0; + } + else if(chip_unit==0){ + chip_unit=1; + } + + + FAPI_DBG("CHIP UNIT IS %d",chip_unit); + + } + rc = fapiGetScom(master_target, scom_mode_pb_reg_addr[FIR_CP_IOMC0_P0], data); + if (!rc.ok()) + { + FAPI_ERR("Error Reading SCOM mode PB register for ioreset_hard_bus0 on master side(=%08X)!", + scom_mode_pb_reg_addr[FIR_CP_IOMC0_P0]); + return rc; + } + + rc_ecmd = data.setBit(2+chip_unit,1); // Scom_mode_pb ,ioreset starts at bit 2 + if(rc_ecmd) + { + rc.setEcmdError(rc_ecmd); + return(rc); + } + FAPI_DBG("Writing the Hard reset on PU "); + // use FIR AND mask register to un-mask selected bits + rc = fapiPutScom(master_target, scom_mode_pb_reg_addr[FIR_CP_IOMC0_P0], data); + if (!rc.ok()) + { + FAPI_ERR("Error writing SCOM mode PB register for ioreset_hard_bus0 on master side(=%08X)!", + scom_mode_pb_reg_addr[FIR_CP_IOMC0_P0]); + return rc; + } + + rc_ecmd = data.flushTo0(); + if(rc_ecmd) + { + rc.setEcmdError(rc_ecmd); + return(rc); + } + // Centaur is always bus0 in reset register + if(slave_interface == CEN_DMI){ + chip_unit=0; + } + rc = fapiGetScom(slave_target, scom_mode_pb_reg_addr[FIR_CEN_DMI], data); + if (!rc.ok()) + { + FAPI_ERR("Error Reading SCOM mode PB register for ioreset_hard_bus0 on Slave side(=%08X)!", + scom_mode_pb_reg_addr[FIR_CEN_DMI]); + return rc; + } + rc_ecmd = data.setBit(2+chip_unit,1); // Scom_mode_pb ,ioreset starts at bit 2 + if(rc_ecmd) + { + rc.setEcmdError(rc_ecmd); + return(rc); + } + // use FIR AND mask register to un-mask selected bits + rc = fapiPutScom(slave_target, scom_mode_pb_reg_addr[FIR_CEN_DMI], data); + if (!rc.ok()) + { + FAPI_ERR("Error writing SCOM mode PB register for ioreset_hard_bus0 on Slave side(=%08X)!", + scom_mode_pb_reg_addr[FIR_CEN_DMI]); + return rc; + } + + + // NOW We clear FIRS.. need to see if we need to do this or some other procedure will do this . Bellows/Irving to respond + + rc = clear_fir_reg(slave_target,FIR_CEN_DMI); + if(rc) + { + return(rc); + } + rc = clear_fir_reg(master_target,FIR_CP_IOMC0_P0); + if(rc) + { + return(rc); + } + return rc; +} + +// Determines if target is a master... +static ReturnCode isChipMaster(const Target& chip_target, io_interface_t chip_interface,uint32_t current_group, bool & masterchip_found ) { + ReturnCode rc; + ecmdDataBufferBase mode_data(16); + masterchip_found=false; + + // Check if rx_master_mode bit is set for chip + // Read rx_master_mode for chip + if(chip_interface==CP_FABRIC_X0) + { + rc=GCR_read(chip_target , chip_interface, ei4_rx_mode_pg, current_group,0, mode_data); + } + else + { + rc=GCR_read(chip_target , chip_interface, rx_mode_pg, current_group,0, mode_data); + } + if (rc) { + FAPI_ERR("io_cleanup: Error reading master mode bit\n"); + } + else + { + // Check if chip is master + if (mode_data.isBitSet(0)) { + FAPI_DBG("This chip is a master\n"); + masterchip_found =true; + } + } + return(rc); +} + + +// Cleans up for Centaur Reconfig or Abus hot plug case +ReturnCode io_cleanup(const Target &master_target,const Target &slave_target){ + ReturnCode rc; + io_interface_t master_interface,slave_interface; + uint32_t master_group=0; + uint32_t slave_group=0; + bool is_master=false; + + + // This is a DMI/MC bus + if( (master_target.getType() == fapi::TARGET_TYPE_MCS_CHIPLET )&& (slave_target.getType() == fapi::TARGET_TYPE_MEMBUF_CHIP)){ + FAPI_DBG("This is a DMI bus using base DMI scom address"); + master_interface=CP_IOMC0_P0; // base scom for MC bus + slave_interface=CEN_DMI; // Centaur scom base + master_group=3; // Design requires us to do this as per scom map and layout + slave_group=0; + rc=isChipMaster(master_target,master_interface,master_group,is_master); + if(rc.ok()){ + if(!is_master) + { + FAPI_DBG("DMI Bus ..target swap performed"); + rc=do_cleanup(slave_target,slave_interface,slave_group,master_target,master_interface,master_group); + if(rc) return rc; + } + else + { + rc=do_cleanup(master_target,master_interface,master_group,slave_target,slave_interface,slave_group); + if(rc) return rc; + } + } + } + //This is an A Bus + else if( (master_target.getType() == fapi::TARGET_TYPE_ABUS_ENDPOINT )&& (slave_target.getType() == fapi::TARGET_TYPE_ABUS_ENDPOINT)){ + // This procedure only supports DMI for now + } + else{ + const Target &MASTER_TARGET = master_target; + const Target &SLAVE_TARGET = slave_target; + FAPI_ERR("Invalid io_cleanup HWP invocation . Pair of targets dont belong to DMI or A bus instances"); + FAPI_SET_HWP_ERROR(rc, IO_CLEANUP_INVALID_INVOCATION_RC); + } + return rc; +} + + + +} // extern diff --git a/src/usr/hwpf/hwp/bus_training/io_cleanup.H b/src/usr/hwpf/hwp/bus_training/io_cleanup.H index 3368d20a2..713e25fda 100644 --- a/src/usr/hwpf/hwp/bus_training/io_cleanup.H +++ b/src/usr/hwpf/hwp/bus_training/io_cleanup.H @@ -5,7 +5,7 @@ /* */ /* IBM CONFIDENTIAL */ /* */ -/* COPYRIGHT International Business Machines Corp. 2013 */ +/* COPYRIGHT International Business Machines Corp. 2013,2014 */ /* */ /* p1 */ /* */ @@ -20,7 +20,8 @@ /* Origin: 30 */ /* */ /* IBM_PROLOG_END_TAG */ -//$Id: io_cleanup.H,v 1.1 2013/07/30 12:00:50 varkeykv Exp $
+
+//$Id: io_cleanup.H,v 1.2 2013/12/10 09:22:24 varkeykv Exp $
#ifndef IO_CLEANUP_H_
#define IO_CLEANUP_H_
diff --git a/src/usr/hwpf/hwp/bus_training/io_cleanup_errors.xml b/src/usr/hwpf/hwp/bus_training/io_cleanup_errors.xml new file mode 100755 index 000000000..9899996d1 --- /dev/null +++ b/src/usr/hwpf/hwp/bus_training/io_cleanup_errors.xml @@ -0,0 +1,35 @@ +<!-- IBM_PROLOG_BEGIN_TAG --> +<!-- This is an automatically generated prolog. --> +<!-- --> +<!-- $Source: src/usr/hwpf/hwp/bus_training/io_cleanup_errors.xml $ --> +<!-- --> +<!-- IBM CONFIDENTIAL --> +<!-- --> +<!-- COPYRIGHT International Business Machines Corp. 2014 --> +<!-- --> +<!-- p1 --> +<!-- --> +<!-- Object Code Only (OCO) source materials --> +<!-- Licensed Internal Code Source Materials --> +<!-- IBM HostBoot Licensed Internal Code --> +<!-- --> +<!-- The source code for this program is not published or otherwise --> +<!-- divested of its trade secrets, irrespective of what has been --> +<!-- deposited with the U.S. Copyright Office. --> +<!-- --> +<!-- Origin: 30 --> +<!-- --> +<!-- IBM_PROLOG_END_TAG --> +<!-- $Id: io_cleanup_errors.xml,v 1.3 2014/03/19 18:05:51 smcprek Exp $ --> +<hwpErrors> + <hwpError> + <rc>IO_CLEANUP_INVALID_INVOCATION_RC</rc> + <description>io run training invoked with wrong pair of targets</description> + <ffdc>MASTER_TARGET</ffdc> + <ffdc>SLAVE_TARGET</ffdc> + <callout> + <procedure>CODE</procedure> + <priority>HIGH</priority> + </callout> + </hwpError> +</hwpErrors> diff --git a/src/usr/hwpf/hwp/bus_training/io_clear_firs.C b/src/usr/hwpf/hwp/bus_training/io_clear_firs.C index f4d9771fb..b7f4205e2 100644 --- a/src/usr/hwpf/hwp/bus_training/io_clear_firs.C +++ b/src/usr/hwpf/hwp/bus_training/io_clear_firs.C @@ -5,7 +5,7 @@ /* */ /* IBM CONFIDENTIAL */ /* */ -/* COPYRIGHT International Business Machines Corp. 2013 */ +/* COPYRIGHT International Business Machines Corp. 2013,2014 */ /* */ /* p1 */ /* */ @@ -20,7 +20,7 @@ /* Origin: 30 */ /* */ /* IBM_PROLOG_END_TAG */ -// $Id: io_clear_firs.C,v 1.14 2013/06/20 13:29:37 jmcgill Exp $ +// $Id: io_clear_firs.C,v 1.16 2014/03/20 16:15:49 varkeykv Exp $ // *!*************************************************************************** // *! (C) Copyright International Business Machines Corp. 2012, 2013 // *! All Rights Reserved -- Property of IBM @@ -151,6 +151,7 @@ ReturnCode io_clear_firs(const fapi::Target &i_target){ io_interface_t gcr_interface; // requires different base address for gcr scoms uint32_t group=0; uint32_t max_group=1; + const fapi::Target &ENDPOINT=i_target;
//on dmi if( (i_target.getType() == fapi::TARGET_TYPE_MCS_CHIPLET )){ diff --git a/src/usr/hwpf/hwp/bus_training/io_dccal.C b/src/usr/hwpf/hwp/bus_training/io_dccal.C index 63fd6526d..d9d662193 100644 --- a/src/usr/hwpf/hwp/bus_training/io_dccal.C +++ b/src/usr/hwpf/hwp/bus_training/io_dccal.C @@ -20,7 +20,7 @@ /* Origin: 30 */ /* */ /* IBM_PROLOG_END_TAG */ -// $Id: io_dccal.C,v 1.31 2014/02/17 07:07:39 jaswamin Exp $ +// $Id: io_dccal.C,v 1.35 2014/03/20 08:37:35 varkeykv Exp $ // *!*************************************************************************** // *! (C) Copyright International Business Machines Corp. 1997, 1998 // *! All Rights Reserved -- Property of IBM @@ -115,26 +115,64 @@ ReturnCode run_offset_cal(const Target &target,io_interface_t master_interface,u ecmdDataBufferBase rx_wt_timeout_sel_buf(16),rx_pdwn_lite_value_buf(16),rx_eo_latch_offset_done_buf(16),rx_wt_cu_pll_pgooddly_buf(16),rx_wt_cu_pll_pgooddly_buf_copy(16); ecmdDataBufferBase set_bits(16); ecmdDataBufferBase clear_bits(16); + const fapi::Target &TARGET=target; //char printStr[200]; FAPI_DBG("In the Dccal procedure"); + uint8_t ddlevel; + + rc = FAPI_ATTR_GET(ATTR_CHIP_EC_FEATURE_MCD_HANG_RECOVERY_BUG, &target,ddlevel); + if(rc) + { + FAPI_ERR("IO_DCCAL :Error Reading DDLEVEL using MCD_HANG_RECOVERY attribute"); + return rc; + } + + + + FAPI_DBG("DDLevel FLAG is read as %d",ddlevel); + io_interface_t chip_interface=master_interface;//first we run on master chip uint32_t group=master_group; const Target *target_ptr=⌖ // Assuming I am allowed to do this . - rc=GCR_read(*target_ptr,master_interface,rx_training_status_pg ,group,0,data_buffer);if (rc) {return(rc);} // have to add support for field parsing + rc=GCR_read(*target_ptr,master_interface,rx_training_status_pg ,group,0,data_buffer); + if (rc) + { + // have to add support for field parsing + FAPI_ERR("IO_DCCAL : GCR_read error for rx_training_status_pg"); + return rc; + } FAPI_DBG("IO_DCCAL : Starting Offset Calibration on interface %d group %d",chip_interface,group); // read and save rx_pdwn_lite_disable //int read_bit=rx_pdwn_lite_disable; rc= GCR_read(*target_ptr,master_interface,rx_mode_pg ,group,0,rx_pdwn_lite_value_buf);if (rc) {return(rc);} //int rx_pdwn_lite_value=rx_wt_timeout_sel_buf.getHalfWord(0) & read_bit; - + if (rc) + { + FAPI_ERR("IO_DCCAL : GCR_read error for rx_mode_pg"); + return rc; + } // read and save rx_wt_timeout_sel //read_bit=rx_wt_timeout_sel_tap7; //find the 3 bit value of the field. need it to be all 1's to do an & - rc= GCR_read(*target_ptr,master_interface,rx_timeout_sel_pg ,group,0,rx_wt_timeout_sel_buf);if (rc) {return(rc);} + // -- REVIEW , think this read is safe + rc= GCR_read(*target_ptr,master_interface,rx_timeout_sel_pg ,group,0,rx_wt_timeout_sel_buf); + if (rc) + { + FAPI_ERR("IO_DCCAL : GCR_read error for rx_timeout_sel_pg"); + return rc; + } + //int rx_wt_timeout_value=rx_wt_timeout_sel_buf.getHalfWord(0) & read_bit; //read and save rx_wt_cu_pll_pgooddly //read_bit=rx_wt_cu_pll_pgooddly_disable; // selects 111 for the 3 bit field.need it to be all 1's to do an & - rc= GCR_read(*target_ptr,master_interface,rx_wiretest_pll_cntl_pg,group,0,rx_wt_cu_pll_pgooddly_buf);if (rc) {return(rc);} + rc= GCR_read(*target_ptr,master_interface,rx_wiretest_pll_cntl_pg,group,0,rx_wt_cu_pll_pgooddly_buf); + if (rc) + { + FAPI_ERR("IO_DCCAL : GCR_read error for rx_wiretest_pll_cntl_pgrx_wiretest_pll_cntl_pg"); + return rc; + } + + //int rx_wt_cu_pll_pgooddly_value=rx_wt_cu_pll_pgooddly_buf.getHalfWord(0) & read_bit; //read and save rx_wt_cu_pll_reset @@ -148,26 +186,31 @@ ReturnCode run_offset_cal(const Target &target,io_interface_t master_interface,u // set power down lite disable, rx_pdwn_lite_disable bits=rx_pdwn_lite_disable; //bits=1; - set_bits.insert(rx_pdwn_lite_value_buf,0,16); + rc_ecmd|=set_bits.insert(rx_pdwn_lite_value_buf,0,16); //rc_ecmd|=set_bits.insert(bits,0,16); //rc_ecmd|=set_bits.insert(bits,2,1); //rc_ecmd|=set_bits.setOr(bits,0,16); - set_bits.setBit(2); + rc_ecmd|=set_bits.setBit(2); bits=rx_pdwn_lite_disable_clear; //rc_ecmd|=clear_bits.insert(bits,0,16); rc_ecmd|=clear_bits.flushTo0(); if(rc_ecmd) { + FAPI_ERR("IO_DCCAL : error power down lite disable"); rc.setEcmdError(rc_ecmd); return(rc); } - rc=GCR_write(*target_ptr,chip_interface,rx_mode_pg,group,0,set_bits ,clear_bits);if (rc) {return(rc);} - + rc=GCR_write(*target_ptr,chip_interface,rx_mode_pg,group,0,set_bits ,clear_bits); + if (rc) + { + FAPI_ERR("IO_DCCAL : GCR_write error for rx_mode_pg"); + return rc; + } //write rx_wt_cu_pll_pgooddly to '111' rc_ecmd|=set_bits.insert(rx_wt_cu_pll_pgooddly_buf,0,16); - set_bits.setBit(2); - set_bits.setBit(3); - set_bits.setBit(4); + rc_ecmd|=set_bits.setBit(2); + rc_ecmd|=set_bits.setBit(3); + rc_ecmd|=set_bits.setBit(4); bits=rx_wt_cu_pll_pgooddly_clear; rc_ecmd|=clear_bits.flushTo0(); if(rc_ecmd) @@ -175,24 +218,43 @@ ReturnCode run_offset_cal(const Target &target,io_interface_t master_interface,u rc.setEcmdError(rc_ecmd); return(rc); } - rc=GCR_write(*target_ptr,chip_interface,rx_wiretest_pll_cntl_pg,group,0,set_bits ,clear_bits);if (rc) {return(rc);} + rc=GCR_write(*target_ptr,chip_interface,rx_wiretest_pll_cntl_pg,group,0,set_bits ,clear_bits); + if (rc) + { + FAPI_ERR("IO_DCCAL : GCR_write error for rx_wiretest_pll_cntl_pg"); + return rc; + } // write rx_wt_timeout_sel to '111' bits=rx_wt_timeout_sel_tap7; - set_bits.insert(rx_wt_timeout_sel_buf,0,16); - set_bits.setBit(9); - set_bits.setBit(10); - set_bits.setBit(11); + rc_ecmd|=set_bits.insert(rx_wt_timeout_sel_buf,0,16); + //Update for DDLEVEL - as per Garys find + if(ddlevel==1){ + rc_ecmd|= set_bits.setBit(9); + rc_ecmd|= set_bits.setBit(10); + rc_ecmd|= set_bits.setBit(11); + }else{ + rc_ecmd|= set_bits.setBit(10); + rc_ecmd|= set_bits.setBit(11); + rc_ecmd|= set_bits.setBit(12); + } bits=rx_wt_timeout_sel_clear; //rc_ecmd|=clear_bits.insert(bits,0,16); rc_ecmd|=clear_bits.flushTo0(); if(rc_ecmd) { rc.setEcmdError(rc_ecmd); + FAPI_ERR("IO_DCCAL : error clearing bits for GCR_write rx_timeout_sel_pgrx_timeout_sel_pg"); return(rc); } - rc=GCR_write(*target_ptr,chip_interface,rx_timeout_sel_pg,group,0,set_bits ,clear_bits);if (rc) {return(rc);} - + // -- REVIEW , here bits are not used , only set_bits which are now conditioanlized + rc=GCR_write(*target_ptr,chip_interface,rx_timeout_sel_pg,group,0,set_bits ,clear_bits); + if (rc) + { + FAPI_ERR("IO_DCCAL : GCR_write error for rx_timeout_sel_pg"); + return rc; + } + //writw rx_start_offset_cal to '1' bits=rx_start_offset_cal; @@ -202,15 +264,21 @@ ReturnCode run_offset_cal(const Target &target,io_interface_t master_interface,u if(rc_ecmd) { rc.setEcmdError(rc_ecmd); + FAPI_ERR("IO_DCCAL : error setting up clear bits for GCR_write rx_training_start_pg"); return(rc); } rc=GCR_write(*target_ptr,chip_interface,rx_training_start_pg,group,0,set_bits ,clear_bits);if (rc) {return(rc);} - + + if (rc) + { + FAPI_ERR("IO_DCCAL : GCR_write error for rx_training_start_pg"); + return rc; + } //write rx_wt_cu_pll_reset to '1' rc= GCR_read(*target_ptr,master_interface,rx_wiretest_pll_cntl_pg,group,0,rx_wt_cu_pll_pgooddly_buf_copy);if (rc) {return(rc);} rc_ecmd|=set_bits.insert(rx_wt_cu_pll_pgooddly_buf_copy,0,16); //set_bits.setBit(0); - set_bits.setBit(1); + rc_ecmd|=set_bits.setBit(1); //set_bits.setBit(2); //set_bits.setBit(3); //set_bits.setBit(4); @@ -218,15 +286,26 @@ ReturnCode run_offset_cal(const Target &target,io_interface_t master_interface,u rc_ecmd|=clear_bits.flushTo0(); if(rc_ecmd) { + FAPI_ERR("IO_DCCAL : error setting up set_bits and clear_bits for GCR_write rx_wiretest_pll_cntl_pg"); rc.setEcmdError(rc_ecmd); return(rc); } - rc=GCR_write(*target_ptr,chip_interface,rx_wiretest_pll_cntl_pg,group,0,set_bits ,clear_bits);if (rc) {return(rc);} + rc=GCR_write(*target_ptr,chip_interface,rx_wiretest_pll_cntl_pg,group,0,set_bits ,clear_bits); + if(rc) + { + FAPI_ERR("IO_DCCAL : GCR_write error for rx_wiretest_pll_cntl_pg"); + return rc; + } //write rx_wt_cu_pll_pgood to '1' - rc= GCR_read(*target_ptr,master_interface,rx_wiretest_pll_cntl_pg,group,0,rx_wt_cu_pll_pgooddly_buf_copy);if (rc) {return(rc);} + rc= GCR_read(*target_ptr,master_interface,rx_wiretest_pll_cntl_pg,group,0,rx_wt_cu_pll_pgooddly_buf_copy); + if (rc) + { + FAPI_ERR("IO_DCCAL : GCR_read error for rx_wiretest_pll_cntl_pg"); + return rc; + } rc_ecmd|=set_bits.insert(rx_wt_cu_pll_pgooddly_buf_copy,0,16); - set_bits.setBit(0); + rc_ecmd|=set_bits.setBit(0); //set_bits.setBit(1); //set_bits.setBit(2); //set_bits.setBit(3); @@ -235,41 +314,74 @@ ReturnCode run_offset_cal(const Target &target,io_interface_t master_interface,u rc_ecmd|=clear_bits.flushTo0(); if(rc_ecmd) { + FAPI_ERR("IO_DCCAL : error setting up set_bits and clear_bits for GCR_write rx_wiretest_pll_cntl_pg"); rc.setEcmdError(rc_ecmd); return(rc); } - rc=GCR_write(*target_ptr,chip_interface,rx_wiretest_pll_cntl_pg,group,0,set_bits ,clear_bits);if (rc) {return(rc);} + rc=GCR_write(*target_ptr,chip_interface,rx_wiretest_pll_cntl_pg,group,0,set_bits ,clear_bits); + if (rc) + { + FAPI_ERR("IO_DCCAL : GCR_write error for rx_wiretest_pll_cntl_pg"); + return rc; + } fapiDelay(100000000,10000000); //Wait 100ms for zcal to complete before polling the status register //write rx_wt_timeout_sel to '000' - set_bits.insert(rx_wt_timeout_sel_buf,0,16); - set_bits.clearBit(9); - set_bits.clearBit(10); - set_bits.clearBit(11); + rc_ecmd|= set_bits.insert(rx_wt_timeout_sel_buf,0,16); + if(ddlevel==1){ + rc_ecmd|= set_bits.clearBit(9); + rc_ecmd|= set_bits.clearBit(10); + rc_ecmd|= set_bits.clearBit(11); + }else{ + rc_ecmd|= set_bits.clearBit(10); + rc_ecmd|= set_bits.clearBit(11); + rc_ecmd|= set_bits.clearBit(12); + } bits=rx_wt_timeout_sel_clear; //rc_ecmd|=clear_bits.insert(bits,0,16); rc_ecmd|=clear_bits.flushTo0(); if(rc_ecmd) { + FAPI_ERR("IO_DCCAL : error setting up set_bits and clear_bits for GCR_write rx_timeout_sel_pg"); rc.setEcmdError(rc_ecmd); return(rc); } - rc=GCR_write(*target_ptr,chip_interface,rx_timeout_sel_pg,group,0,set_bits ,clear_bits);if (rc) {return(rc);} + //-- REVIEW here also bits var is not used but above dlevel conditions take care + rc=GCR_write(*target_ptr,chip_interface,rx_timeout_sel_pg,group,0,set_bits ,clear_bits); + if (rc) + { + FAPI_ERR("IO_DCCAL : error GCR_write rx_timeout_sel_pg"); + return rc; + } // Poll for the done bit - rc=GCR_read(*target_ptr,master_interface,rx_training_status_pg ,group,0,data_buffer);if (rc) {return(rc);} // have to add support for field parsing + + rc=GCR_read(*target_ptr,master_interface,rx_training_status_pg ,group,0,data_buffer); + if (rc) + { + FAPI_ERR("IO_DCCAL : error GCR_read rx_training_status_pg"); + return rc; + } int done_bit=rx_offset_cal_done; int fail_bit=rx_offset_cal_failed; bool fail= data_buffer.getHalfWord(0) & fail_bit; bool done = data_buffer.getHalfWord(0)& done_bit; int timeoutCnt = 0; - while ( ( !done ) && ( timeoutCnt < 5000 ) && !fail ) + //Updating timeout as per Gary/Joe's defect SW251251 to be ~1s than the 50s earlier count + // This needs to be regressed in lab + while ( ( !done ) && ( timeoutCnt < 100 ) && !fail ) { // wait for 80000 time units // Time units may be something for simulation, and something else (or nothing) for hardware // At any rate, this is intended to be approximately 100 us. - rc=GCR_read(*target_ptr,chip_interface,rx_training_status_pg,group,0,data_buffer); if (rc) {return(rc);}// have to add support for field parsing + rc=GCR_read(*target_ptr,chip_interface,rx_training_status_pg,group,0,data_buffer); + if (rc) + { + // have to add support for field parsing + FAPI_ERR("IO_DCCAL : error GCR_read rx_training_status_pg in polling for done bit loop"); + return rc; + } fail= data_buffer.getHalfWord(0) & fail_bit; done = data_buffer.getHalfWord(0)& done_bit; fapiDelay(10000000,10000000); @@ -280,29 +392,42 @@ ReturnCode run_offset_cal(const Target &target,io_interface_t master_interface,u { FAPI_ERR("IO Offset cal error on interface %d",chip_interface); //Set HWP error + io_interface_t& CHIP_INTERFACE = chip_interface; + ecmdDataBufferBase& DATA_BUFFER = data_buffer; + int& FAIL_BIT = fail_bit; + const Target &TARGET = target; + FAPI_SET_HWP_ERROR(rc,IO_DCCAL_OFFCAL_ERROR_RC); return rc; } // Check for errors - else if ( timeoutCnt >= 5000 && !done && !fail ) + else if ( timeoutCnt >=100 && !done && !fail ) { FAPI_ERR("Timed out waiting for Done bit to be set"); //Set HWP error + int &TIMEOUTCNT=timeoutCnt; FAPI_SET_HWP_ERROR(rc,IO_DCCAL_OFFCAL_TIMEOUT_RC); return rc; } else { - FAPI_DBG("IO Offset cal Completed on interface %d",chip_interface); + FAPI_DBG("IO Offset cal Completed on interface %d with timeoutcount %d",chip_interface,timeoutCnt); } // clear eye opt offset cal done bit, rx_eo_latch_offset_done - rc=GCR_read(*target_ptr,chip_interface,rx_eo_step_stat_pg,group,0,set_bits); if (rc) {return(rc);}// have to add support for field parsing + rc=GCR_read(*target_ptr,chip_interface,rx_eo_step_stat_pg,group,0,set_bits); + if (rc) + { + // have to add support for field parsing + FAPI_ERR("IO_DCCAL : error GCR_read rx_eo_step_stat_pg"); + return rc; + } rc_ecmd|=set_bits.clearBit(0); bits=rx_eo_latch_offset_done_clear; rc_ecmd|=clear_bits.insert(bits,0,16); if(rc_ecmd) { + FAPI_ERR("IO_DCCAL : error in set and clear bits for GCR_write rx_eo_step_stat_pg"); rc.setEcmdError(rc_ecmd); return(rc); } @@ -328,15 +453,15 @@ ReturnCode run_offset_cal(const Target &target,io_interface_t master_interface,u //bits=rx_wt_timeout_value; bits=rx_wt_timeout_sel_tap3; - set_bits.insert(rx_wt_timeout_sel_buf,0,16); + rc_ecmd|=set_bits.insert(rx_wt_timeout_sel_buf,0,16); //rc_ecmd |= set_bits.setAnd(bits,9,3); // if(target.getType() != fapi::TARGET_TYPE_MEMBUF_CHIP){ // rc_ecmd|=set_bits.insert(bits,9,3); // } // else //rc_ecmd |= set_bits.clearBit(9); - bits=rx_wt_timeout_sel_clear; - rc_ecmd|=clear_bits.insert(bits,0,16); + // -- bits=rx_wt_timeout_sel_clear; + rc_ecmd|=clear_bits.flushTo0(); if(rc_ecmd) { rc.setEcmdError(rc_ecmd); @@ -370,7 +495,7 @@ ReturnCode run_zcal_debug(const Target& target,io_interface_t interface,uint32_t ecmdDataBufferBase data_buffer(16); rc=GCR_read(target,interface,tx_impcal_nval_pb,group,0,data_buffer);if (rc) {return(rc);} // have to add support for field parsing rc=GCR_read(target,interface,tx_impcal_pval_pb,group,0,data_buffer);if (rc) {return(rc);} // have to add support for field parsing - rc=GCR_read(target,interface,tx_impcal_p_4x_pb,group,0,data_buffer);if (rc) {return(rc);} // have to add support for field parsing + rc=GCR_read(target,interface,tx_impcal_p_4x_pb,group,0,data_buffer);if (rc) {return(rc);} // have to add support for field parsing return rc; } @@ -385,8 +510,11 @@ ReturnCode run_zcal(const Target& target,io_interface_t master_interface,uint32_ ecmdDataBufferBase set_bits(16); ecmdDataBufferBase clear_bits(16); ecmdDataBufferBase data_buffer(16); - rc_ecmd|=set_bits.flushTo0(); + rc_ecmd=set_bits.flushTo0(); rc_ecmd|=clear_bits.flushTo1(); // I dont want to clear anything by default + const fapi::Target &TARGET=target; + const uint32_t& K2 = k2; + const uint32_t& M = m; if(rc_ecmd) { rc.setEcmdError(rc_ecmd); @@ -394,14 +522,6 @@ ReturnCode run_zcal(const Target& target,io_interface_t master_interface,uint32_ } io_interface_t chip_interface=master_interface;//first we run on master chip uint32_t group=master_group; - // Get all the input attributes from PLAT - /* - Need to check if these attributes are required or not - rc = FAPI_ATTR_GET(ATTR_IOD_MARGIN_RATIO, &target, m); // Fetch the attribute for the chip we are working on - rc = FAPI_ATTR_GET(ATTR_IOD_POST_CURSOR_DRIVER_RATIO, &target, k2); - // Find if we are in SW_OVERRIDE mode - rc = FAPI_ATTR_GET(ATTR_IOD_ZCAL_SW_OVERRIDE, &target, swOverride); - */ const uint32_t min = (10<<3); // impcntl min - - p8 - 10<<3 const uint32_t max = (40<<3); // impcntl max - - p8 - 40<<3 @@ -427,12 +547,7 @@ ReturnCode run_zcal(const Target& target,io_interface_t master_interface,uint32_ FAPI_SET_HWP_ERROR(rc,IO_DCCAL_ZCAL_M_EXCEEDED_RC); return rc; } - - //if ( m < 0x40 ) { - // FAPI_DBG("MARGIN RATIO m is less than 50 percent"); - // FAPI_SET_HWP_ERROR(rc,IO_DCCAL_ZCAL_M_LOW_RC); - // return rc; - //} + if ( ( ! zcal_override ) && ( ! swOverride ) ) { @@ -475,6 +590,8 @@ ReturnCode run_zcal(const Target& target,io_interface_t master_interface,uint32_ FAPI_DBG("IO Impedance cal error on interface %d ",chip_interface); run_zcal_debug(*target_ptr,chip_interface,group); //set HWP error + ecmdDataBufferBase& DATA_BUFFER=data_buffer; + bool &FAIL=fail; FAPI_SET_HWP_ERROR(rc,IO_DCCAL_ZCAL_ERROR_RC); return(rc); @@ -484,6 +601,7 @@ ReturnCode run_zcal(const Target& target,io_interface_t master_interface,uint32_ { FAPI_DBG("Timed out waiting for Done bit to be set"); //set HWP error + int &TIMEOUTCNT=timeoutCnt; FAPI_SET_HWP_ERROR(rc,IO_DCCAL_ZCAL_TIMEOUT_RC); return rc; } @@ -511,12 +629,19 @@ ReturnCode run_zcal(const Target& target,io_interface_t master_interface,uint32_ if ( ( (uint32_t)zcal_n < min )|| ( (uint32_t)zcal_n > max ) ) { FAPI_ERR("zcal_n value is out of impcntl range"); + uint32_t &ZCAL_N=zcal_n; + const uint32_t &MIN=min; + const uint32_t &MAX=max; + FAPI_SET_HWP_ERROR(rc, IO_DCCAL_ZCALN_VALUE_OUT_OF_RANGE_RC); return rc; } if ( ( (uint32_t)zcal_p < min )|| ( (uint32_t)zcal_p > max ) ) { FAPI_ERR("zcal_p value is out of impcntl range"); + uint32_t &ZCAL_P=zcal_p; + const uint32_t &MIN=min; + const uint32_t &MAX=max; FAPI_SET_HWP_ERROR(rc, IO_DCCAL_ZCALP_VALUE_OUT_OF_RANGE_RC); return rc; } @@ -643,7 +768,7 @@ ReturnCode io_dccal(const Target& target){ fapi::Target parent_target; uint32_t ring_length=0; uint32_t rc_ecmd=0; - +const fapi::Target& TARGET = target; FAPI_DBG("Running IO DCCAL PROCEDURE"); // This is a DMI/MC bus diff --git a/src/usr/hwpf/hwp/bus_training/io_dccal_errors.xml b/src/usr/hwpf/hwp/bus_training/io_dccal_errors.xml new file mode 100644 index 000000000..7dfa3c325 --- /dev/null +++ b/src/usr/hwpf/hwp/bus_training/io_dccal_errors.xml @@ -0,0 +1,226 @@ +<!-- IBM_PROLOG_BEGIN_TAG --> +<!-- This is an automatically generated prolog. --> +<!-- --> +<!-- $Source: src/usr/hwpf/hwp/bus_training/io_dccal_errors.xml $ --> +<!-- --> +<!-- IBM CONFIDENTIAL --> +<!-- --> +<!-- COPYRIGHT International Business Machines Corp. 2014 --> +<!-- --> +<!-- p1 --> +<!-- --> +<!-- Object Code Only (OCO) source materials --> +<!-- Licensed Internal Code Source Materials --> +<!-- IBM HostBoot Licensed Internal Code --> +<!-- --> +<!-- The source code for this program is not published or otherwise --> +<!-- divested of its trade secrets, irrespective of what has been --> +<!-- deposited with the U.S. Copyright Office. --> +<!-- --> +<!-- Origin: 30 --> +<!-- --> +<!-- IBM_PROLOG_END_TAG --> +<!-- $Id: io_dccal_errors.xml,v 1.5 2014/03/18 14:58:40 jgrell Exp $ --> + +<!-- Error definitions for io_dccal HWPS --> +<hwpErrors> + <!-- *********************************************************************** --> + <hwpError> + <rc>IO_DCCAL_OFFCAL_ERROR_RC</rc> + <ffdc>CHIP_INTERFACE</ffdc> + <ffdc>DATA_BUFFER</ffdc> + <ffdc>FAIL_BIT</ffdc> + <ffdc>TARGET</ffdc> + <description>io offset cal errored out</description> + <callout> + <target>TARGET</target> + <priority>MEDIUM</priority> + </callout> + <callout> + <procedure>CODE</procedure> + <priority>LOW</priority> + </callout> + <deconfigure> + <target>TARGET</target> + </deconfigure> + <gard> + <target>TARGET</target> + </gard> + </hwpError> + <!-- *********************************************************************** --> + <hwpError> + <rc>IO_DCCAL_OFFCAL_TIMEOUT_RC</rc> + <ffdc>TIMEOUTCNT</ffdc> + <description>io offset cal timedout</description> + <callout> + <target>TARGET</target> + <priority>MEDIUM</priority> + </callout> + <callout> + <procedure>CODE</procedure> + <priority>LOW</priority> + </callout> + <deconfigure> + <target>TARGET</target> + </deconfigure> + <gard> + <target>TARGET</target> + </gard> + </hwpError> + <!-- *********************************************************************** --> + <hwpError> + <rc>IO_DCCAL_ZCAL_K2_EXCEEDED_RC</rc> + <ffdc>K2</ffdc> + <description>Post cursor drive ratio has exceeded 0.25</description> + <callout> + <target>TARGET</target> + <priority>MEDIUM</priority> + </callout> + <callout> + <procedure>CODE</procedure> + <priority>LOW</priority> + </callout> + <deconfigure> + <target>TARGET</target> + </deconfigure> + <gard> + <target>TARGET</target> + </gard> + </hwpError> + <!-- *********************************************************************** --> + <hwpError> + <rc>IO_DCCAL_ZCAL_M_EXCEEDED_RC</rc> + <ffdc>M</ffdc> + <callout> + <target>TARGET</target> + <priority>MEDIUM</priority> + </callout> + <callout> + <procedure>CODE</procedure> + <priority>LOW</priority> + </callout> + <deconfigure> + <target>TARGET</target> + </deconfigure> + <gard> + <target>TARGET</target> + </gard> + <description>Margin Ratio has exceeded 100 percentage</description> + </hwpError> + <!-- *********************************************************************** --> + <hwpError> + <rc>IO_DCCAL_ZCAL_ERROR_RC</rc> + <ffdc>FAIL</ffdc> + <ffdc>DATA_BUFFER</ffdc> + <description>io impedance cal errored out</description> + <callout> + <target>TARGET</target> + <priority>MEDIUM</priority> + </callout> + <callout> + <procedure>CODE</procedure> + <priority>LOW</priority> + </callout> + <deconfigure> + <target>TARGET</target> + </deconfigure> + <gard> + <target>TARGET</target> + </gard> + </hwpError> + <!-- *********************************************************************** --> + <hwpError> + <rc>IO_DCCAL_ZCAL_TIMEOUT_RC</rc> + <ffdc>TIMEOUTCNT</ffdc> + <description>io impedance cal timed out</description> + <callout> + <target>TARGET</target> + <priority>MEDIUM</priority> + </callout> + <callout> + <procedure>CODE</procedure> + <priority>LOW</priority> + </callout> + <deconfigure> + <target>TARGET</target> + </deconfigure> + <gard> + <target>TARGET</target> + </gard> + <callout> + <procedure>CODE</procedure> + <priority>HIGH</priority> + </callout> + </hwpError> + <!-- *********************************************************************** --> + <hwpError> + <rc>IO_DCCAL_ZCALN_VALUE_OUT_OF_RANGE_RC</rc> + <ffdc>ZCAL_N</ffdc> + <ffdc>MIN</ffdc> + <ffdc>MAX</ffdc> + <description>Impedance calibration zcal_n value out of range</description> + <callout> + <target>TARGET</target> + <priority>MEDIUM</priority> + </callout> + <callout> + <procedure>CODE</procedure> + <priority>LOW</priority> + </callout> + <deconfigure> + <target>TARGET</target> + </deconfigure> + <gard> + <target>TARGET</target> + </gard> + </hwpError> + <!-- *********************************************************************** --> + <hwpError> + <rc>IO_DCCAL_ZCALP_VALUE_OUT_OF_RANGE_RC</rc> + <ffdc>ZCAL_P</ffdc> + <ffdc>MIN</ffdc> + <ffdc>MAX</ffdc> + <description>Impedance calibration zcal_p value out of range</description> + <callout> + <target>TARGET</target> + <priority>MEDIUM</priority> + </callout> + <callout> + <procedure>CODE</procedure> + <priority>LOW</priority> + </callout> + <deconfigure> + <target>TARGET</target> + </deconfigure> + <gard> + <target>TARGET</target> + </gard> + </hwpError> + <!-- *********************************************************************** --> + <hwpError> + <rc>IO_DCCAL_INVALID_INVOCATION_RC</rc> + <ffdc>TARGET</ffdc> + <description>io dc cal invoked with wrong pair of targets</description> + <callout> + <procedure>CODE</procedure> + <priority>HIGH</priority> + </callout> + <callout> + <target>TARGET</target> + <priority>MEDIUM</priority> + </callout> + <callout> + <procedure>CODE</procedure> + <priority>LOW</priority> + </callout> + <deconfigure> + <target>TARGET</target> + </deconfigure> + <gard> + <target>TARGET</target> + </gard> + </hwpError> + +</hwpErrors> + + diff --git a/src/usr/hwpf/hwp/bus_training/io_errors.xml b/src/usr/hwpf/hwp/bus_training/io_errors.xml deleted file mode 100644 index c3e7f48df..000000000 --- a/src/usr/hwpf/hwp/bus_training/io_errors.xml +++ /dev/null @@ -1,244 +0,0 @@ -<!-- IBM_PROLOG_BEGIN_TAG --> -<!-- This is an automatically generated prolog. --> -<!-- --> -<!-- $Source: src/usr/hwpf/hwp/bus_training/io_errors.xml $ --> -<!-- --> -<!-- IBM CONFIDENTIAL --> -<!-- --> -<!-- COPYRIGHT International Business Machines Corp. 2012,2013 --> -<!-- --> -<!-- p1 --> -<!-- --> -<!-- Object Code Only (OCO) source materials --> -<!-- Licensed Internal Code Source Materials --> -<!-- IBM HostBoot Licensed Internal Code --> -<!-- --> -<!-- The source code for this program is not published or otherwise --> -<!-- divested of its trade secrets, irrespective of what has been --> -<!-- deposited with the U.S. Copyright Office. --> -<!-- --> -<!-- Origin: 30 --> -<!-- --> -<!-- IBM_PROLOG_END_TAG --> -<!-- $Id: io_errors.xml,v 1.12 2013/12/06 19:17:34 jgrell Exp $ --> -<!-- Error definitions for IO HWPS --> -<hwpErrors> - <!-- *********************************************************************** --> - <hwpError> - <rc>IO_RUN_TRAINING_INVALID_ARGS_RC</rc> - <description>Invalid or out-of-range argument value(s) presented to IO_RUN_TRAINING HWP.</description> - </hwpError> - <!-- *********************************************************************** --> - <hwpError> - <rc>IO_RUN_TRAINING_INTERNAL_ERR_RC</rc> - <description>Unexpected internal program logic error.</description> - </hwpError> - <!-- *********************************************************************** --> - <hwpError> - <rc>IO_RUN_TRAINING_FAIL_ERR_RC</rc> - <description>Training fail was reported in a P8 or Centaur status register</description> - </hwpError> - <!-- *********************************************************************** --> - <hwpError> - <rc>IO_RUN_TRAINING_FAIL_WIRETEST_RC</rc> - <description>Wiretest Training fail was reported in a P8 or Centaur status register</description> - </hwpError> - <!-- *********************************************************************** --> - <hwpError> - <rc>IO_RUN_TRAINING_FAIL_DESKEW_RC</rc> - <description>Deskew Training fail was reported in a P8 or Centaur status register</description> - </hwpError> - <!-- *********************************************************************** --> - <hwpError> - <rc>IO_RUN_TRAINING_FAIL_EYE_OPT_RC</rc> - <description>Eye Optimization Training fail was reported in a P8 or Centaur status register</description> - </hwpError> - <!-- *********************************************************************** --> - <hwpError> - <rc>IO_RUN_TRAINING_FAIL_REPAIR_RC</rc> - <description>Static Repair Training fail was reported in a P8 or Centaur status register</description> - </hwpError> - <!-- *********************************************************************** --> - <hwpError> - <rc>IO_RUN_TRAINING_FAIL_FUNC_MODE_RC</rc> - <description>Functional mode Training fail was reported in a P8 or Centaur status register</description> - </hwpError> - <!-- *********************************************************************** --> - <hwpError> - <rc>IO_RUN_TRAINING_WIRETEST_TIMEOUT_RC</rc> - <ffdc>FFDC_NUM_CYCLES</ffdc> - <description>io run training wiretest timed out waiting for pass/fail indication in the p8 or centaur Status Registers</description> - </hwpError> - <!-- *********************************************************************** --> - <hwpError> - <rc>IO_RUN_TRAINING_DESKEW_TIMEOUT_RC</rc> - <ffdc>FFDC_NUM_CYCLES</ffdc> - <description>io run training deskew timed out waiting for pass/fail indication in the p8 or centaur Status Registers</description> - </hwpError> - <!-- *********************************************************************** --> - <hwpError> - <rc>IO_RUN_TRAINING_EYE_OPT_TIMEOUT_RC</rc> - <ffdc>FFDC_NUM_CYCLES</ffdc> - <description>io run training eye opt timed out waiting for pass/fail indication in the p8 or centaur Status Registers</description> - </hwpError> - <!-- *********************************************************************** --> - <hwpError> - <rc>IO_RUN_TRAINING_REPAIR_TIMEOUT_RC</rc> - <ffdc>FFDC_NUM_CYCLES</ffdc> - <description>io run training repair timed out waiting for pass/fail indication in the p8 or centaur Status Registers</description> - </hwpError> - <!-- *********************************************************************** --> - <hwpError> - <rc>IO_RUN_TRAINING_FUNC_MODE_TIMEOUT_RC</rc> - <ffdc>FFDC_NUM_CYCLES</ffdc> - <description>io run training functional mode timed out waiting for pass/fail indication in the p8 or centaur Status Registers</description> - </hwpError> - <!-- *********************************************************************** --> - <hwpError> - <rc>IO_GCR_WRITE_MISMATCH_RC</rc> - <description>IO GCR write operation failed to readback data that was written</description> - <ffdc>READ_BUF</ffdc> - <ffdc>WRITE_BUF</ffdc> - </hwpError> - <!-- *********************************************************************** --> - <hwpError> - <rc>IO_RUN_TRAINING_DLL_WORKAROUND_FAIL</rc> - <description>DLL Workaround failed to arrive at a solution</description> - </hwpError> - <!-- *********************************************************************** --> - <hwpError> - <rc>IO_RUN_TRAINING_DLL_VAL_OUT_OF_BOUND_RC</rc> - <description>DLL Workaround encountered unexpected start value</description> - </hwpError> - <!-- *********************************************************************** --> - <hwpError> - <rc>IO_RUN_TRAINING_INVALID_INVOCATION_RC</rc> - <description>io run training invoked with wrong pair of targets</description> - </hwpError> - <!-- *********************************************************************** --> - <hwpError> - <rc>IO_DCCAL_OFFCAL_TIMEOUT_RC</rc> - <description>io offset cal timedout</description> - </hwpError> - <!-- *********************************************************************** --> - <hwpError> - <rc>IO_DCCAL_OFFCAL_ERROR_RC</rc> - <description>io offset cal errored out</description> - </hwpError> - <!-- *********************************************************************** --> - <hwpError> - <rc>IO_DCCAL_INVALID_INVOCATION_RC</rc> - <description>io dc cal invoked with wrong pair of targets</description> - </hwpError> - <!-- *********************************************************************** --> - <hwpError> - <rc>IO_DCCAL_ZCAL_ERROR_RC</rc> - <description>io impedance cal errored out</description> - </hwpError> - <!-- *********************************************************************** --> - <hwpError> - <rc>IO_DCCAL_ZCAL_TIMEOUT_RC</rc> - <description>io impedance cal timed out</description> - </hwpError> - <!-- *********************************************************************** --> - <hwpError> - <rc>IO_DCCAL_ZCALN_VALUE_OUT_OF_RANGE_RC</rc> - <description>Impedance calibration zcal_n value out of range</description> - </hwpError> - <!-- *********************************************************************** --> - <hwpError> - <rc>IO_DCCAL_ZCALP_VALUE_OUT_OF_RANGE_RC</rc> - <description>Impedance calibration zcal_p value out of range</description> - </hwpError> - <!-- *********************************************************************** --> - <hwpError> - <rc>IO_DCCAL_ZCAL_K2_EXCEEDED_RC</rc> - <description>Post cursor drive ratio has exceeded 0.25</description> - </hwpError> - <!-- *********************************************************************** --> - <hwpError> - <rc>IO_DCCAL_ZCAL_M_EXCEEDED_RC</rc> - <description>Margin Ratio has exceeded 100 percentage</description> - </hwpError> - <!-- *********************************************************************** --> - <hwpError> - <rc>IO_DCCAL_ZCAL_M_LOW_RC</rc> - <description>Margin Ratio is less than 50 percent</description> - </hwpError> - <!-- *********************************************************************** --> - <hwpError> - <rc>IO_CLEAR_FIRS_INVALID_INVOCATION_RC</rc> - <description>io clear firs hwp invoked with wrong pair of targets</description> - </hwpError> - <!-- *********************************************************************** --> - <hwpError> - <rc>IO_FIR_LANE_RX_PARITY_ERROR_RC</rc> - <description>io lane level rx parity error set</description> - <ffdc>CHIP_TARGET</ffdc> - <ffdc>LANE_ID</ffdc> - <ffdc>RX_ERROR_REG</ffdc> - </hwpError> - <!-- *********************************************************************** --> - <hwpError> - <rc>IO_FIR_GROUP_RX_PARITY_ERROR_RC</rc> - <description>io group level rx parity error set</description> - <ffdc>CHIP_TARGET</ffdc> - <ffdc>RX_ERROR_REG</ffdc> - </hwpError> - <!-- *********************************************************************** --> - <hwpError> - <rc>IO_FIR_BUS_RX_PARITY_ERROR_RC</rc> - <description>io bus level rx parity error set</description> - <ffdc>CHIP_TARGET</ffdc> - <ffdc>RX_ERROR_REG</ffdc> - </hwpError> - <!-- *********************************************************************** --> - <hwpError> - <rc>IO_FIR_LANE_TX_PARITY_ERROR_RC</rc> - <description>io lane level tx parity error set</description> - <ffdc>CHIP_TARGET</ffdc> - <ffdc>LANE_ID</ffdc> - <ffdc>TX_ERROR_REG</ffdc> - </hwpError> - <!-- *********************************************************************** --> - <hwpError> - <rc>IO_FIR_GROUP_TX_PARITY_ERROR_RC</rc> - <description>io group level tx parity error set</description> - <ffdc>CHIP_TARGET</ffdc> - <ffdc>TX_ERROR_REG</ffdc> - </hwpError> - <!-- *********************************************************************** --> - <hwpError> - <rc>IO_FIR_SPARES_DEPLOYED_FIR_RC</rc> - <description>A spare has been deployed</description> - <ffdc>CHIP_TARGET</ffdc> - <ffdc>SPARE_ERROR_REG</ffdc> - </hwpError> - <!-- *********************************************************************** --> - <hwpError> - <rc>IO_FIR_MAX_SPARES_EXCEEDED_FIR_RC</rc> - <description>maximum spares possible to deploy exceeded</description> - <ffdc>CHIP_TARGET</ffdc> - <ffdc>SPARE_ERROR_REG</ffdc> - </hwpError> - <!-- *********************************************************************** --> - <hwpError> - <rc>IO_FIR_GCR_HANG_ERROR_RC</rc> - <description>gcr hang error detected</description> - <ffdc>CHIP_TARGET</ffdc> - </hwpError> - <!-- *********************************************************************** --> - <hwpError> - <rc>IO_FIR_RECALIBRATION_ERROR_RC</rc> - <description>recalibration or a repair error has been detected</description> - <ffdc>CHIP_TARGET</ffdc> - <ffdc>RECAL_ERROR_REG</ffdc> - </hwpError> - <!-- *********************************************************************** --> - <hwpError> - <rc>IO_FIR_TOO_MANY_BUS_ERROR_RC</rc> - <description>A bus has experienced too many random lane errors</description> - <ffdc>CHIP_TARGET</ffdc> - <ffdc>BUS_ERROR_REG</ffdc> - </hwpError> -</hwpErrors> diff --git a/src/usr/hwpf/hwp/bus_training/io_fir_isolation.C b/src/usr/hwpf/hwp/bus_training/io_fir_isolation.C index 5c19acaf2..d14737bf3 100644 --- a/src/usr/hwpf/hwp/bus_training/io_fir_isolation.C +++ b/src/usr/hwpf/hwp/bus_training/io_fir_isolation.C @@ -5,7 +5,7 @@ /* */ /* IBM CONFIDENTIAL */ /* */ -/* COPYRIGHT International Business Machines Corp. 2013 */ +/* COPYRIGHT International Business Machines Corp. 2013,2014 */ /* */ /* p1 */ /* */ @@ -20,16 +20,16 @@ /* Origin: 30 */ /* */ /* IBM_PROLOG_END_TAG */ -// $Id: io_fir_isolation.C,v 1.11 2013/11/13 10:50:44 jaswamin Exp $ +// $Id: io_fir_isolation.C,v 1.14 2014/03/20 14:06:08 varkeykv Exp $ // *!*************************************************************************** // *! (C) Copyright International Business Machines Corp. 2012 , 2013 // *! All Rights Reserved -- Property of IBM // *! *** IBM Confidential *** // *!*************************************************************************** // *! FILENAME : io_fir_isolation.C -// *! TITLE : +// *! TITLE : // *! DESCRIPTION : To isolate the error causing the firs to flag -// *! CONTEXT : +// *! CONTEXT : // *! // *! OWNER NAME : Swaminathan, Janani Email: jaswamin@in.ibm.com // *! BACKUP NAME : Varghese, Varkey Email: varkey.kv@in.ibm.com @@ -40,14 +40,14 @@ // Version:|Author: | Date: | Comment: // --------|--------|--------|-------------------------------------------------- // 1.9 |jaswamin|04/19/13| Fixes for firmware compile issues. -// 1.8 |jaswamin|03/22/13| Added comments +// 1.8 |jaswamin|03/22/13| Added comments // 1.7 |jaswamin|03/18/13| Changed indentation // 1.6 |jaswamin|03/13/13| Returncode logging // 1.5 |jaswamin|03/12/13| Return in case of a gcr operation error. // 1.4 |jaswamin|03/06/13| Removed commented out portion. // 1.3 |jaswamin|03/04/13| Changes as per review comment. // 1.2 |jaswamin|02/20/13| Changes as per review comment -// 1.1 |jaswamin|02/14/13| Initial check in . +// 1.1 |jaswamin|02/14/13| Initial check in . //------------------------------------------------------------------------------ #include <fapi.H> @@ -60,7 +60,6 @@ extern "C" { using namespace fapi; - //! Function : io_fir_too_many_bus_err_isolation //! Parameters : i_target => FAPI target, //! chip_interface => io_chip_interface viz., A, X, DMI, CEN @@ -73,23 +72,20 @@ using namespace fapi; ReturnCode io_fir_too_many_bus_err_isolation(const fapi::Target &i_target, io_interface_t i_chip_interface, uint32_t i_current_group){ - + ReturnCode o_rc; ecmdDataBufferBase error_data(16); - //uint32_t bitPos=0x0080; - - + o_rc=GCR_read(i_target , i_chip_interface, rx_fir_training_pg, i_current_group,0, error_data); if(o_rc) return o_rc; if(error_data.isBitSet(8,1)){ - //error_data.setAnd(bitPos,0,16); ecmdDataBufferBase & BUS_ERROR_REG = error_data; //bit1 of the register represnts the spare deployed bit. - const fapi::Target & CHIP_TARGET= i_target; + const fapi::Target & ENDPOINT = i_target; FAPI_SET_HWP_ERROR(o_rc,IO_FIR_TOO_MANY_BUS_ERROR_RC); fapiLogError(o_rc,FAPI_ERRL_SEV_UNRECOVERABLE); } - return(FAPI_RC_SUCCESS); + return(FAPI_RC_SUCCESS); } //! Function : io_fir_recal_error_isolation @@ -105,18 +101,16 @@ ReturnCode io_fir_too_many_bus_err_isolation(const fapi::Target &i_target, ReturnCode io_fir_recal_error_isolation(const fapi::Target &i_target, io_interface_t i_chip_interface, uint32_t i_current_group){ - + ReturnCode o_rc; ecmdDataBufferBase error_data(16); - //uint32_t bitPos=0x1200; - + o_rc=GCR_read(i_target , i_chip_interface, rx_fir_training_pg, i_current_group,0, error_data); if(o_rc) return o_rc; if(error_data.isBitSet(3,1) || error_data.isBitSet(6,1)){ //can be caused by dynamic repair or recal error (bits 3 and 6 respectively) - //error_data.setAnd(bitPos,0,16); ecmdDataBufferBase & RECAL_ERROR_REG = error_data ; //bit1 of the register represnts the spare deployed bit. - const fapi::Target & CHIP_TARGET= i_target; + const fapi::Target & ENDPOINT = i_target; FAPI_SET_HWP_ERROR(o_rc,IO_FIR_RECALIBRATION_ERROR_RC); fapiLogError(o_rc,FAPI_ERRL_SEV_RECOVERED); } @@ -131,23 +125,21 @@ ReturnCode io_fir_recal_error_isolation(const fapi::Target &i_target, //! This includes the target details and the source of the error. //! Description : This function collects the register contents of the training register //! that would help root cause the error as being from pre/during training, - //! post training or during recal that caused the spares to exceed. + //! post training or during recal that caused the spares to exceed. //! This is provided as FFDC dump. ReturnCode io_fir_max_spares_exceeded_isolation(const fapi::Target &i_target, io_interface_t i_chip_interface, uint32_t i_current_group){ - + ReturnCode o_rc; ecmdDataBufferBase error_data(16); - //uint32_t bitPos=0x2680; - + o_rc=GCR_read(i_target , i_chip_interface, rx_fir_training_pg, i_current_group,0, error_data); if(o_rc) return o_rc; if(error_data.isBitSet(2,1) || error_data.isBitSet(5,1)|| error_data.isBitSet(8,1)){ // can be caused by a static (pre training - bit 2) or dynamic (post training - bit 5) or recal(bit 8) - //error_data.setAnd(bitPos,0,16); ecmdDataBufferBase & SPARE_ERROR_REG = error_data; //bit2 /bit 5 /bit 8of the register represents the max spare exceeded bit.To determine what caused the max spares exceeded error - const fapi::Target & CHIP_TARGET= i_target; + const fapi::Target & ENDPOINT = i_target; FAPI_SET_HWP_ERROR(o_rc,IO_FIR_MAX_SPARES_EXCEEDED_FIR_RC); fapiLogError(o_rc,FAPI_ERRL_SEV_UNRECOVERABLE); } @@ -167,18 +159,16 @@ ReturnCode io_fir_max_spares_exceeded_isolation(const fapi::Target &i_target, ReturnCode io_fir_spare_deployed_isolation(const fapi::Target &i_target, io_interface_t i_chip_interface, uint32_t i_current_group){ - + ReturnCode o_rc; ecmdDataBufferBase error_data(16); - //uint32_t bitPos=0x6900; - + o_rc=GCR_read(i_target , i_chip_interface, rx_fir_training_pg, i_current_group,0, error_data); if(o_rc) return o_rc; if(error_data.isBitSet(1,1) || error_data.isBitSet(4,1) || error_data.isBitSet(7,1)){ // can be caused by a spare deployment prior to training , post training or during recal - //error_data.setAnd(bitPos,0,16); ecmdDataBufferBase & SPARE_ERROR_REG = error_data; //bit1 /bit4 / bit 7 of the register represnts the spare deployed bit. To determine which type of error caused the spare to be deployed - const fapi::Target & CHIP_TARGET= i_target; + const fapi::Target & ENDPOINT = i_target; FAPI_SET_HWP_ERROR(o_rc,IO_FIR_SPARES_DEPLOYED_FIR_RC); fapiLogError(o_rc,FAPI_ERRL_SEV_RECOVERED); } @@ -194,16 +184,16 @@ ReturnCode io_fir_spare_deployed_isolation(const fapi::Target &i_target, //! and the lane id if it is a lane level error. //! Description : This function collects the register contents that would help //! determine the source of the parity error and provides it as a FFDC data dump. - + ReturnCode io_fir_tx_parity_isolation(const fapi::Target &i_target, io_interface_t i_chip_interface, uint32_t i_current_group){ - + ReturnCode o_rc; ecmdDataBufferBase error_data(16); - uint32_t loop_val=0; + uint32_t loop_val=0; uint32_t lane,group; - + if(i_chip_interface==CP_FABRIC_X0){ lane=77; } @@ -216,16 +206,16 @@ ReturnCode io_fir_tx_parity_isolation(const fapi::Target &i_target, else{ lane=24; } - + for(loop_val=0;loop_val<lane;loop_val++){ - + if(i_chip_interface==CP_FABRIC_X0){ group=loop_val%20; } else{ group=i_current_group; } - + o_rc=GCR_read(i_target , i_chip_interface, tx_fir_pl, group,loop_val, error_data); if(o_rc){ FAPI_ERR("io_fir_isolation: Error reading rx fir per lane register\n"); @@ -233,35 +223,37 @@ ReturnCode io_fir_tx_parity_isolation(const fapi::Target &i_target, } //bit 0 for rx_fir_pl in case of X and bit 0 and 1 for A and DMI if(error_data.isBitSet(0,1)){ - + // find the current lane and group to send information - + uint32_t & LANE_ID = loop_val; ecmdDataBufferBase & TX_ERROR_REG = error_data; - const fapi::Target & CHIP_TARGET= i_target; + const fapi::Target & ENDPOINT = i_target; FAPI_DBG("io_fir_rx_parity_isolation:A per lane register or state machine error has occured. Lane is %d\n",loop_val); FAPI_SET_HWP_ERROR(o_rc,IO_FIR_LANE_TX_PARITY_ERROR_RC); fapiLogError(o_rc,FAPI_ERRL_SEV_RECOVERED); + break; } } - - + + o_rc=GCR_read(i_target ,i_chip_interface, tx_fir_pg, i_current_group,0, error_data); if(o_rc) return o_rc; for(loop_val=0;loop_val<16;loop_val++){ - + if(error_data.isBitSet(loop_val,1)){ - + ecmdDataBufferBase & TX_ERROR_REG = error_data; - const fapi::Target & CHIP_TARGET= i_target; + const fapi::Target & ENDPOINT = i_target; FAPI_SET_HWP_ERROR(o_rc,IO_FIR_GROUP_TX_PARITY_ERROR_RC); fapiLogError(o_rc,FAPI_ERRL_SEV_RECOVERED); + break; } } - + return(FAPI_RC_SUCCESS); - + } //! Function : io_fir_rx_parity_isolation @@ -276,13 +268,13 @@ ReturnCode io_fir_tx_parity_isolation(const fapi::Target &i_target, ReturnCode io_fir_rx_parity_isolation(const fapi::Target &i_target, io_interface_t i_chip_interface, uint32_t i_current_group){ - - + + ReturnCode o_rc; ecmdDataBufferBase error_data(16); uint32_t loop_val=0; uint32_t lane,group; - + //in case its bit 0 it is the rx_parity error. To find which bit is set read the registers that contribute to it. This is a per lane register. Hence we need to loop through each //lane to determine which is erroring out. if(i_chip_interface==CP_FABRIC_X0){ @@ -297,80 +289,82 @@ ReturnCode io_fir_rx_parity_isolation(const fapi::Target &i_target, else{ lane=17; } - + for(loop_val=0;loop_val<lane;loop_val++){ - + if(i_chip_interface==CP_FABRIC_X0){ group=loop_val%20; } else{ group=i_current_group; } - + o_rc=GCR_read(i_target , i_chip_interface, rx_fir_pl, group,loop_val, error_data); - + if(o_rc){ FAPI_DBG("io_fir_isolation: Error reading rx fir per lane register\n"); return(o_rc); } //bit 0 for rx_fir_pl in case of X and bit 0 and 1 for A and DMI if(error_data.isBitSet(0,1) || error_data.isBitSet(1,1)){ - - + + // find the current lane and group to send information uint32_t & LANE_ID = loop_val; ecmdDataBufferBase & RX_ERROR_REG = error_data; - const fapi::Target & CHIP_TARGET= i_target; + const fapi::Target & ENDPOINT = i_target; FAPI_DBG("io_fir_rx_parity_isolation:A per lane register or state machine error has occured. Lane is %d\n",loop_val); FAPI_SET_HWP_ERROR(o_rc,IO_FIR_LANE_RX_PARITY_ERROR_RC); fapiLogError(o_rc,FAPI_ERRL_SEV_RECOVERED); + break; } } - + //for fir1_reg and fir2_reg it is group wise hence do not need lane information - + o_rc=GCR_read(i_target ,i_chip_interface, rx_fir1_pg, i_current_group,0, error_data); if(o_rc) return o_rc; for(loop_val=0;loop_val<16;loop_val++){ - + if(error_data.isBitSet(loop_val,1)){ ecmdDataBufferBase & RX_ERROR_REG = error_data; - const fapi::Target & CHIP_TARGET= i_target; + const fapi::Target & ENDPOINT = i_target; FAPI_DBG("io_fir_isolation: %s\n",fir1_reg[loop_val]); FAPI_SET_HWP_ERROR(o_rc,IO_FIR_GROUP_RX_PARITY_ERROR_RC); fapiLogError(o_rc,FAPI_ERRL_SEV_RECOVERED); - + break; } } - - + + o_rc=GCR_read(i_target , i_chip_interface, rx_fir2_pg, i_current_group,0, error_data); if(o_rc) return o_rc; for(loop_val=0;loop_val<16;loop_val++){ - + if(error_data.isBitSet(loop_val,1)){ ecmdDataBufferBase & RX_ERROR_REG = error_data; - const fapi::Target & CHIP_TARGET= i_target; + const fapi::Target & ENDPOINT = i_target; FAPI_DBG("io_fir_isolation: %s\n",fir2_reg[loop_val]); FAPI_SET_HWP_ERROR(o_rc,IO_FIR_GROUP_RX_PARITY_ERROR_RC); fapiLogError(o_rc,FAPI_ERRL_SEV_RECOVERED); - + break; } } - - + + o_rc=GCR_read(i_target,i_chip_interface,rx_fir_pb,i_current_group,0,error_data); if(o_rc) return o_rc; for(loop_val=0;loop_val<16;loop_val++){ - + if(error_data.isBitSet(loop_val,1)){ ecmdDataBufferBase & RX_ERROR_REG = error_data; - const fapi::Target & CHIP_TARGET= i_target; + const fapi::Target & ENDPOINT = i_target; FAPI_SET_HWP_ERROR(o_rc,IO_FIR_BUS_RX_PARITY_ERROR_RC); fapiLogError(o_rc,FAPI_ERRL_SEV_RECOVERED); + break; } } return(FAPI_RC_SUCCESS); @@ -389,99 +383,99 @@ ReturnCode io_error_isolation(const fapi::Target &i_target, io_interface_t i_chip_interface, uint32_t i_current_group, ecmdDataBufferBase &i_fir_data){ - + ReturnCode o_rc; //ecmdDataBufferBase error_data(16),id_data(16); - - + + //need to determine what error it represents. - + //if it is a rx_parity error - if(i_fir_data.isBitSet(RX_PARITY,1)){ + if(i_fir_data.isBitSet(RX_PARITY,1)){ o_rc=io_fir_rx_parity_isolation(i_target,i_chip_interface,i_current_group); if(o_rc) return(o_rc); } - + //check for tx_parity error if(i_fir_data.isBitSet(TX_PARITY,1)){ - + o_rc=io_fir_tx_parity_isolation(i_target,i_chip_interface,i_current_group); if(o_rc) return(o_rc); } - + //GCR hang error - if(i_fir_data.isBitSet(GCR_HANG_ERROR,1)){ + if(i_fir_data.isBitSet(GCR_HANG_ERROR,1)){ //check whether the gcr hang error bit is set - - - const fapi::Target & CHIP_TARGET= i_target; + + + const fapi::Target & ENDPOINT = i_target; FAPI_SET_HWP_ERROR(o_rc,IO_FIR_GCR_HANG_ERROR_RC); fapiLogError(o_rc,FAPI_ERRL_SEV_UNRECOVERABLE); //since the logging of error needs to happen here for this error. - - + + } - - //spare deploy? + + //spare deploy? if(i_fir_data.isBitSet(BUS0_SPARE_DEPLOYED,1) || i_fir_data.isBitSet(BUS1_SPARE_DEPLOYED,1) || i_fir_data.isBitSet(BUS2_SPARE_DEPLOYED,1) || i_fir_data.isBitSet(BUS3_SPARE_DEPLOYED,1) || - i_fir_data.isBitSet(BUS4_SPARE_DEPLOYED,1) ){ - + i_fir_data.isBitSet(BUS4_SPARE_DEPLOYED,1) ){ + o_rc=io_fir_spare_deployed_isolation(i_target,i_chip_interface,i_current_group); if(o_rc) return(o_rc); - - + + } - - //maximum spares deployed and exceeded? + + //maximum spares deployed and exceeded? if(i_fir_data.isBitSet(BUS0_MAX_SPARES_EXCEEDED,1) || i_fir_data.isBitSet(BUS1_MAX_SPARES_EXCEEDED,1) || i_fir_data.isBitSet(BUS2_MAX_SPARES_EXCEEDED,1) || i_fir_data.isBitSet(BUS3_MAX_SPARES_EXCEEDED,1) || - i_fir_data.isBitSet(BUS4_MAX_SPARES_EXCEEDED,1)){ - + i_fir_data.isBitSet(BUS4_MAX_SPARES_EXCEEDED,1)){ + o_rc=io_fir_max_spares_exceeded_isolation(i_target,i_chip_interface,i_current_group); if(o_rc) return(o_rc); - + } - - //recalibration error + + //recalibration error if(i_fir_data.isBitSet(BUS0_RECALIBRATION_ERROR,1) || i_fir_data.isBitSet(BUS1_RECALIBRATION_ERROR,1) || i_fir_data.isBitSet(BUS2_RECALIBRATION_ERROR,1) || i_fir_data.isBitSet(BUS3_RECALIBRATION_ERROR,1) || - i_fir_data.isBitSet(BUS4_RECALIBRATION_ERROR,1)){ - - + i_fir_data.isBitSet(BUS4_RECALIBRATION_ERROR,1)){ + + o_rc=io_fir_recal_error_isolation(i_target,i_chip_interface,i_current_group); if(o_rc) return(o_rc); - + } - + //too many bus errors if(i_fir_data.isBitSet(BUS0_TOO_MANY_BUS_ERRORS,1) || i_fir_data.isBitSet(BUS1_TOO_MANY_BUS_ERRORS,1) || i_fir_data.isBitSet(BUS2_TOO_MANY_BUS_ERRORS,1) || i_fir_data.isBitSet(BUS3_TOO_MANY_BUS_ERRORS,1) || - i_fir_data.isBitSet(BUS4_TOO_MANY_BUS_ERRORS,1)){ - + i_fir_data.isBitSet(BUS4_TOO_MANY_BUS_ERRORS,1)){ + o_rc=io_fir_too_many_bus_err_isolation(i_target,i_chip_interface,i_current_group); if(o_rc) return(o_rc); - + } - + return(FAPI_RC_SUCCESS); // Currently this does not cause any harm as you are returning all the errors in the middle of the function, but it is good to change this to "return(o_r)". } ReturnCode io_fir_isolation(const fapi::Target &i_target){ - + ReturnCode o_rc; uint32_t rc_ecmd=0; fir_io_interface_t interface; @@ -489,8 +483,12 @@ ReturnCode io_fir_isolation(const fapi::Target &i_target){ uint32_t group; ecmdDataBufferBase fir_data(64); rc_ecmd|=fir_data.flushTo0(); - //rc_ecmd|=fir_data.setBitLength(64); - + if(rc_ecmd) + { + o_rc.setEcmdError(rc_ecmd); + return(o_rc); + } + //on dmi if( (i_target.getType() == fapi::TARGET_TYPE_MCS_CHIPLET )){ FAPI_DBG("This is a Processor DMI bus using base DMI scom address"); @@ -501,7 +499,7 @@ ReturnCode io_fir_isolation(const fapi::Target &i_target){ if(o_rc) return(o_rc); o_rc=io_error_isolation(i_target,gcr_interface,group,fir_data); - + } //on cen side else if((i_target.getType() == fapi::TARGET_TYPE_MEMBUF_CHIP)){ @@ -513,7 +511,7 @@ ReturnCode io_fir_isolation(const fapi::Target &i_target){ if(o_rc) return(o_rc); o_rc=io_error_isolation(i_target,gcr_interface,group,fir_data); - + } // on x bus else if((i_target.getType() == fapi::TARGET_TYPE_XBUS_ENDPOINT)){ @@ -525,7 +523,7 @@ ReturnCode io_fir_isolation(const fapi::Target &i_target){ if(o_rc) return(o_rc); o_rc=io_error_isolation(i_target,gcr_interface,group,fir_data); - + } //on a bus else if((i_target.getType() == fapi::TARGET_TYPE_ABUS_ENDPOINT)){ @@ -537,19 +535,18 @@ ReturnCode io_fir_isolation(const fapi::Target &i_target){ if(o_rc) return(o_rc); o_rc=io_error_isolation(i_target,gcr_interface,group,fir_data); - + } else{ - FAPI_ERR("Invalid io_clear_firs HWP invocation . Target doesnt belong to DMI/X/A instances"); - FAPI_SET_HWP_ERROR(o_rc, IO_CLEAR_FIRS_INVALID_INVOCATION_RC); + FAPI_ERR("Invalid io_fir HWP invocation . Target doesnt belong to DMI/X/A instances"); + const fapi::Target & ENDPOINT = i_target; + FAPI_SET_HWP_ERROR(o_rc, IO_FIR_INVALID_INVOCATION_RC); } - - return(o_rc); - -} + return(o_rc); } +} diff --git a/src/usr/hwpf/hwp/bus_training/io_fir_isolation_errors.xml b/src/usr/hwpf/hwp/bus_training/io_fir_isolation_errors.xml new file mode 100755 index 000000000..da002fce4 --- /dev/null +++ b/src/usr/hwpf/hwp/bus_training/io_fir_isolation_errors.xml @@ -0,0 +1,204 @@ +<!-- IBM_PROLOG_BEGIN_TAG --> +<!-- This is an automatically generated prolog. --> +<!-- --> +<!-- $Source: src/usr/hwpf/hwp/bus_training/io_fir_isolation_errors.xml $ --> +<!-- --> +<!-- IBM CONFIDENTIAL --> +<!-- --> +<!-- COPYRIGHT International Business Machines Corp. 2014 --> +<!-- --> +<!-- p1 --> +<!-- --> +<!-- Object Code Only (OCO) source materials --> +<!-- Licensed Internal Code Source Materials --> +<!-- IBM HostBoot Licensed Internal Code --> +<!-- --> +<!-- The source code for this program is not published or otherwise --> +<!-- divested of its trade secrets, irrespective of what has been --> +<!-- deposited with the U.S. Copyright Office. --> +<!-- --> +<!-- Origin: 30 --> +<!-- --> +<!-- IBM_PROLOG_END_TAG --> +<!-- $Id: io_fir_isolation_errors.xml,v 1.4 2014/03/20 14:09:56 varkeykv Exp $ --> +<hwpErrors> + <hwpError> + <rc>IO_FIR_TOO_MANY_BUS_ERROR_RC</rc> + <description>A bus has experienced too many random lane errors</description> + <ffdc>ENDPOINT</ffdc> + <ffdc>BUS_ERROR_REG</ffdc> + <callout> + <target>ENDPOINT</target> + <priority>HIGH</priority> + </callout> + <deconfigure> + <target>ENDPOINT</target> + </deconfigure> + <gard> + <target>ENDPOINT</target> + </gard> + </hwpError> + <hwpError> + <rc>IO_FIR_RECALIBRATION_ERROR_RC</rc> + <description>recalibration or a repair error has been detected</description> + <ffdc>ENDPOINT</ffdc> + <ffdc>RECAL_ERROR_REG</ffdc> + <callout> + <target>ENDPOINT</target> + <priority>HIGH</priority> + </callout> + <deconfigure> + <target>ENDPOINT</target> + </deconfigure> + <gard> + <target>ENDPOINT</target> + </gard> + </hwpError> + <hwpError> + <rc>IO_FIR_MAX_SPARES_EXCEEDED_FIR_RC</rc> + <description>maximum spares possible to deploy exceeded</description> + <ffdc>ENDPOINT</ffdc> + <ffdc>SPARE_ERROR_REG</ffdc> + <callout> + <target>ENDPOINT</target> + <priority>HIGH</priority> + </callout> + <deconfigure> + <target>ENDPOINT</target> + </deconfigure> + <gard> + <target>ENDPOINT</target> + </gard> + </hwpError> + <hwpError> + <rc>IO_FIR_SPARES_DEPLOYED_FIR_RC</rc> + <description>A spare has been deployed</description> + <ffdc>ENDPOINT</ffdc> + <ffdc>SPARE_ERROR_REG</ffdc> + <callout> + <target>ENDPOINT</target> + <priority>HIGH</priority> + </callout> + <deconfigure> + <target>ENDPOINT</target> + </deconfigure> + <gard> + <target>ENDPOINT</target> + </gard> + </hwpError> + <hwpError> + <rc>IO_FIR_LANE_TX_PARITY_ERROR_RC</rc> + <description>io lane level tx parity error set</description> + <ffdc>ENDPOINT</ffdc> + <ffdc>LANE_ID</ffdc> + <ffdc>TX_ERROR_REG</ffdc> + <callout> + <target>ENDPOINT</target> + <priority>HIGH</priority> + </callout> + <deconfigure> + <target>ENDPOINT</target> + </deconfigure> + <gard> + <target>ENDPOINT</target> + </gard> + </hwpError> + <hwpError> + <rc>IO_FIR_GROUP_TX_PARITY_ERROR_RC</rc> + <description>io group level tx parity error set</description> + <ffdc>ENDPOINT</ffdc> + <ffdc>TX_ERROR_REG</ffdc> + <callout> + <target>ENDPOINT</target> + <priority>HIGH</priority> + </callout> + <deconfigure> + <target>ENDPOINT</target> + </deconfigure> + <gard> + <target>ENDPOINT</target> + </gard> + </hwpError> + <hwpError> + <rc>IO_FIR_LANE_RX_PARITY_ERROR_RC</rc> + <description>io lane level rx parity error set</description> + <ffdc>ENDPOINT</ffdc> + <ffdc>LANE_ID</ffdc> + <ffdc>RX_ERROR_REG</ffdc> + <callout> + <target>ENDPOINT</target> + <priority>HIGH</priority> + </callout> + <deconfigure> + <target>ENDPOINT</target> + </deconfigure> + <gard> + <target>ENDPOINT</target> + </gard> + </hwpError> + <hwpError> + <rc>IO_FIR_GROUP_RX_PARITY_ERROR_RC</rc> + <description>io group level rx parity error set</description> + <ffdc>ENDPOINT</ffdc> + <ffdc>RX_ERROR_REG</ffdc> + <callout> + <target>ENDPOINT</target> + <priority>HIGH</priority> + </callout> + <deconfigure> + <target>ENDPOINT</target> + </deconfigure> + <gard> + <target>ENDPOINT</target> + </gard> + </hwpError> + <hwpError> + <rc>IO_FIR_BUS_RX_PARITY_ERROR_RC</rc> + <description>io bus level rx parity error set</description> + <ffdc>ENDPOINT</ffdc> + <ffdc>RX_ERROR_REG</ffdc> + <callout> + <target>ENDPOINT</target> + <priority>HIGH</priority> + </callout> + <deconfigure> + <target>ENDPOINT</target> + </deconfigure> + <gard> + <target>ENDPOINT</target> + </gard> + </hwpError> + <hwpError> + <rc>IO_FIR_GCR_HANG_ERROR_RC</rc> + <description>gcr hang error detected</description> + <ffdc>ENDPOINT</ffdc> + <callout> + <target>ENDPOINT</target> + <priority>HIGH</priority> + </callout> + <deconfigure> + <target>ENDPOINT</target> + </deconfigure> + <gard> + <target>ENDPOINT</target> + </gard> + </hwpError> + <hwpError> + <rc>IO_FIR_INVALID_INVOCATION_RC</rc> + <description>io clear firs hwp invoked with wrong pair of targets</description> + <ffdc>ENDPOINT</ffdc> + <callout> + <procedure>CODE</procedure> + <priority>HIGH</priority> + </callout> + </hwpError> + <hwpError> + <rc>IO_CLEAR_FIRS_INVALID_INVOCATION_RC</rc> + <description>io clear firs hwp invoked with wrong pair of targets</description> + <ffdc>ENDPOINT</ffdc> + <callout> + <procedure>CODE</procedure> + <priority>HIGH</priority> + </callout> + </hwpError> +</hwpErrors> diff --git a/src/usr/hwpf/hwp/bus_training/io_funcs.C b/src/usr/hwpf/hwp/bus_training/io_funcs.C index ebe838ad2..2cd372dde 100644 --- a/src/usr/hwpf/hwp/bus_training/io_funcs.C +++ b/src/usr/hwpf/hwp/bus_training/io_funcs.C @@ -20,7 +20,7 @@ /* Origin: 30 */ /* */ /* IBM_PROLOG_END_TAG */ -// $Id: io_funcs.C,v 1.19 2014/02/11 05:46:59 varkeykv Exp $ +// $Id: io_funcs.C,v 1.25 2014/03/20 08:36:49 varkeykv Exp $ // *!*************************************************************************** // *! (C) Copyright International Business Machines Corp. 1997, 1998 // *! All Rights Reserved -- Property of IBM @@ -82,6 +82,7 @@ ReturnCode edi_training::run_training(const Target& master_target, io_interfac rc=training_function_status(master_target , master_interface,current_group, slave_target , slave_interface,current_group); if(!rc.ok()){ FAPI_ERR("io_run_training : Failed Training"); + return rc; } } } @@ -89,6 +90,7 @@ ReturnCode edi_training::run_training(const Target& master_target, io_interfac rc=training_function_status(master_target , master_interface,master_group, slave_target , slave_interface,slave_group); if(!rc.ok()){ FAPI_ERR("io_run_training : Failed Training"); + return rc; } } } @@ -204,6 +206,14 @@ ReturnCode edi_training::training_function_status(const Target& master_chip_ta rc_ecmd|=status_data.setBitLength(16); rc_ecmd|=status_data.flushTo0(); + //Reference variables matching error XML + const fapi::Target& MASTER_TARGET = master_chip_target; + const fapi::Target& SLAVE_TARGET = slave_chip_target; + const io_interface_t& MASTER_CHIP_INTERFACE = master_chip_interface; + const uint32_t& MASTER_GROUP = master_group; + const io_interface_t& SLAVE_CHIP_INTERFACE = slave_chip_interface; + const uint32_t& SLAVE_GROUP = slave_group; + if(rc_ecmd) { FAPI_ERR("io_run_training: Failed buffer intialization in training_function_status\n"); @@ -244,11 +254,11 @@ ReturnCode edi_training::training_function_status(const Target& master_chip_ta if (status_data.getHalfWord(0) & fail_bit) { FAPI_ERR("io_run_training: the wiretest training state reported a fail \n"); - FAPI_SET_HWP_ERROR(rc, IO_RUN_TRAINING_FAIL_WIRETEST_RC); + // FAPI_SET_HWP_ERROR(rc, IO_RUN_TRAINING_FAIL_WIRETEST_RC); wire_test_status = FAILED ; rx_wderf_failed[WIRE_TEST]=true; // Run First FAILED Data Capture for Wire Test for FAILED bus - dump_ffdc_wiretest(master_chip_target, master_chip_interface , master_group, slave_chip_target , slave_chip_interface,slave_group); + rc=dump_ffdc_wiretest(master_chip_target, master_chip_interface , master_group, slave_chip_target , slave_chip_interface,slave_group); break; } @@ -272,8 +282,9 @@ ReturnCode edi_training::training_function_status(const Target& master_chip_ta { rx_wderf_failed[DESKEW]=true; FAPI_ERR("io_run_training : deskew training state reported a fail \n"); - FAPI_SET_HWP_ERROR(rc, IO_RUN_TRAINING_FAIL_DESKEW_RC); + //FAPI_SET_HWP_ERROR(rc, IO_RUN_TRAINING_FAIL_DESKEW_RC); desckew_status = FAILED ; + rc=dump_ffdc_deskew(master_chip_target, master_chip_interface , master_group, slave_chip_target , slave_chip_interface,slave_group); break; } else @@ -295,9 +306,10 @@ ReturnCode edi_training::training_function_status(const Target& master_chip_ta if (status_data.getHalfWord(0) & fail_bit) { FAPI_ERR("io_run_training : eye_opt_ training state reported a fail\n"); - FAPI_SET_HWP_ERROR(rc, IO_RUN_TRAINING_FAIL_EYE_OPT_RC); + //FAPI_SET_HWP_ERROR(rc, IO_RUN_TRAINING_FAIL_EYE_OPT_RC); rx_wderf_failed[EYE_OPT]=true; eye_opt_status = FAILED ; + rc=dump_ffdc_eyeopt(master_chip_target, master_chip_interface , master_group, slave_chip_target , slave_chip_interface,slave_group); break; } else @@ -319,7 +331,8 @@ ReturnCode edi_training::training_function_status(const Target& master_chip_ta if (status_data.getHalfWord(0) & fail_bit) { FAPI_DBG("io_run_training: static repair encountered an error \n"); - FAPI_SET_HWP_ERROR(rc, IO_RUN_TRAINING_FAIL_REPAIR_RC); + //FAPI_SET_HWP_ERROR(rc, IO_RUN_TRAINING_FAIL_REPAIR_RC); + rc=dump_ffdc_repair(master_chip_target, master_chip_interface , master_group, slave_chip_target , slave_chip_interface,slave_group); rx_wderf_failed[REPAIR]=true; repair_status = FAILED ; break; @@ -346,7 +359,8 @@ ReturnCode edi_training::training_function_status(const Target& master_chip_ta { FAPI_DBG("io_run_training: rx_func_mode_failed \n"); rx_wderf_failed[FUNCTIONAL]=true; - FAPI_SET_HWP_ERROR(rc, IO_RUN_TRAINING_FAIL_FUNC_MODE_RC); + //FAPI_SET_HWP_ERROR(rc, IO_RUN_TRAINING_FAIL_FUNC_MODE_RC); + rc=dump_ffdc_func(master_chip_target, master_chip_interface , master_group, slave_chip_target , slave_chip_interface,slave_group); functional_status = FAILED ; break; } @@ -389,27 +403,27 @@ ReturnCode edi_training::training_function_status(const Target& master_chip_ta if (wire_test_selected && wire_test_status== RUNNING) { FAPI_ERR("io_run_training: wiretest timeout"); - FAPI_SET_HWP_ERROR(rc, IO_RUN_TRAINING_WIRETEST_TIMEOUT_RC); + FAPI_SET_HWP_ERROR(rc, IO_FUNCS_WIRETEST_TIMEOUT_RC); } else if (desckew_selected && desckew_status == RUNNING) { FAPI_ERR("io_run_training: deskew timeout"); - FAPI_SET_HWP_ERROR(rc, IO_RUN_TRAINING_DESKEW_TIMEOUT_RC); + FAPI_SET_HWP_ERROR(rc, IO_FUNCS_DESKEW_TIMEOUT_RC); } else if (repair_selected && repair_status == RUNNING) { FAPI_ERR("io_run_training: repair timeout"); - FAPI_SET_HWP_ERROR(rc, IO_RUN_TRAINING_REPAIR_TIMEOUT_RC); + FAPI_SET_HWP_ERROR(rc, IO_FUNCS_REPAIR_TIMEOUT_RC); } else if (eye_opt_selected && eye_opt_status == RUNNING) { FAPI_ERR("io_run_training: eyeopt timeout"); - FAPI_SET_HWP_ERROR(rc, IO_RUN_TRAINING_EYE_OPT_TIMEOUT_RC); + FAPI_SET_HWP_ERROR(rc, IO_FUNCS_EYEOPT_TIMEOUT_RC); } else { FAPI_ERR("io_run_training: func timeout"); - FAPI_SET_HWP_ERROR(rc, IO_RUN_TRAINING_FUNC_MODE_TIMEOUT_RC); + FAPI_SET_HWP_ERROR(rc, IO_FUNCS_FUNC_MODE_TIMEOUT_RC); } break; } @@ -449,77 +463,666 @@ ReturnCode edi_training::isChipMaster(const Target& chip_target, io_interface_t // First Fail Data Capture (wire_test) // FFDC functions have not been tested in detail .. -// Will need to tie this into the eRepair/PRD conversation that we are having with Zane +// Will need to tie this into the eRepair/PRD conversation that we are having with Zane + // DUMP ALL THESE + // rx_lane_disabled_vec_0_15_pg, + // rx_lane_disabled_vec_16_31_pg, + // rx_lane_swapped_vec_0_15_pg, + // rx_lane_swapped_vec_16_31_pg, + // rx_init_state_pg, + // rx_wiretest_state_pg, + // rx_wiretest_laneinfo_pg, + // rx_wt_status_pl + //rx_main_init_state + //rx_wtl_state + //rx_wtm_state + //rx_wtr_state + //rx_wtr_bad_lane_count + //rx_wt_lane_bad_code ( per lane - can we?) + //rx_wtr_bad_lane_count + //rx_wiretest_failed + //rx_wt_clk_bad_lane_code? + //rx_wt_clk_lane_inverted? + //rx_wt_clk_status_pg ReturnCode edi_training::dump_ffdc_wiretest(const Target& master_chip_target, io_interface_t master_chip_interface ,uint32_t master_group, const Target& slave_chip_target , io_interface_t slave_chip_interface,uint32_t slave_group) { - ReturnCode rc; - - ecmdDataBufferBase master_lane_bad_vec_0_15_data(16); - ecmdDataBufferBase master_lane_bad_vec_16_31_data(16); - ecmdDataBufferBase slave_lane_bad_vec_0_15_data(16); - ecmdDataBufferBase slave_lane_bad_vec_16_31_data(16); + ReturnCode rc; + ReturnCode lane_rc; // for logging per lane FFDC + + const io_interface_t& MASTER_CHIP_INTERFACE = master_chip_interface; + const uint32_t& MASTER_GROUP = master_group; + const io_interface_t& SLAVE_CHIP_INTERFACE = slave_chip_interface; + const uint32_t& SLAVE_GROUP = slave_group; + + const fapi::Target &MASTER_TARGET=master_chip_target; + const fapi::Target &SLAVE_TARGET=slave_chip_target; + - ecmdDataBufferBase master_lane_bad_data(16); + //FFDC Buffers + ecmdDataBufferBase MASTER_RX_LANE_BAD_0_15_PG(16); + ecmdDataBufferBase MASTER_RX_LANE_BAD_16_31_PG(16); + ecmdDataBufferBase MASTER_RX_LANE_DISABLED_VEC_0_15_PG(16); + ecmdDataBufferBase MASTER_RX_LANE_DISABLED_VEC_16_31_PG(16); + ecmdDataBufferBase MASTER_RX_LANE_SWAPPED_VEC_0_15_PG(16); + ecmdDataBufferBase MASTER_RX_LANE_SWAPPED_VEC_16_31_PG(16); + ecmdDataBufferBase MASTER_RX_INIT_STATE_PG(16); + ecmdDataBufferBase MASTER_RX_WIRETEST_STATE_PG(16); + ecmdDataBufferBase MASTER_RX_WIRETEST_LANEINFO_PG(16); + ecmdDataBufferBase MASTER_RX_TRAINING_STATUS_PG(16); + ecmdDataBufferBase MASTER_RX_WT_CLK_STATUS_PG(16); + ecmdDataBufferBase SLAVE_RX_LANE_BAD_0_15_PG(16); + ecmdDataBufferBase SLAVE_RX_LANE_BAD_16_31_PG(16); + ecmdDataBufferBase SLAVE_RX_LANE_DISABLED_VEC_0_15_PG(16); + ecmdDataBufferBase SLAVE_RX_LANE_DISABLED_VEC_16_31_PG(16); + ecmdDataBufferBase SLAVE_RX_LANE_SWAPPED_VEC_0_15_PG(16); + ecmdDataBufferBase SLAVE_RX_LANE_SWAPPED_VEC_16_31_PG(16); + ecmdDataBufferBase SLAVE_RX_INIT_STATE_PG(16); + ecmdDataBufferBase SLAVE_RX_WIRETEST_STATE_PG(16); + ecmdDataBufferBase SLAVE_RX_WIRETEST_LANEINFO_PG(16); + ecmdDataBufferBase SLAVE_RX_TRAINING_STATUS_PG(16); + ecmdDataBufferBase SLAVE_RX_WT_CLK_STATUS_PG(16); + + //These are for per-lane FFDC captures + ecmdDataBufferBase RX_WT_STATUS_PL(16); + + const uint32_t NUM_PG_REGS=11; + // const uint32_t NUM_PL_REGS=0; + + const GCR_sub_registers pg_reg_list[NUM_PG_REGS]={rx_lane_bad_vec_0_15_pg,rx_lane_bad_vec_16_31_pg,rx_lane_disabled_vec_0_15_pg, rx_lane_disabled_vec_16_31_pg,rx_lane_swapped_vec_0_15_pg, + rx_lane_swapped_vec_16_31_pg,rx_init_state_pg,rx_wiretest_state_pg,rx_wiretest_laneinfo_pg,rx_training_status_pg,rx_wt_clk_status_pg}; + + // const GCR_sub_registers pl_reg_list[NUM_PL_REGS]={}; + + ecmdDataBufferBase *MASTER_BUFFERS[NUM_PG_REGS]= { &MASTER_RX_LANE_BAD_0_15_PG, + &MASTER_RX_LANE_BAD_16_31_PG, + &MASTER_RX_LANE_DISABLED_VEC_0_15_PG, + &MASTER_RX_LANE_DISABLED_VEC_16_31_PG, + &MASTER_RX_LANE_SWAPPED_VEC_0_15_PG, + &MASTER_RX_LANE_SWAPPED_VEC_16_31_PG, + &MASTER_RX_INIT_STATE_PG, + &MASTER_RX_WIRETEST_STATE_PG, + &MASTER_RX_WIRETEST_LANEINFO_PG, + &MASTER_RX_TRAINING_STATUS_PG, + &MASTER_RX_WT_CLK_STATUS_PG + }; + + ecmdDataBufferBase *SLAVE_BUFFERS[NUM_PG_REGS]= { &SLAVE_RX_LANE_BAD_0_15_PG, + &SLAVE_RX_LANE_BAD_16_31_PG, + &SLAVE_RX_LANE_DISABLED_VEC_0_15_PG, + &SLAVE_RX_LANE_DISABLED_VEC_16_31_PG, + &SLAVE_RX_LANE_SWAPPED_VEC_0_15_PG, + &SLAVE_RX_LANE_SWAPPED_VEC_16_31_PG, + &SLAVE_RX_INIT_STATE_PG, + &SLAVE_RX_WIRETEST_STATE_PG, + &SLAVE_RX_WIRETEST_LANEINFO_PG, + &SLAVE_RX_TRAINING_STATUS_PG, + &SLAVE_RX_WT_CLK_STATUS_PG + }; FAPI_DBG("dump_ffdc_wiretest function entered \n"); + + - // DO MASTER HERE - // Read rx_lane_bad_vec_0_15_pg & rx_lane_bad_vec_16_32_pg - if(master_chip_interface==CP_FABRIC_X0) - { - rc=GCR_read(master_chip_target , master_chip_interface, ei4_rx_lane_bad_vec_0_15_pg, master_group,0, master_lane_bad_vec_0_15_data); - } - else - { - rc=GCR_read(master_chip_target , master_chip_interface, rx_lane_bad_vec_0_15_pg, master_group,0, master_lane_bad_vec_0_15_data); - } - if (rc) - { - FAPI_ERR("io_run_training : Error Reading rx_lane_bad_vec_0_15"); - } - //avoiding else on purpose.. I want to try reading the second registe if first one on master fails - if(master_chip_interface==CP_FABRIC_X0) - { - rc=GCR_read(master_chip_target , master_chip_interface, ei4_rx_lane_bad_vec_16_31_pg, master_group,0, master_lane_bad_vec_16_31_data); - } - else - { - rc=GCR_read(master_chip_target , master_chip_interface, rx_lane_bad_vec_16_31_pg, master_group,0, master_lane_bad_vec_16_31_data); - } - if (rc) { - FAPI_ERR("io_run_training : Error Reading rx_lane_bad_vec_16_31"); - } - // Not doing the else here on purpose.. if read on master fails .. we want to try reading slave side + // Capture MASTER Side registers + + uint32_t rx_lane_end=num_rxlanes_per_group[master_chip_interface]; - // DO SLAVE HERE - if(slave_chip_interface==CP_FABRIC_X0) - { - rc=GCR_read(slave_chip_target , slave_chip_interface, ei4_rx_lane_bad_vec_0_15_pg, slave_group,0, slave_lane_bad_vec_0_15_data); - } - else - { - rc=GCR_read(slave_chip_target , slave_chip_interface, rx_lane_bad_vec_0_15_pg, slave_group,0, slave_lane_bad_vec_0_15_data); - } - if (rc) - { - FAPI_ERR("io_run_training : Error Reading rx_lane_bad_vec_0_15 on slave chip"); - - } - if(slave_chip_interface==CP_FABRIC_X0) - { - rc=GCR_read(slave_chip_target , slave_chip_interface, ei4_rx_lane_bad_vec_16_31_pg, slave_group,0, slave_lane_bad_vec_16_31_data); - } - else - { - rc=GCR_read(slave_chip_target , slave_chip_interface, rx_lane_bad_vec_16_31_pg, slave_group,0, slave_lane_bad_vec_16_31_data); - } - if (rc) { - FAPI_ERR("io_run_training : Error Reading rx_lane_bad_vec_16_31 on slave chip"); - } + for(uint32_t reg_num=0;reg_num<NUM_PG_REGS;++reg_num){ + FAPI_DBG("Reading register name %s on MASTER side",GCR_sub_reg_names[pg_reg_list[reg_num]]); + rc=GCR_read(master_chip_target , master_chip_interface, pg_reg_list[reg_num], master_group,0, *MASTER_BUFFERS[reg_num]); + if (rc) + { + FAPI_ERR("io_run_training : Error Reading %s",GCR_sub_reg_names[pg_reg_list[reg_num]]); + } + // Not doing the else here on purpose.. if read on one reg fails , we want to try next and maybe the slave side if all fails + + } + + for(uint32_t reg_num=0;reg_num<NUM_PG_REGS;++reg_num){ + FAPI_DBG("Reading register name %s on SLAVE side",GCR_sub_reg_names[pg_reg_list[reg_num]]); + rc=GCR_read(slave_chip_target , slave_chip_interface, pg_reg_list[reg_num], slave_group,0, *SLAVE_BUFFERS[reg_num]); + if (rc) + { + FAPI_ERR("io_run_training : Error Reading %s",GCR_sub_reg_names[pg_reg_list[reg_num]]); + } + // Not doing the else here on purpose.. if read on one reg fails , we want to try next and maybe the slave side if all fails + } + + FAPI_SET_HWP_ERROR(lane_rc,IO_FUNCS_WIRETEST_FAIL_RC); + + //Lets do per-lane registers now , will Log and continue instead of wasting buffers and making it complex + for(uint32_t lane=0;lane<rx_lane_end;++lane){ + FAPI_DBG("Reading per lane register RX_WT_STATUS_PL on lane %d",lane); + rc=GCR_read(master_chip_target , master_chip_interface, rx_wt_status_pl, master_group,lane, RX_WT_STATUS_PL); + if (rc) + { + FAPI_ERR("io_run_training : Error Reading RX_WT_STATUS_PL"); + } + else{ + // we will continue to try other lanes data + const fapi::Target & CHIP_TARGET= master_chip_target; + uint32_t &LANEID=lane; + //as per Andrea to save log space + FAPI_ADD_INFO_TO_HWP_ERROR(lane_rc,IO_FUNCS_WIRETEST_FAIL_LANE_MASTER_DATA_RC); + } + } + + + // Capture SLAVE Side registers + rx_lane_end=num_rxlanes_per_group[slave_chip_interface]; + + + + //Lets do per-lane registers now , will Log and continue instead of wasting buffers and making it complex + for(uint32_t lane=0;lane<rx_lane_end;++lane){ + FAPI_DBG("Reading per lane register RX_WT_STATUS_PL on lane %d",lane); + rc=GCR_read(slave_chip_target , slave_chip_interface, rx_wt_status_pl, slave_group,lane, RX_WT_STATUS_PL); + if (rc) + { + FAPI_ERR("io_run_training : Error Reading RX_WT_STATUS_PL"); + } + else{ + const fapi::Target & CHIP_TARGET= slave_chip_target; + uint32_t &LANEID=lane; + //as per Andrea to save log space + FAPI_ADD_INFO_TO_HWP_ERROR(lane_rc,IO_FUNCS_WIRETEST_FAIL_LANE_SLAVE_DATA_RC); + } + } + + return(lane_rc); +} + + + //rx_rxdsm_state + // rx_deskew_failed --> rx_training_status_pg + // rx_bad_block_lock --> rx_deskew_stat_pl + // rx_bad_skew --> rx_deskew_stat_pl + // rx_bad_deskew --> rx_deskew_stat_pl + // rx_some_skew_valid --> rx_stat_pl + // rx_some_block_locked --> rx_stat_pl + // rx_skew_value --> rx_stat_pl + // rx_vref --> rx_vref_pl + // rx_fifo_l2u_dly --> rx_fifo_stat_pl + // rx_phaserot_val --> rx_prot_status_pl + +ReturnCode edi_training::dump_ffdc_deskew(const Target& master_chip_target, io_interface_t master_chip_interface ,uint32_t master_group, const Target& slave_chip_target , + io_interface_t slave_chip_interface,uint32_t slave_group) +{ + ReturnCode rc; + ReturnCode lane_rc; // for logging per lane FFDC + + const fapi::Target &MASTER_TARGET=master_chip_target; + const fapi::Target &SLAVE_TARGET=slave_chip_target; + const io_interface_t& MASTER_CHIP_INTERFACE = master_chip_interface; + const uint32_t& MASTER_GROUP = master_group; + const io_interface_t& SLAVE_CHIP_INTERFACE = slave_chip_interface; + const uint32_t& SLAVE_GROUP = slave_group; + + + //FFDC Buffers; + ecmdDataBufferBase MASTER_RX_INIT_STATE_PG(16); + ecmdDataBufferBase MASTER_RX_TRAINING_STATUS_PG(16); + ecmdDataBufferBase MASTER_RX_DESKEW_STATE_PG(16); + ecmdDataBufferBase MASTER_RX_LANE_BAD_0_15_PG(16); + ecmdDataBufferBase MASTER_RX_LANE_BAD_16_31_PG(16); + + ecmdDataBufferBase SLAVE_RX_INIT_STATE_PG(16); + ecmdDataBufferBase SLAVE_RX_TRAINING_STATUS_PG(16); + ecmdDataBufferBase SLAVE_RX_DESKEW_STATE_PG(16); + ecmdDataBufferBase SLAVE_RX_LANE_BAD_0_15_PG(16); + ecmdDataBufferBase SLAVE_RX_LANE_BAD_16_31_PG(16); + + + //These are for per-lane FFDC captures + ecmdDataBufferBase RX_DESKEW_STAT_PL(16); + ecmdDataBufferBase RX_STAT_PL(16); + ecmdDataBufferBase RX_FIFO_STAT_PL(16); + ecmdDataBufferBase RX_PROT_STATUS_PL(16); + + //EI4 only + ecmdDataBufferBase RX_VREF_PL(16); + + const uint32_t NUM_PG_REGS=5; + const uint32_t NUM_PL_REGS=5; + + const GCR_sub_registers pg_reg_list[NUM_PG_REGS]={rx_init_state_pg,rx_training_status_pg,rx_deskew_state_pg,rx_lane_bad_vec_0_15_pg,rx_lane_bad_vec_16_31_pg}; + + const GCR_sub_registers pl_reg_list[NUM_PL_REGS]={rx_deskew_stat_pl,rx_stat_pl,rx_fifo_stat_pl,rx_prot_status_pl,ei4_rx_vref_pl}; + + ecmdDataBufferBase *MASTER_BUFFERS[NUM_PG_REGS+NUM_PL_REGS]= { &MASTER_RX_INIT_STATE_PG, + &MASTER_RX_TRAINING_STATUS_PG, + &MASTER_RX_DESKEW_STATE_PG,&MASTER_RX_LANE_BAD_0_15_PG,&MASTER_RX_LANE_BAD_16_31_PG, + &RX_DESKEW_STAT_PL, + &RX_STAT_PL, + &RX_FIFO_STAT_PL, + &RX_PROT_STATUS_PL, + &RX_VREF_PL + }; + + ecmdDataBufferBase *SLAVE_BUFFERS[NUM_PG_REGS+NUM_PL_REGS]= { &SLAVE_RX_INIT_STATE_PG, + &SLAVE_RX_TRAINING_STATUS_PG, + & SLAVE_RX_DESKEW_STATE_PG,&SLAVE_RX_LANE_BAD_0_15_PG,&SLAVE_RX_LANE_BAD_16_31_PG, + &RX_DESKEW_STAT_PL, + &RX_STAT_PL, + &RX_FIFO_STAT_PL, + &RX_PROT_STATUS_PL, + &RX_VREF_PL + }; + + + FAPI_DBG("dump_ffdc_deskew function entered \n"); + + // Capture MASTER Side registers + + uint32_t rx_lane_end=num_rxlanes_per_group[master_chip_interface]; + + for(uint32_t reg_num=0;reg_num<NUM_PG_REGS;++reg_num){ + FAPI_DBG("Reading register name %s on MASTER side",GCR_sub_reg_names[pg_reg_list[reg_num]]); + rc=GCR_read(master_chip_target , master_chip_interface, pg_reg_list[reg_num], master_group,0, *MASTER_BUFFERS[reg_num]); + if (rc) + { + FAPI_ERR("io_run_training : Error Reading %s",GCR_sub_reg_names[pg_reg_list[reg_num]]); + } + // Not doing the else here on purpose.. if read on one reg fails , we want to try next and maybe the slave side if all fails + } + + + for(uint32_t reg_num=0;reg_num<NUM_PG_REGS;++reg_num){ + FAPI_DBG("Reading register name %s on SLAVE side",GCR_sub_reg_names[pg_reg_list[reg_num]]); + rc=GCR_read(slave_chip_target , slave_chip_interface, pg_reg_list[reg_num], slave_group,0, *SLAVE_BUFFERS[reg_num]); + if (rc) + { + FAPI_ERR("io_run_training : Error Reading %s",GCR_sub_reg_names[pg_reg_list[reg_num]]); + } + // Not doing the else here on purpose.. if read on one reg fails , we want to try next and maybe the slave side if all fails + } + + FAPI_SET_HWP_ERROR(lane_rc,IO_FUNCS_DESKEW_FAIL_RC); + //Lets do per-lane registers now , will Log and continue instead of wasting buffers and making it complex + for(uint32_t lane=0;lane<rx_lane_end;++lane){ + for(uint32_t lane_reg_num=0;lane_reg_num<NUM_PL_REGS;++lane_reg_num){ + if(master_chip_interface!=CP_FABRIC_X0 && pl_reg_list[lane_reg_num] ==ei4_rx_vref_pl ){ + continue; // VREF PL valid only for X bus + } + FAPI_DBG("Reading per lane register %s on lane %d",GCR_sub_reg_names[pl_reg_list[lane_reg_num]],lane); + rc=GCR_read(master_chip_target , master_chip_interface, pl_reg_list[lane_reg_num], master_group,lane, *MASTER_BUFFERS[NUM_PG_REGS+lane_reg_num]); + if (rc) + { + FAPI_ERR("io_run_training : Error Reading %s",GCR_sub_reg_names[pl_reg_list[lane_reg_num]]); + } + else{ + // we will continue to try other lanes data + const fapi::Target & CHIP_TARGET= master_chip_target; + uint32_t &LANEID=lane; + FAPI_SET_HWP_ERROR(lane_rc,IO_FUNCS_DESKEW_FAIL_LANE_MASTER_DATA_RC); + //as per Andrea to save log space + FAPI_ADD_INFO_TO_HWP_ERROR(lane_rc,IO_FUNCS_DESKEW_FAIL_LANE_MASTER_DATA_RC); + } + } + } + + + // Capture SLAVE Side registers + rx_lane_end=num_rxlanes_per_group[slave_chip_interface]; + + //Lets do per-lane registers now , will Log and continue instead of wasting buffers and making it complex + for(uint32_t lane=0;lane<rx_lane_end;++lane){ + for(uint32_t lane_reg_num=0;lane_reg_num<NUM_PL_REGS;++lane_reg_num){ + if(slave_chip_interface!=CP_FABRIC_X0 && pl_reg_list[lane_reg_num] ==ei4_rx_vref_pl ){ + continue; // VREF PL valid only for X bus + } + FAPI_DBG("Reading per lane register %s on lane %d",GCR_sub_reg_names[pl_reg_list[lane_reg_num]],lane); + rc=GCR_read(slave_chip_target , slave_chip_interface, pl_reg_list[lane_reg_num], slave_group,lane, *SLAVE_BUFFERS[NUM_PG_REGS+lane_reg_num]); + if (rc) + { + FAPI_ERR("io_run_training : Error Reading %s",GCR_sub_reg_names[pl_reg_list[lane_reg_num]]); + } + else{ + // we will continue to try other lanes data + const fapi::Target & CHIP_TARGET= slave_chip_target; + uint32_t &LANEID=lane; + //as per Andrea to save log space + FAPI_ADD_INFO_TO_HWP_ERROR(lane_rc,IO_FUNCS_DESKEW_FAIL_LANE_SLAVE_DATA_RC); + } + } + } + + + + return(lane_rc); +} + + +// FFDC AS per Rob +// +//rx_eye_opt_failed --> rx_training_status_pg +//rx_eye_opt_state rx_eo_recal_pg +//rx_ap_even_samp rx_ap_pl +//rx_ap_odd_samp rx_ap_pl +//rx_an_even_samp rx_an_pl +//rx_an_odd_samp rx_an_pl +//rx_amin_even rx_amin_pl +//rx_amin_odd rx_amin_pl +//rx_h1_even_samp1 rx_h1_even_pl +//rx_h1_even_samp0 rx_h1_even_pl +//rx_h1_odd_samp1 rx_h1_odd_pl +//rx_h1_odd_samp0 rx_h1_odd_pl +//rx_bad_eye_opt_ber rx_eye_opt_stat_pl +//rx_bad_eye_opt_width rx_eye_opt_stat_pl +//rx_bad_eye_opt_height rx_eye_opt_stat_pl +//rx_bad_eye_opt_ddc rx_eye_opt_stat_pl +//rx_eye_width rx_eye_width_status_pl +//rx_hist_min_eye_width_valid rx_eye_width_status_pl +//rx_hist_min_eye_width rx_eye_width_status_pl +//rx_dcd_adjust rx_dcd_adj_pl + +ReturnCode edi_training::dump_ffdc_eyeopt(const Target& master_chip_target, io_interface_t master_chip_interface ,uint32_t master_group, const Target& slave_chip_target , + io_interface_t slave_chip_interface,uint32_t slave_group) +{ + ReturnCode rc; + ReturnCode lane_rc; // for logging per lane FFDC + + const fapi::Target &MASTER_TARGET=master_chip_target; + const fapi::Target &SLAVE_TARGET=slave_chip_target; + + const io_interface_t& MASTER_CHIP_INTERFACE = master_chip_interface; + const uint32_t& MASTER_GROUP = master_group; + const io_interface_t& SLAVE_CHIP_INTERFACE = slave_chip_interface; + const uint32_t& SLAVE_GROUP = slave_group; + + //FFDC Buffers; + ecmdDataBufferBase MASTER_RX_TRAINING_STATUS_PG(16); + ecmdDataBufferBase MASTER_RX_EO_RECAL_PG(16); + ecmdDataBufferBase MASTER_RX_LANE_BAD_0_15_PG(16); + ecmdDataBufferBase MASTER_RX_LANE_BAD_16_31_PG(16); + + ecmdDataBufferBase SLAVE_RX_TRAINING_STATUS_PG(16); + ecmdDataBufferBase SLAVE_RX_EO_RECAL_PG(16); + ecmdDataBufferBase SLAVE_RX_LANE_BAD_0_15_PG(16); + ecmdDataBufferBase SLAVE_RX_LANE_BAD_16_31_PG(16); + + + //These are for per-lane FFDC captures + ecmdDataBufferBase RX_AP_PL(16);// EDI only + ecmdDataBufferBase RX_AN_PL(16);// EDI only + ecmdDataBufferBase RX_AMIN_PL(16);// EDI only + ecmdDataBufferBase RX_H1_EVEN_PL(16);// EDI only + ecmdDataBufferBase RX_H1_ODD_PL(16);// EDI only + ecmdDataBufferBase RX_EYE_OPT_STATE_PL(16); // both + ecmdDataBufferBase RX_EYE_WIDTH_STATUS_PL(16); //both + ecmdDataBufferBase RX_DCD_ADJ_PL(16); // ei4 only + + const uint32_t NUM_PG_REGS=4; + const uint32_t NUM_PL_REGS=8; + + const GCR_sub_registers pg_reg_list[NUM_PG_REGS]={rx_training_status_pg,rx_eo_recal_pg,rx_lane_bad_vec_0_15_pg,rx_lane_bad_vec_16_31_pg}; + + const GCR_sub_registers pl_reg_list[NUM_PL_REGS]={rx_ap_pl,rx_an_pl,rx_amin_pl,rx_h1_even_pl,rx_h1_odd_pl,rx_eye_opt_stat_pl,rx_eye_width_status_pl,ei4_rx_dcd_adj_pl}; + + ecmdDataBufferBase *MASTER_BUFFERS[NUM_PG_REGS+NUM_PL_REGS]= { &MASTER_RX_TRAINING_STATUS_PG, + &MASTER_RX_EO_RECAL_PG,&MASTER_RX_LANE_BAD_0_15_PG,&MASTER_RX_LANE_BAD_16_31_PG, + &RX_AP_PL, + &RX_AN_PL, + &RX_AMIN_PL, + &RX_H1_EVEN_PL, + &RX_H1_ODD_PL, + &RX_EYE_OPT_STATE_PL, + &RX_EYE_WIDTH_STATUS_PL, + &RX_DCD_ADJ_PL + }; + + + ecmdDataBufferBase *SLAVE_BUFFERS[NUM_PG_REGS+NUM_PL_REGS]= { &SLAVE_RX_TRAINING_STATUS_PG, + &SLAVE_RX_EO_RECAL_PG,&SLAVE_RX_LANE_BAD_0_15_PG,&SLAVE_RX_LANE_BAD_16_31_PG, + &RX_AP_PL, + &RX_AN_PL, + &RX_AMIN_PL, + &RX_H1_EVEN_PL, + &RX_H1_ODD_PL, + &RX_EYE_OPT_STATE_PL, + &RX_EYE_WIDTH_STATUS_PL, + &RX_DCD_ADJ_PL + }; + + + + FAPI_DBG("dump_ffdc_eyeopt function entered \n"); + + // Capture MASTER Side registers + + uint32_t rx_lane_end=num_rxlanes_per_group[master_chip_interface]; + + for(uint32_t reg_num=0;reg_num<NUM_PG_REGS;++reg_num){ + FAPI_DBG("Reading register name %s on MASTER side",GCR_sub_reg_names[pg_reg_list[reg_num]]); + rc=GCR_read(master_chip_target , master_chip_interface, pg_reg_list[reg_num], master_group,0, *MASTER_BUFFERS[reg_num]); + if (rc) + { + FAPI_ERR("io_run_training : Error Reading %s",GCR_sub_reg_names[pg_reg_list[reg_num]]); + } + // Not doing the else here on purpose.. if read on one reg fails , we want to try next and maybe the slave side if all fails + } + + + for(uint32_t reg_num=0;reg_num<NUM_PG_REGS;++reg_num){ + FAPI_DBG("Reading register name %s on SLAVE side",GCR_sub_reg_names[pg_reg_list[reg_num]]); + rc=GCR_read(slave_chip_target , slave_chip_interface, pg_reg_list[reg_num], slave_group,0, *SLAVE_BUFFERS[reg_num]); + if (rc) + { + FAPI_ERR("io_run_training : Error Reading %s",GCR_sub_reg_names[pg_reg_list[reg_num]]); + } + // Not doing the else here on purpose.. if read on one reg fails , we want to try next and maybe the slave side if all fails + } + + FAPI_SET_HWP_ERROR(lane_rc,IO_FUNCS_EYEOPT_FAIL_RC); + //Lets do per-lane registers now , will Log and continue instead of wasting buffers and making it complex + for(uint32_t lane=0;lane<rx_lane_end;++lane){ + for(uint32_t lane_reg_num=0;lane_reg_num<NUM_PL_REGS;++lane_reg_num){ + if(master_chip_interface!=CP_FABRIC_X0 && pl_reg_list[lane_reg_num] ==ei4_rx_dcd_adj_pl ){ + continue; // DCD ADJ PL valid only for X bus + } + if(master_chip_interface==CP_FABRIC_X0 && lane_reg_num<5 ){ + continue; // Only 7,8,9 regs valid on X bus + } + FAPI_DBG("Reading per lane register %s on lane %d",GCR_sub_reg_names[pl_reg_list[lane_reg_num]],lane); + rc=GCR_read(master_chip_target , master_chip_interface, pl_reg_list[lane_reg_num], master_group,lane, *MASTER_BUFFERS[NUM_PG_REGS+lane_reg_num]); + if (rc) + { + FAPI_ERR("io_run_training : Error Reading %s",GCR_sub_reg_names[pl_reg_list[lane_reg_num]]); + } + else{ + // we will continue to try other lanes data + const fapi::Target & CHIP_TARGET= master_chip_target; + uint32_t &LANEID=lane; + //as per Andrea to save log space + FAPI_ADD_INFO_TO_HWP_ERROR(lane_rc,IO_FUNCS_EYEOPT_FAIL_LANE_MASTER_DATA_RC); + } + } + } + + + // Capture SLAVE Side registers + rx_lane_end=num_rxlanes_per_group[slave_chip_interface]; + + //Lets do per-lane registers now , will Log and continue instead of wasting buffers and making it complex + for(uint32_t lane=0;lane<rx_lane_end;++lane){ + for(uint32_t lane_reg_num=0;lane_reg_num<NUM_PL_REGS;++lane_reg_num){ + if(slave_chip_interface!=CP_FABRIC_X0 && pl_reg_list[lane_reg_num] ==ei4_rx_dcd_adj_pl ){ + continue; // DCD ADJ PL valid only for X bus + } + if(slave_chip_interface==CP_FABRIC_X0 && lane_reg_num<5 ){ + continue; // Only 7,8,9 regs valid on X bus + } + FAPI_DBG("Reading per lane register %s on lane %d",GCR_sub_reg_names[pl_reg_list[lane_reg_num]],lane); + rc=GCR_read(slave_chip_target , slave_chip_interface, pl_reg_list[lane_reg_num], slave_group,lane, *SLAVE_BUFFERS[NUM_PG_REGS+lane_reg_num]); + if (rc) + { + FAPI_ERR("io_run_training : Error Reading %s",GCR_sub_reg_names[pl_reg_list[lane_reg_num]]); + } + else{ + // we will continue to try other lanes data + const fapi::Target & CHIP_TARGET= slave_chip_target; + uint32_t &LANEID=lane; + //as per Andrea to save log space + FAPI_ADD_INFO_TO_HWP_ERROR(lane_rc,IO_FUNCS_EYEOPT_FAIL_LANE_SLAVE_DATA_RC); + } + } + } + + + + return(lane_rc); +} + +//FFDC for repair +//rx_rpr_state rx_static_repair_state_pg +//rx_repair_failed rx_training_status_pg +//rx_bad_lane1_gcrmsg rx_bad_lane_enc_gcrmsg_pg +//rx_bad_lane2_gcrmsgrx_bad_lane_enc_gcrmsg_pg + +ReturnCode edi_training::dump_ffdc_repair(const Target& master_chip_target, io_interface_t master_chip_interface ,uint32_t master_group, const Target& slave_chip_target , + io_interface_t slave_chip_interface,uint32_t slave_group) +{ + ReturnCode rc; + ReturnCode lane_rc; // for logging per lane FFDC + + const fapi::Target &MASTER_TARGET=master_chip_target; + const fapi::Target &SLAVE_TARGET=slave_chip_target; + const io_interface_t& MASTER_CHIP_INTERFACE = master_chip_interface; + const uint32_t& MASTER_GROUP = master_group; + const io_interface_t& SLAVE_CHIP_INTERFACE = slave_chip_interface; + const uint32_t& SLAVE_GROUP = slave_group; + + //FFDC Buffers; + ecmdDataBufferBase MASTER_RX_STATIC_REPAIR_STATE_PG(16); + ecmdDataBufferBase MASTER_RX_TRAINING_STATUS_PG(16); + ecmdDataBufferBase MASTER_RX_BAD_LANE_ENC_GCRMSG_PG(16); + + ecmdDataBufferBase SLAVE_RX_STATIC_REPAIR_STATE_PG(16); + ecmdDataBufferBase SLAVE_RX_TRAINING_STATUS_PG(16); + ecmdDataBufferBase SLAVE_RX_BAD_LANE_ENC_GCRMSG_PG(16); + + + + const uint32_t NUM_PG_REGS=3; + + const GCR_sub_registers pg_reg_list[NUM_PG_REGS]={rx_static_repair_state_pg,rx_training_status_pg,rx_bad_lane_enc_gcrmsg_pg}; + + + ecmdDataBufferBase *MASTER_BUFFERS[NUM_PG_REGS]= { + &MASTER_RX_STATIC_REPAIR_STATE_PG, + &MASTER_RX_TRAINING_STATUS_PG, + &MASTER_RX_BAD_LANE_ENC_GCRMSG_PG, + }; + + + ecmdDataBufferBase *SLAVE_BUFFERS[NUM_PG_REGS]= { + &SLAVE_RX_STATIC_REPAIR_STATE_PG, + &SLAVE_RX_TRAINING_STATUS_PG, + &SLAVE_RX_BAD_LANE_ENC_GCRMSG_PG, + }; + + + + + FAPI_DBG("dump_ffdc_repair function entered \n"); + + // Capture MASTER Side registers + + + for(uint32_t reg_num=0;reg_num<NUM_PG_REGS;++reg_num){ + FAPI_DBG("Reading register name %s on MASTER side",GCR_sub_reg_names[pg_reg_list[reg_num]]); + rc=GCR_read(master_chip_target , master_chip_interface, pg_reg_list[reg_num], master_group,0, *MASTER_BUFFERS[reg_num]); + if (rc) + { + FAPI_ERR("io_run_training : Error Reading %s",GCR_sub_reg_names[pg_reg_list[reg_num]]); + } + // Not doing the else here on purpose.. if read on one reg fails , we want to try next and maybe the slave side if all fails + } + + for(uint32_t reg_num=0;reg_num<NUM_PG_REGS;++reg_num){ + FAPI_DBG("Reading register name %s on SLAVE side",GCR_sub_reg_names[pg_reg_list[reg_num]]); + rc=GCR_read(slave_chip_target , slave_chip_interface, pg_reg_list[reg_num], slave_group,0, *SLAVE_BUFFERS[reg_num]); + if (rc) + { + FAPI_ERR("io_run_training : Error Reading %s",GCR_sub_reg_names[pg_reg_list[reg_num]]); + } + // Not doing the else here on purpose.. if read on one reg fails , we want to try next and maybe the slave side if all fails + } + + FAPI_SET_HWP_ERROR(rc,IO_FUNCS_REPAIR_FAIL_RC); return(rc); } +ReturnCode edi_training::dump_ffdc_func(const Target& master_chip_target, io_interface_t master_chip_interface ,uint32_t master_group, const Target& slave_chip_target , + io_interface_t slave_chip_interface,uint32_t slave_group) +{ + ReturnCode rc; + ReturnCode lane_rc; // for logging per lane FFDC + + const fapi::Target &MASTER_TARGET=master_chip_target; + const fapi::Target &SLAVE_TARGET=slave_chip_target; + const io_interface_t& MASTER_CHIP_INTERFACE = master_chip_interface; + const uint32_t& MASTER_GROUP = master_group; + const io_interface_t& SLAVE_CHIP_INTERFACE = slave_chip_interface; + const uint32_t& SLAVE_GROUP = slave_group; + + //FFDC Buffers; + ecmdDataBufferBase MASTER_RX_FUNC_STATE_PG(16); + ecmdDataBufferBase MASTER_RX_TRAINING_STATUS_PG(16); + + ecmdDataBufferBase SLAVE_RX_FUNC_STATE_PG(16); + ecmdDataBufferBase SLAVE_RX_TRAINING_STATUS_PG(16); + + + + const uint32_t NUM_PG_REGS=2; + + const GCR_sub_registers pg_reg_list[NUM_PG_REGS]={rx_func_state_pg,rx_training_status_pg}; + + + ecmdDataBufferBase *MASTER_BUFFERS[NUM_PG_REGS]= { + &MASTER_RX_FUNC_STATE_PG, + &MASTER_RX_TRAINING_STATUS_PG, + }; + + + ecmdDataBufferBase *SLAVE_BUFFERS[NUM_PG_REGS]= { + &SLAVE_RX_FUNC_STATE_PG, + &SLAVE_RX_TRAINING_STATUS_PG, + }; + + + + + FAPI_DBG("dump_ffdc_func function entered \n"); + + // Capture MASTER Side registers + + + for(uint32_t reg_num=0;reg_num<NUM_PG_REGS;++reg_num){ + FAPI_DBG("Reading register name %s on MASTER side",GCR_sub_reg_names[pg_reg_list[reg_num]]); + rc=GCR_read(master_chip_target , master_chip_interface, pg_reg_list[reg_num], master_group,0, *MASTER_BUFFERS[reg_num]); + if (rc) + { + FAPI_ERR("io_run_training : Error Reading %s",GCR_sub_reg_names[pg_reg_list[reg_num]]); + } + // Not doing the else here on purpose.. if read on one reg fails , we want to try next and maybe the slave side if all fails + } + + for(uint32_t reg_num=0;reg_num<NUM_PG_REGS;++reg_num){ + FAPI_DBG("Reading register name %s on SLAVE side",GCR_sub_reg_names[pg_reg_list[reg_num]]); + rc=GCR_read(slave_chip_target , slave_chip_interface, pg_reg_list[reg_num], slave_group,0, *SLAVE_BUFFERS[reg_num]); + if (rc) + { + FAPI_ERR("io_run_training : Error Reading %s",GCR_sub_reg_names[pg_reg_list[reg_num]]); + } + // Not doing the else here on purpose.. if read on one reg fails , we want to try next and maybe the slave side if all fails + } + + FAPI_SET_HWP_ERROR(rc,IO_FUNCS_FUNC_FAIL_RC); + return(rc); +} } diff --git a/src/usr/hwpf/hwp/bus_training/io_funcs.H b/src/usr/hwpf/hwp/bus_training/io_funcs.H index c5d061834..3ed1d2a21 100644 --- a/src/usr/hwpf/hwp/bus_training/io_funcs.H +++ b/src/usr/hwpf/hwp/bus_training/io_funcs.H @@ -5,7 +5,7 @@ /* */ /* IBM CONFIDENTIAL */ /* */ -/* COPYRIGHT International Business Machines Corp. 2012,2013 */ +/* COPYRIGHT International Business Machines Corp. 2012,2014 */ /* */ /* p1 */ /* */ @@ -20,7 +20,7 @@ /* Origin: 30 */ /* */ /* IBM_PROLOG_END_TAG */ -// $Id: io_funcs.H,v 1.16 2013/11/25 07:10:39 varkeykv Exp $ +// $Id: io_funcs.H,v 1.17 2014/02/20 13:27:29 varkeykv Exp $ // *!*************************************************************************** // *! (C) Copyright International Business Machines Corp. 1997, 1998 // *! All Rights Reserved -- Property of IBM @@ -139,6 +139,42 @@ public: io_interface_t slave_chip_interface, uint32_t slave_group ); + + // First Fail Data Capture Routines + // Deskew First Fail Data Capture + ReturnCode dump_ffdc_deskew(const Target& master_chip_target, + io_interface_t master_chip_interface , + uint32_t master_group, + const Target& slave_chip_target , + io_interface_t slave_chip_interface, + uint32_t slave_group + ); + + // Eye opt First Fail Data Capture + ReturnCode dump_ffdc_eyeopt(const Target& master_chip_target, + io_interface_t master_chip_interface , + uint32_t master_group, + const Target& slave_chip_target , + io_interface_t slave_chip_interface, + uint32_t slave_group + ); + + // Repair First Fail Data Capture + ReturnCode dump_ffdc_repair(const Target& master_chip_target, + io_interface_t master_chip_interface , + uint32_t master_group, + const Target& slave_chip_target , + io_interface_t slave_chip_interface, + uint32_t slave_group + ); + // FUnc mode First Fail Data Capture + ReturnCode dump_ffdc_func(const Target& master_chip_target, + io_interface_t master_chip_interface , + uint32_t master_group, + const Target& slave_chip_target , + io_interface_t slave_chip_interface, + uint32_t slave_group + ); // Utility functions // Determines if target chip is a Master (reads rx_master_mode bit) diff --git a/src/usr/hwpf/hwp/bus_training/io_funcs_errors.xml b/src/usr/hwpf/hwp/bus_training/io_funcs_errors.xml new file mode 100644 index 000000000..1d34406e4 --- /dev/null +++ b/src/usr/hwpf/hwp/bus_training/io_funcs_errors.xml @@ -0,0 +1,435 @@ +<!-- IBM_PROLOG_BEGIN_TAG --> +<!-- This is an automatically generated prolog. --> +<!-- --> +<!-- $Source: src/usr/hwpf/hwp/bus_training/io_funcs_errors.xml $ --> +<!-- --> +<!-- IBM CONFIDENTIAL --> +<!-- --> +<!-- COPYRIGHT International Business Machines Corp. 2014 --> +<!-- --> +<!-- p1 --> +<!-- --> +<!-- Object Code Only (OCO) source materials --> +<!-- Licensed Internal Code Source Materials --> +<!-- IBM HostBoot Licensed Internal Code --> +<!-- --> +<!-- The source code for this program is not published or otherwise --> +<!-- divested of its trade secrets, irrespective of what has been --> +<!-- deposited with the U.S. Copyright Office. --> +<!-- --> +<!-- Origin: 30 --> +<!-- --> +<!-- IBM_PROLOG_END_TAG --> +<!-- $Id: io_funcs_errors.xml,v 1.4 2014/03/18 14:58:41 jgrell Exp $ --> + +<hwpErrors> + + <!-- **********************TIMEOUT FAILS************************************************* --> + <!-- *********************************************************************** --> + <hwpError> + <rc>IO_FUNCS_WIRETEST_TIMEOUT_RC</rc> + <ffdc>FFDC_NUM_CYCLES</ffdc> + <description>io run training wiretest timed out waiting for pass/fail indication in the p8 or centaur Status Registers</description> + <ffdc>MASTER_CHIP_INTERFACE</ffdc> + <ffdc>MASTER_GROUP</ffdc> + <ffdc>SLAVE_CHIP_INTERFACE</ffdc> + <ffdc>SLAVE_GROUP</ffdc> + <callout> + <target>MASTER_TARGET</target> + <priority>MEDIUM</priority> + </callout> + <callout> + <target>SLAVE_TARGET</target> + <priority>MEDIUM</priority> + </callout> + <callout> + <bus>MASTER_TARGET,SLAVE_TARGET</bus> + <priority>HIGH</priority> + </callout> + <deconfigure> + <target>SLAVE_TARGET</target> + </deconfigure> + <gard> + <target>SLAVE_TARGET</target> + </gard> + </hwpError> + <!-- *********************************************************************** --> + <hwpError> + <rc>IO_FUNCS_DESKEW_TIMEOUT_RC</rc> + <ffdc>FFDC_NUM_CYCLES</ffdc> + <description>io run training deskew timed out waiting for pass/fail indication in the p8 or centaur Status Registers</description> + <ffdc>MASTER_CHIP_INTERFACE</ffdc> + <ffdc>MASTER_GROUP</ffdc> + <ffdc>SLAVE_CHIP_INTERFACE</ffdc> + <ffdc>SLAVE_GROUP</ffdc> + + <callout> + <target>MASTER_TARGET</target> + <priority>MEDIUM</priority> + </callout> + <callout> + <target>SLAVE_TARGET</target> + <priority>MEDIUM</priority> + </callout> + <callout> + <bus>MASTER_TARGET,SLAVE_TARGET</bus> + <priority>HIGH</priority> + </callout> + <deconfigure> + <target>SLAVE_TARGET</target> + </deconfigure> + <gard> + <target>SLAVE_TARGET</target> + </gard> + </hwpError> + <!-- *********************************************************************** --> + <hwpError> + <rc>IO_FUNCS_EYEOPT_TIMEOUT_RC</rc> + <ffdc>FFDC_NUM_CYCLES</ffdc> + <description>io run training Eyeopt timed out waiting for pass/fail indication in the p8 or centaur Status Registers</description> + <ffdc>MASTER_CHIP_INTERFACE</ffdc> + <ffdc>MASTER_GROUP</ffdc> + <ffdc>SLAVE_CHIP_INTERFACE</ffdc> + <ffdc>SLAVE_GROUP</ffdc> + <callout> + <target>MASTER_TARGET</target> + <priority>MEDIUM</priority> + </callout> + <callout> + <target>SLAVE_TARGET</target> + <priority>MEDIUM</priority> + </callout> + <callout> + <bus>MASTER_TARGET,SLAVE_TARGET</bus> + <priority>HIGH</priority> + </callout> + <deconfigure> + <target>SLAVE_TARGET</target> + </deconfigure> + <gard> + <target>SLAVE_TARGET</target> + </gard> + </hwpError> + <!-- *********************************************************************** --> + <hwpError> + <rc>IO_FUNCS_REPAIR_TIMEOUT_RC</rc> + <ffdc>FFDC_NUM_CYCLES</ffdc> + <description>io run training repair timed out waiting for pass/fail indication in the p8 or centaur Status Registers</description> + <ffdc>MASTER_CHIP_INTERFACE</ffdc> + <ffdc>MASTER_GROUP</ffdc> + <ffdc>SLAVE_CHIP_INTERFACE</ffdc> + <ffdc>SLAVE_GROUP</ffdc> + <callout> + <target>MASTER_TARGET</target> + <priority>MEDIUM</priority> + </callout> + <callout> + <target>SLAVE_TARGET</target> + <priority>MEDIUM</priority> + </callout> + <callout> + <bus>MASTER_TARGET,SLAVE_TARGET</bus> + <priority>HIGH</priority> + </callout> + <deconfigure> + <target>SLAVE_TARGET</target> + </deconfigure> + <gard> + <target>SLAVE_TARGET</target> + </gard> + </hwpError> + <!-- *********************************************************************** --> + <hwpError> + <rc>IO_FUNCS_FUNC_MODE_TIMEOUT_RC</rc> + <ffdc>FFDC_NUM_CYCLES</ffdc> + <description>io run training functional mode timed out waiting for pass/fail indication in the p8 or centaur Status Registers</description> + <ffdc>MASTER_CHIP_INTERFACE</ffdc> + <ffdc>MASTER_GROUP</ffdc> + <ffdc>SLAVE_CHIP_INTERFACE</ffdc> + <ffdc>SLAVE_GROUP</ffdc> + <callout> + <target>MASTER_TARGET</target> + <priority>MEDIUM</priority> + </callout> + <callout> + <target>SLAVE_TARGET</target> + <priority>MEDIUM</priority> + </callout> + <callout> + <bus>MASTER_TARGET,SLAVE_TARGET</bus> + <priority>HIGH</priority> + </callout> + <deconfigure> + <target>SLAVE_TARGET</target> + </deconfigure> + <gard> + <target>SLAVE_TARGET</target> + </gard> + </hwpError> + <!-- *********************************************************************** --> + + <!-- *********************************************************************** --> + <hwpError> + <rc>IO_FUNCS_WIRETEST_FAIL_RC</rc> + <description>Wiretest Training fail was reported in a P8 or Centaur status register</description> + <ffdc>MASTER_CHIP_INTERFACE</ffdc> + <ffdc>MASTER_GROUP</ffdc> + <ffdc>SLAVE_CHIP_INTERFACE</ffdc> + <ffdc>SLAVE_GROUP</ffdc> + <ffdc>MASTER_RX_LANE_DISABLED_VEC_0_15_PG</ffdc> + <ffdc>MASTER_RX_LANE_DISABLED_VEC_16_31_PG</ffdc> + <ffdc>MASTER_RX_LANE_SWAPPED_VEC_0_15_PG</ffdc> + <ffdc>MASTER_RX_INIT_STATE_PG</ffdc> + <ffdc>MASTER_RX_WIRETEST_STATE_PG</ffdc> + <ffdc>MASTER_RX_WIRETEST_LANEINFO_PG</ffdc> + <ffdc>MASTER_RX_TRAINING_STATUS_PG</ffdc> + <ffdc>MASTER_RX_WT_CLK_STATUS_PG</ffdc> + <ffdc>SLAVE_RX_LANE_DISABLED_VEC_0_15_PG</ffdc> + <ffdc>SLAVE_RX_LANE_DISABLED_VEC_16_31_PG</ffdc> + <ffdc>SLAVE_RX_LANE_SWAPPED_VEC_0_15_PG</ffdc> + <ffdc>SLAVE_RX_INIT_STATE_PG</ffdc> + <ffdc>SLAVE_RX_WIRETEST_STATE_PG</ffdc> + <ffdc>SLAVE_RX_WIRETEST_LANEINFO_PG</ffdc> + <ffdc>SLAVE_RX_TRAINING_STATUS_PG</ffdc> + <ffdc>SLAVE_RX_WT_CLK_STATUS_PG</ffdc> + <callout> + <target>MASTER_TARGET</target> + <priority>MEDIUM</priority> + </callout> + <callout> + <target>SLAVE_TARGET</target> + <priority>MEDIUM</priority> + </callout> + <callout> + <bus>MASTER_TARGET,SLAVE_TARGET</bus> + <priority>HIGH</priority> + </callout> + <deconfigure> + <target>SLAVE_TARGET</target> + </deconfigure> + <gard> + <target>SLAVE_TARGET</target> + </gard> + </hwpError> + + + <hwpError> + <rc>IO_FUNCS_WIRETEST_FAIL_LANE_MASTER_DATA_RC</rc> + <description>FFDC for Wiretest failure in training ( PER LANE MASTER DATA ) </description> + <ffdc>CHIP_TARGET</ffdc> + <ffdc>LANEID</ffdc> + <ffdc>RX_WT_STATUS_PL</ffdc> + </hwpError> + + <hwpError> + <rc>IO_FUNCS_WIRETEST_FAIL_LANE_SLAVE_DATA_RC</rc> + <description>FFDC for Wiretest failure in training (PER LANE SLAVE DATA ) </description> + <ffdc>CHIP_TARGET</ffdc> + <ffdc>LANEID</ffdc> + <ffdc>RX_WT_STATUS_PL</ffdc> + </hwpError> + + <!-- ********************DESKEW *************************************************** --> + + <hwpError> + <rc>IO_FUNCS_DESKEW_FAIL_RC</rc> + <description>Deskew Training fail was reported in a P8 or Centaur status register</description> + <ffdc>MASTER_CHIP_INTERFACE</ffdc> + <ffdc>MASTER_GROUP</ffdc> + <ffdc>SLAVE_CHIP_INTERFACE</ffdc> + <ffdc>SLAVE_GROUP</ffdc> + <ffdc>MASTER_RX_INIT_STATE_PG</ffdc> + <ffdc>MASTER_RX_TRAINING_STATUS_PG</ffdc> + <ffdc>MASTER_RX_DESKEW_STATE_PG</ffdc> + <ffdc>MASTER_RX_LANE_BAD_0_15_PG</ffdc> + <ffdc>MASTER_RX_LANE_BAD_16_31_PG</ffdc> + <ffdc>SLAVE_RX_INIT_STATE_PG</ffdc> + <ffdc>SLAVE_RX_TRAINING_STATUS_PG</ffdc> + <ffdc>SLAVE_RX_DESKEW_STATE_PG</ffdc> + <ffdc>SLAVE_RX_LANE_BAD_0_15_PG</ffdc> + <ffdc>SLAVE_RX_LANE_BAD_16_31_PG</ffdc> + <callout> + <target>MASTER_TARGET</target> + <priority>MEDIUM</priority> + </callout> + <callout> + <target>SLAVE_TARGET</target> + <priority>MEDIUM</priority> + </callout> + <callout> + <bus>MASTER_TARGET,SLAVE_TARGET</bus> + <priority>HIGH</priority> + </callout> + <deconfigure> + <target>SLAVE_TARGET</target> + </deconfigure> + <gard> + <target>SLAVE_TARGET</target> + </gard> + </hwpError> + + + + <hwpError> + <rc>IO_FUNCS_DESKEW_FAIL_LANE_MASTER_DATA_RC</rc> + <description>FFDC for Deskew in training ( PER LANE MASTER DATA )</description> + <ffdc>CHIP_TARGET</ffdc> + <ffdc>LANEID</ffdc> + <ffdc>RX_DESKEW_STAT_PL</ffdc> + <ffdc>RX_STAT_PL</ffdc> + <ffdc>RX_VREF_PL</ffdc> + <ffdc>RX_FIFO_STAT_PL</ffdc> + <ffdc>RX_PROT_STATUS_PL</ffdc> + </hwpError> + + <hwpError> + <rc>IO_FUNCS_DESKEW_FAIL_LANE_SLAVE_DATA_RC</rc> + <description>FFDC for Deskew in training ( PER LANE SLAVE DATA )</description> + <ffdc>CHIP_TARGET</ffdc> + <ffdc>LANEID</ffdc> + <ffdc>RX_DESKEW_STAT_PL</ffdc> + <ffdc>RX_STAT_PL</ffdc> + <ffdc>RX_VREF_PL</ffdc> + <ffdc>RX_FIFO_STAT_PL</ffdc> + <ffdc>RX_PROT_STATUS_PL</ffdc> + </hwpError> + + <!-- ********************EYEOPT*************************************************** --> + <hwpError> + <rc>IO_FUNCS_EYEOPT_FAIL_RC</rc> + <description>Eye Optimization Training fail was reported in a P8 or Centaur status register</description> + <ffdc>MASTER_CHIP_INTERFACE</ffdc> + <ffdc>MASTER_GROUP</ffdc> + <ffdc>SLAVE_CHIP_INTERFACE</ffdc> + <ffdc>SLAVE_GROUP</ffdc> + <ffdc>MASTER_RX_TRAINING_STATUS_PG</ffdc> + <ffdc>MASTER_RX_EO_RECAL_PG</ffdc> + <ffdc>MASTER_RX_LANE_BAD_0_15_PG</ffdc> + <ffdc>MASTER_RX_LANE_BAD_16_31_PG</ffdc> + <ffdc>SLAVE_RX_TRAINING_STATUS_PG</ffdc> + <ffdc>SLAVE_RX_EO_RECAL_PG</ffdc> + <ffdc>SLAVE_RX_LANE_BAD_0_15_PG</ffdc> + <ffdc>SLAVE_RX_LANE_BAD_16_31_PG</ffdc> + <callout> + <target>MASTER_TARGET</target> + <priority>MEDIUM</priority> + </callout> + <callout> + <target>SLAVE_TARGET</target> + <priority>MEDIUM</priority> + </callout> + <callout> + <bus>MASTER_TARGET,SLAVE_TARGET</bus> + <priority>HIGH</priority> + </callout> + <deconfigure> + <target>SLAVE_TARGET</target> + </deconfigure> + <gard> + <target>SLAVE_TARGET</target> + </gard> + </hwpError> + + + <hwpError> + <rc>IO_FUNCS_EYEOPT_FAIL_LANE_MASTER_DATA_RC</rc> + <description>FFDC for Deskew in training ( PER LANE MASTER DATA )</description> + <ffdc>CHIP_TARGET</ffdc> + <ffdc>LANEID</ffdc> + <ffdc>RX_AP_PL</ffdc> + <ffdc>RX_AN_PL</ffdc> + <ffdc>RX_AMIN_PL</ffdc> + <ffdc>RX_H1_EVEN_PL</ffdc> + <ffdc>RX_H1_ODD_PL</ffdc> + <ffdc>RX_EYE_OPT_STATE_PL</ffdc> + <ffdc>RX_EYE_WIDTH_STATUS_PL</ffdc> + <ffdc>RX_DCD_ADJ_PL</ffdc> + + </hwpError> + + <hwpError> + <rc>IO_FUNCS_EYEOPT_FAIL_LANE_SLAVE_DATA_RC</rc> + <description>FFDC for Deskew in training ( PER LANE SLAVE DATA )</description> + <ffdc>CHIP_TARGET</ffdc> + <ffdc>LANEID</ffdc> + <ffdc>RX_AP_PL</ffdc> + <ffdc>RX_AN_PL</ffdc> + <ffdc>RX_AMIN_PL</ffdc> + <ffdc>RX_H1_EVEN_PL</ffdc> + <ffdc>RX_H1_ODD_PL</ffdc> + <ffdc>RX_EYE_OPT_STATE_PL</ffdc> + <ffdc>RX_EYE_WIDTH_STATUS_PL</ffdc> + <ffdc>RX_DCD_ADJ_PL</ffdc> + + </hwpError> + + + <!-- ********************REPAIR *************************************************** --> + <hwpError> + <rc>IO_FUNCS_REPAIR_FAIL_RC</rc> + <description>Static Repair Training fail was reported in a P8 or Centaur status register</description> + <ffdc>MASTER_CHIP_INTERFACE</ffdc> + <ffdc>MASTER_GROUP</ffdc> + <ffdc>SLAVE_CHIP_INTERFACE</ffdc> + <ffdc>SLAVE_GROUP</ffdc> + <ffdc>MASTER_RX_STATIC_REPAIR_STATE_PG</ffdc> + <ffdc>MASTER_RX_TRAINING_STATUS_PG</ffdc> + <ffdc>MASTER_RX_BAD_LANE_ENC_GCRMSG_PG</ffdc> + <ffdc>SLAVE_RX_STATIC_REPAIR_STATE_PG</ffdc> + <ffdc>SLAVE_RX_TRAINING_STATUS_PG</ffdc> + <ffdc>SLAVE_RX_BAD_LANE_ENC_GCRMSG_PG</ffdc> + <callout> + <target>MASTER_TARGET</target> + <priority>MEDIUM</priority> + </callout> + <callout> + <target>SLAVE_TARGET</target> + <priority>MEDIUM</priority> + </callout> + <callout> + <bus>MASTER_TARGET,SLAVE_TARGET</bus> + <priority>HIGH</priority> + </callout> + <deconfigure> + <target>SLAVE_TARGET</target> + </deconfigure> + <gard> + <target>SLAVE_TARGET</target> + </gard> + </hwpError> + + + <!-- ********************FUNC MODE *************************************************** --> + <hwpError> + <rc>IO_FUNCS_FUNC_FAIL_RC</rc> + <description>Functional mode Training fail was reported in a P8 or Centaur status register</description> + <ffdc>MASTER_CHIP_INTERFACE</ffdc> + <ffdc>MASTER_GROUP</ffdc> + <ffdc>SLAVE_CHIP_INTERFACE</ffdc> + <ffdc>SLAVE_GROUP</ffdc> + <ffdc>MASTER_RX_FUNC_STATE_PG</ffdc> + <ffdc>MASTER_RX_TRAINING_STATUS_PG</ffdc> + <ffdc>SLAVE_RX_FUNC_STATE_PG</ffdc> + <ffdc>SLAVE_RX_TRAINING_STATUS_PG</ffdc> + <callout> + <target>MASTER_TARGET</target> + <priority>MEDIUM</priority> + </callout> + <callout> + <target>SLAVE_TARGET</target> + <priority>MEDIUM</priority> + </callout> + <callout> + <bus>MASTER_TARGET,SLAVE_TARGET</bus> + <priority>HIGH</priority> + </callout> + <deconfigure> + <target>SLAVE_TARGET</target> + </deconfigure> + <gard> + <target>SLAVE_TARGET</target> + </gard> + </hwpError> + + + </hwpErrors> diff --git a/src/usr/hwpf/hwp/bus_training/io_power_down_lanes.C b/src/usr/hwpf/hwp/bus_training/io_power_down_lanes.C index 4133f68a5..7b7675652 100644 --- a/src/usr/hwpf/hwp/bus_training/io_power_down_lanes.C +++ b/src/usr/hwpf/hwp/bus_training/io_power_down_lanes.C @@ -20,7 +20,7 @@ /* Origin: 30 */ /* */ /* IBM_PROLOG_END_TAG */ -// $Id: io_power_down_lanes.C,v 1.12 2014/02/14 09:04:48 varkeykv Exp $ +// $Id: io_power_down_lanes.C,v 1.13 2014/03/06 11:12:24 varkeykv Exp $ // *!*************************************************************************** // *! (C) Copyright International Business Machines Corp. 1997, 1998 // *! All Rights Reserved -- Property of IBM @@ -35,7 +35,7 @@ // *! BACKUP NAME : Swaminathan, Janani Email: jaswamin@in.ibm.com // *! // *!*************************************************************************** -// CHANGE HISTORY: +// CHANGE HISTORY: //------------------------------------------------------------------------------ // Version:|Author: | Date: | Comment: // --------|--------|--------|-------------------------------------------------- @@ -60,159 +60,171 @@ using namespace fapi; ReturnCode io_power_down_lanes(const Target& target,const std::vector<uint8_t> &tx_lanes,const std::vector<uint8_t> &rx_lanes) { - ReturnCode rc; - ecmdDataBufferBase data(16); - ecmdDataBufferBase mask(16); - ecmdDataBufferBase mode_reg(16); - uint8_t lane=0; - bool msbswap=false; - const uint8_t xbus_lanes_per_group=20; - uint8_t end_lane=0; + ReturnCode rc; + ecmdDataBufferBase data(16); + ecmdDataBufferBase mask(16); + ecmdDataBufferBase mode_reg(16); + uint8_t lane=0; + bool msbswap=false; + const uint8_t xbus_lanes_per_group=20; + uint8_t end_lane=0; - io_interface_t interface=CP_IOMC0_P0; // Since G - uint32_t rc_ecmd=0; - uint8_t clock_group=0; - uint8_t start_group=0; - - rc_ecmd=mask.flushTo1(); - if(rc_ecmd) - { - rc.setEcmdError(rc_ecmd); - return(rc); - } - // Both TX and RX power down bits are on bit 0 - rc_ecmd=mask.clearBit(0); - if(rc_ecmd) - { - rc.setEcmdError(rc_ecmd); - return(rc); - } + io_interface_t interface=CP_IOMC0_P0; // Since G + uint32_t rc_ecmd=0; + uint8_t clock_group=0; + uint8_t start_group=0; + + do + { + // Both TX and RX power down bits are on bit 0 + rc_ecmd=mask.flushTo1(); + rc_ecmd=mask.clearBit(0); + if(rc_ecmd) + { + FAPI_ERR("io_power_down_lanes error occured while" + " flushing and clearing bits for mask"); + rc.setEcmdError(rc_ecmd); + break; + } - // Check which type of bus this is and do setup needed - if(target.getType() == fapi::TARGET_TYPE_ABUS_ENDPOINT) { - start_group=0; - interface=CP_FABRIC_A0; // base scom for A bus , assume translation to A1 by PLAT - } - else if(target.getType() == fapi::TARGET_TYPE_XBUS_ENDPOINT ) { - start_group=0; - interface=CP_FABRIC_X0; // base scom for X bus - } - else if(target.getType() == fapi::TARGET_TYPE_MCS_CHIPLET){ - start_group=3; - interface=CP_IOMC0_P0; // base scom for MC bus - } - else if(target.getType() == fapi::TARGET_TYPE_MEMBUF_CHIP){ - start_group=0; - interface=CEN_DMI; // base scom Centaur chip - } - else{ - FAPI_ERR("Invalid io_power_down_lanes HWP invocation"); - FAPI_SET_HWP_ERROR(rc, IO_RUN_TRAINING_INVALID_INVOCATION_RC); - return(rc); - } + // Check which type of bus this is and do setup needed + fapi::TargetType l_type= target.getType(); + switch (l_type) + { + case fapi::TARGET_TYPE_ABUS_ENDPOINT: + start_group=0; + interface=CP_FABRIC_A0; // base scom for A bus , assume translation to A1 by PLAT + break; + case fapi::TARGET_TYPE_XBUS_ENDPOINT: + start_group=0; + interface=CP_FABRIC_X0; // base scom for X bus + break; + case fapi::TARGET_TYPE_MCS_CHIPLET: + start_group=3; + interface=CP_IOMC0_P0; // base scom for MC bus + break; + case fapi::TARGET_TYPE_MEMBUF_CHIP: + start_group=0; + interface=CEN_DMI; // base scom Centaur chip + break; + default: + FAPI_ERR("Invalid io_power_down_lanes HWP invocation"); + const fapi::Target &TARGET=target; + FAPI_SET_HWP_ERROR(rc, IO_POWER_DOWN_LANES_INVALID_INVOCATION_RC); + break; + } + if (rc) + { + break; + } - FAPI_INF("Power down IO lanes\n"); + FAPI_INF("Power down IO lanes\n"); - rc_ecmd|=data.flushTo0(); - rc_ecmd|=data.setBit(0); // Power down is on bit 0 always - - if(rc_ecmd) - { - rc.setEcmdError(rc_ecmd); - return(rc); - } + rc_ecmd|=data.flushTo0(); + rc_ecmd|=data.setBit(0); // Power down is on bit 0 always + if(rc_ecmd) + { + FAPI_ERR("io_power_down_lanes error occured while" + " flushing and clearing bits for data"); + rc.setEcmdError(rc_ecmd); + break; + } - rc = GCR_read( target, interface,tx_mode_pg, start_group, 0, mode_reg); - if(rc){return rc;} + rc = GCR_read( target, interface,tx_mode_pg, start_group, 0, mode_reg); + if(rc) + { + FAPI_ERR("GCR_read returned an error while reading tx_mode_pg"); + break; + } - if(mode_reg.isBitSet(5)){ - FAPI_DBG("TX MSB-LSB SWAP MODE ON on this target %d \n",tx_end_lane_id); - msbswap=true; - } + if(mode_reg.isBitSet(5)) + { + FAPI_DBG("TX MSB-LSB SWAP MODE ON on this target %d \n",tx_end_lane_id); + msbswap=true; + } - //TX Lanes power down - for(uint8_t i=0;i<tx_lanes.size();++i){ - lane=tx_lanes[i]; - //For Xbus figure out the clock group number - if(interface==CP_FABRIC_X0){ - clock_group=start_group; - while(lane>(xbus_lanes_per_group-1)){ - lane=lane-xbus_lanes_per_group; - clock_group++; - } - } - else{ - clock_group=start_group; - // MSBLSB SWAP condition can be there in MC or A - if(msbswap){ - // We can read out tx_end_lane_id now for swap correction - rc = GCR_read( target, interface,tx_id3_pg, clock_group, 0, mode_reg); - if(rc){return rc;} - rc_ecmd=mode_reg.extract(&end_lane,9,7); - if(rc_ecmd) - { - rc.setEcmdError(rc_ecmd); - return(rc); - } - end_lane=end_lane>>1;// move left aligned extract by 1 - FAPI_DBG("END lane id is %d\n",end_lane); - lane=end_lane-tx_lanes[i]; // GFW VPD does not know about MSBSWAP , this adjusts for swapping - } - } - //Power down this lane - rc = GCR_read( target,interface,tx_mode_pl, clock_group, lane, data); - if(rc){return rc;} - FAPI_DBG("read out tx_mode_pl successfully for clock group%d lane %d",clock_group,lane); - rc_ecmd=data.setBit(0); - if(rc_ecmd) - { - rc.setEcmdError(rc_ecmd); - return(rc); - } - rc = GCR_write( target, interface, tx_mode_pl, clock_group, lane, data,mask ); - if(rc){return rc;} - FAPI_DBG("Wrote tx_mode_pl successfullyfor clock group%d lane %d",clock_group,lane); - } + //TX Lanes power down + for(uint8_t i=0;i<tx_lanes.size();++i) + { + lane=tx_lanes[i]; + //For Xbus figure out the clock group number + if(interface==CP_FABRIC_X0) + { + clock_group=start_group; + while(lane>(xbus_lanes_per_group-1)) + { + lane=lane-xbus_lanes_per_group; + clock_group++; + } + } + else + { + clock_group=start_group; + // MSBLSB SWAP condition can be there in MC or A + if(msbswap) + { + // We can read out tx_end_lane_id now for swap correction + rc = GCR_read( target, interface,tx_id3_pg, clock_group, 0, mode_reg); + if(rc) + { + FAPI_ERR("GCR_read returned an error during call to read tx_id3_pg"); + break; + } + + rc_ecmd=mode_reg.extract(&end_lane,9,7); + if(rc_ecmd) + { + rc.setEcmdError(rc_ecmd); + break; + } + end_lane=end_lane>>1;// move left aligned extract by 1 + FAPI_DBG("END lane id is %d\n",end_lane); + lane=end_lane-tx_lanes[i]; // GFW VPD does not know about MSBSWAP , this adjusts for swapping + } + } + + //Power down this lane + rc = GCR_write( target, interface, tx_mode_pl, clock_group, lane, data,mask ); + if(rc) + { + FAPI_ERR("GCR_write returned an error while writing tx_mode_pl"); + break; + } + } - // Process RX lane powerdown - for(uint8_t i=0;i<rx_lanes.size();++i){ - lane=rx_lanes[i]; - //For X bus set the right clock group number - if(interface==CP_FABRIC_X0){ - clock_group=start_group; - while(lane>(xbus_lanes_per_group-1)){ - lane=lane-xbus_lanes_per_group; - clock_group++; - } - } - else{ - clock_group=start_group; - } - //Power down this lane - rc = GCR_read( target,interface,rx_mode_pl, clock_group, lane, data); - if(rc){return rc;} - rc_ecmd=data.setBit(0); - if(rc_ecmd) - { - rc.setEcmdError(rc_ecmd); - return(rc); - } - rc = GCR_write( target, interface, rx_mode_pl, clock_group, lane, data,mask ); - if(rc){return rc;} - FAPI_DBG("Read rx_mode_pl successfully for clock group%d lane %d",clock_group,lane); - // As per Gary/ Defect SW244284 , as per Design team inputs add rx_wt_lane_disabled - rc = GCR_read( target,interface, rx_wt_status_pl, clock_group, lane, data); - if(rc){return rc;} - rc_ecmd=data.setBit(0); - if(rc_ecmd) - { - rc.setEcmdError(rc_ecmd); - return(rc); - } - rc = GCR_write( target, interface, rx_wt_status_pl, clock_group, lane, data,mask ); - FAPI_DBG("Wrote rx_mode_pl successfully for clock group%d lane %d",clock_group,lane); - } - return rc; + //break out of larger while loop + if (rc) + { + break; + } + // Process RX lane powerdown + for(uint8_t i=0;i<rx_lanes.size();++i) + { + lane=rx_lanes[i]; + //For X bus set the right clock group number + if(interface==CP_FABRIC_X0) + { + clock_group=start_group; + while(lane>(xbus_lanes_per_group-1)) + { + lane=lane-xbus_lanes_per_group; + clock_group++; + } + } + else + { + clock_group=start_group; + } + //Power down this lane + rc = GCR_write( target, interface, rx_mode_pl, clock_group, lane, data,mask ); + if(rc) + { + FAPI_ERR("GCR_write returned an error while writing rx_mode_pl"); + break; + } + } + }while(0); + return rc; } } //end extern C diff --git a/src/usr/hwpf/hwp/bus_training/io_power_down_lanes.H b/src/usr/hwpf/hwp/bus_training/io_power_down_lanes.H index 7db744d37..9cb3e2b3b 100644 --- a/src/usr/hwpf/hwp/bus_training/io_power_down_lanes.H +++ b/src/usr/hwpf/hwp/bus_training/io_power_down_lanes.H @@ -1,11 +1,11 @@ /* IBM_PROLOG_BEGIN_TAG */ /* This is an automatically generated prolog. */ /* */ -/* $Source: src/usr/hwpf/hwp/io_power_down_lanes/io_power_down_lanes.H $ */ +/* $Source: src/usr/hwpf/hwp/bus_training/io_power_down_lanes.H $ */ /* */ /* IBM CONFIDENTIAL */ /* */ -/* COPYRIGHT International Business Machines Corp. 2013 */ +/* COPYRIGHT International Business Machines Corp. 2013,2014 */ /* */ /* p1 */ /* */ @@ -20,12 +20,12 @@ /* Origin: 30 */ /* */ /* IBM_PROLOG_END_TAG */ -// $Id: io_power_down_lanes.H,v 1.4 2013/02/12 07:32:04 varkeykv Exp $ +// $Id: io_power_down_lanes.H,v 1.5 2014/03/06 11:12:24 varkeykv Exp $ #ifndef IO_POWER_DOWN_LANES_H_ #define IO_POWER_DOWN_LANES_H_ -#include <fapi.H> +#include <fapi.H> /** * @brief IO Power down lanes diff --git a/src/usr/hwpf/hwp/bus_training/io_power_down_lanes_errors.xml b/src/usr/hwpf/hwp/bus_training/io_power_down_lanes_errors.xml new file mode 100644 index 000000000..11f5d44a9 --- /dev/null +++ b/src/usr/hwpf/hwp/bus_training/io_power_down_lanes_errors.xml @@ -0,0 +1,37 @@ +<!-- IBM_PROLOG_BEGIN_TAG --> +<!-- This is an automatically generated prolog. --> +<!-- --> +<!-- $Source: src/usr/hwpf/hwp/bus_training/io_power_down_lanes_errors.xml $ --> +<!-- --> +<!-- IBM CONFIDENTIAL --> +<!-- --> +<!-- COPYRIGHT International Business Machines Corp. 2014 --> +<!-- --> +<!-- p1 --> +<!-- --> +<!-- Object Code Only (OCO) source materials --> +<!-- Licensed Internal Code Source Materials --> +<!-- IBM HostBoot Licensed Internal Code --> +<!-- --> +<!-- The source code for this program is not published or otherwise --> +<!-- divested of its trade secrets, irrespective of what has been --> +<!-- deposited with the U.S. Copyright Office. --> +<!-- --> +<!-- Origin: 30 --> +<!-- --> +<!-- IBM_PROLOG_END_TAG --> +<!-- $Id: io_power_down_lanes_errors.xml,v 1.2 2014/03/18 14:58:41 jgrell Exp $ --> + +<!-- Error definitions for io_power_down_lanes.o_power_down_lanes.CC --> +<hwpErrors> + <!-- *********************************************************************** --> + <hwpError> + <rc>IO_POWER_DOWN_LANES_INVALID_INVOCATION_RC</rc> + <description>io_power_down_lanes invoked with incorrect target type</description> + <ffdc>TARGET</ffdc> + <callout> + <procedure>CODE</procedure> + <priority>HIGH</priority> + </callout> + </hwpError> +</hwpErrors> diff --git a/src/usr/hwpf/hwp/bus_training/io_read_erepair.C b/src/usr/hwpf/hwp/bus_training/io_read_erepair.C index 16aae79d8..0aa7a399a 100644 --- a/src/usr/hwpf/hwp/bus_training/io_read_erepair.C +++ b/src/usr/hwpf/hwp/bus_training/io_read_erepair.C @@ -20,7 +20,7 @@ /* Origin: 30 */ /* */ /* IBM_PROLOG_END_TAG */ -// $Id: io_read_erepair.C,v 1.9 2014/02/04 15:16:02 varkeykv Exp $ +// $Id: io_read_erepair.C,v 1.11 2014/03/06 11:44:04 varkeykv Exp $ // *!*************************************************************************** // *! (C) Copyright International Business Machines Corp. 1997, 1998 // *! All Rights Reserved -- Property of IBM @@ -59,118 +59,133 @@ using namespace fapi; */ ReturnCode io_read_erepair(const Target& target,std::vector<uint8_t> &rx_lanes) { - ReturnCode rc; - ecmdDataBufferBase data_one(16); - ecmdDataBufferBase mask(16); - uint8_t lane=0; + ReturnCode rc; + ecmdDataBufferBase data_one(16); + ecmdDataBufferBase mask(16); + uint8_t lane=0; - io_interface_t interface=CP_IOMC0_P0; // Since G - uint32_t rc_ecmd=0; - uint8_t start_group=0; - uint8_t end_group=0; + io_interface_t interface=CP_IOMC0_P0; // Since G + uint32_t rc_ecmd=0; + uint8_t start_group=0; + uint8_t end_group=0; + const fapi::Target &TARGET=target; + rc_ecmd=mask.flushTo1(); + if(rc_ecmd) + { + rc.setEcmdError(rc_ecmd); + return(rc); + } - rc_ecmd=mask.flushTo1(); - if(rc_ecmd) - { - rc.setEcmdError(rc_ecmd); - return(rc); - } - - // Check which type of bus this is and do setup needed - if(target.getType() == fapi::TARGET_TYPE_ABUS_ENDPOINT) { - start_group=0; - end_group=0; - interface=CP_FABRIC_A0; // base scom for A bus , assume translation to A1 by PLAT - } - else if(target.getType() == fapi::TARGET_TYPE_XBUS_ENDPOINT ) { - start_group=0; - end_group=0; - interface=CP_FABRIC_X0; // base scom for X bus - } - else if(target.getType() == fapi::TARGET_TYPE_MCS_CHIPLET){ - start_group=3; - end_group=3; - interface=CP_IOMC0_P0; // base scom for MC bus - } - else if(target.getType() == fapi::TARGET_TYPE_MEMBUF_CHIP){ - start_group=0; - end_group=0; - interface=CEN_DMI; // base scom Centaur chip - } - else{ - FAPI_ERR("Invalid io_read_erepair HWP invocation"); - FAPI_SET_HWP_ERROR(rc, IO_RUN_TRAINING_INVALID_INVOCATION_RC); - return(rc); - } + // Check which type of bus this is and do setup needed + fapi::TargetType l_type = target.getType(); + switch (l_type) + { + case fapi::TARGET_TYPE_ABUS_ENDPOINT: + start_group=0; + end_group=0; + interface=CP_FABRIC_A0; // base scom for A bus , assume translation to A1 by PLAT + break; + case fapi::TARGET_TYPE_XBUS_ENDPOINT: + start_group=0; + end_group=3; + interface=CP_FABRIC_X0; // base scom for X bus + break; + case fapi::TARGET_TYPE_MCS_CHIPLET: + start_group=3; + end_group=3; + interface=CP_IOMC0_P0; // base scom for MC bus + break; + case fapi::TARGET_TYPE_MEMBUF_CHIP: + start_group=0; + end_group=0; + interface=CEN_DMI; // base scom Centaur chip + break; + default: + FAPI_ERR("Invalid io_read_erepair HWP invocation"); + FAPI_SET_HWP_ERROR(rc, IO_READ_EREPAIR_INVALID_INVOCATION_RC); + break; + } + if (rc) + { + return(rc); + } - FAPI_INF("Reading erepair data \n"); + FAPI_INF("Reading erepair data \n"); - for(uint8_t clock_group=start_group;clock_group<=end_group;++clock_group){ - // This is only for X bus ..where multi groups are translated to consecutive lane numbers - if(interface==CP_FABRIC_X0){ - if(clock_group==0){ - lane=0; - } - else if(clock_group==1){ - lane=20; - } - else if(clock_group==2){ - lane=40; - } - else if(clock_group==3){ - lane=60; - } - } + for(uint8_t clock_group=start_group;clock_group<=end_group;++clock_group) + { + // This is only for X bus ..where multi groups are translated to consecutive lane numbers + if(interface==CP_FABRIC_X0) + { + switch (clock_group) + { + case 0: + lane=0; + break; + case 1: + lane=20; + break; + case 2: + lane=40; + break; + case 3: + lane=60; + break; + default: + //don't need to do anything? + FAPI_ERR("io_read_erepair has a non-known clock groupd"); + break; + } + } - //Collect the RX bad lanes - rc_ecmd|=data_one.flushTo0(); + //Collect the RX bad lanes + rc_ecmd|=data_one.flushTo0(); - if(rc_ecmd) - { - rc.setEcmdError(rc_ecmd); - return(rc); - } - - rc = GCR_read( target, interface, rx_bad_lane_enc_gcrmsg_pg, clock_group, 0, data_one); - if(rc){return rc;} - - // RX lane records - // Set the RX bad lanes in the RX vector - uint8_t status=0; + if(rc_ecmd) + { + FAPI_ERR("io_read_erepair hit an error while flushing data"); + rc.setEcmdError(rc_ecmd); + return(rc); + } - // Get first bad lane - data_one.extract(&status,14,2); - status=status>>6; - FAPI_DBG("Bad lane status is %d",status); - - if(status!=0){ - if(status>=1){ - if(!data_one.isBitClear(0,7)) - { - data_one.extract(&lane,0,7); - lane=lane>>1; - FAPI_DBG("First bad lane is %d",lane); - rx_lanes.push_back(lane); // 0 to 15 bad lanes - } - } - // Get second bad lane if any - if(status>=2){ - if(!data_one.isBitClear(7,7)){ - data_one.extract(&lane,7,7); - lane=lane>>1; - FAPI_DBG("Second bad lane is %d",lane); - rx_lanes.push_back(lane); // 16 to 31 bad lanes - } - } - } - else{ - // No bad lanes to report - FAPI_DBG("No bad lane to report!!"); - } + rc = GCR_read( target, interface, rx_bad_lane_enc_gcrmsg_pg, clock_group, 0, data_one); + if(rc) + { + FAPI_ERR("io_read_erepair hit an error while writing rx_bad_lane_enc_gcrmsg_pg"); + return(rc); + } + // RX lane records + // Set the RX bad lanes in the RX vector + uint8_t status=0; + + // Get first bad lane + data_one.extract(&status,14,2); + status=status>>6; + FAPI_DBG("Bad lane status is %d",status); + + if(status!=0){ + if(status>=1){ + data_one.extract(&lane,0,7); + lane=lane>>1; + FAPI_DBG("First bad lane is %d",lane); + rx_lanes.push_back(lane); // 0 to 15 bad lanes + } + // Get second bad lane if any + if(status>=2){ + data_one.extract(&lane,7,7); + lane=lane>>1; + FAPI_DBG("Second bad lane is %d",lane); + rx_lanes.push_back(lane); // 16 to 31 bad lanes + } + } + else{ + // No bad lanes to report + FAPI_DBG("No bad lane to report!!"); + } - } - return rc; + } + return rc; } } //end extern C diff --git a/src/usr/hwpf/hwp/bus_training/io_read_erepair_errors.xml b/src/usr/hwpf/hwp/bus_training/io_read_erepair_errors.xml new file mode 100644 index 000000000..6aa602eeb --- /dev/null +++ b/src/usr/hwpf/hwp/bus_training/io_read_erepair_errors.xml @@ -0,0 +1,37 @@ +<!-- IBM_PROLOG_BEGIN_TAG --> +<!-- This is an automatically generated prolog. --> +<!-- --> +<!-- $Source: src/usr/hwpf/hwp/bus_training/io_read_erepair_errors.xml $ --> +<!-- --> +<!-- IBM CONFIDENTIAL --> +<!-- --> +<!-- COPYRIGHT International Business Machines Corp. 2014 --> +<!-- --> +<!-- p1 --> +<!-- --> +<!-- Object Code Only (OCO) source materials --> +<!-- Licensed Internal Code Source Materials --> +<!-- IBM HostBoot Licensed Internal Code --> +<!-- --> +<!-- The source code for this program is not published or otherwise --> +<!-- divested of its trade secrets, irrespective of what has been --> +<!-- deposited with the U.S. Copyright Office. --> +<!-- --> +<!-- Origin: 30 --> +<!-- --> +<!-- IBM_PROLOG_END_TAG --> +<!-- $Id: io_read_erepair_errors.xml,v 1.2 2014/03/18 14:58:41 jgrell Exp $ --> + +<!-- Error definitions for IO_READ_EREPAIR HWPS --> +<hwpErrors> + <!-- *********************************************************************** --> + <hwpError> + <rc>IO_READ_EREPAIR_INVALID_INVOCATION_RC</rc> + <description>io_run_training invoked with wrong pair of targets</description> + <ffdc>TARGET</ffdc> + <callout> + <procedure>CODE</procedure> + <priority>HIGH</priority> + </callout> + </hwpError> +</hwpErrors> diff --git a/src/usr/hwpf/hwp/bus_training/io_restore_erepair.C b/src/usr/hwpf/hwp/bus_training/io_restore_erepair.C index 683214eb5..ca92249cb 100644 --- a/src/usr/hwpf/hwp/bus_training/io_restore_erepair.C +++ b/src/usr/hwpf/hwp/bus_training/io_restore_erepair.C @@ -5,7 +5,7 @@ /* */ /* IBM CONFIDENTIAL */ /* */ -/* COPYRIGHT International Business Machines Corp. 2013 */ +/* COPYRIGHT International Business Machines Corp. 2013,2014 */ /* */ /* p1 */ /* */ @@ -20,7 +20,7 @@ /* Origin: 30 */ /* */ /* IBM_PROLOG_END_TAG */ -// $Id: io_restore_erepair.C,v 1.16 2013/11/14 08:50:21 varkeykv Exp $ +// $Id: io_restore_erepair.C,v 1.17 2014/03/05 12:01:03 varkeykv Exp $ // *!*************************************************************************** // *! (C) Copyright International Business Machines Corp. 1997, 1998 // *! All Rights Reserved -- Property of IBM @@ -42,18 +42,19 @@ // 1.0 |varkeykv|09/27/11|Initial check in . Have to modify targets once bus target is defined and available.Not tested in any way other than in unit SIM IOTK //------------------------------------------------------------------------------ + #include <fapi.H> #include "io_restore_erepair.H" -#include "gcr_funcs.H"
-#include "io_power_down_lanes.H"
+#include "gcr_funcs.H" +#include "io_power_down_lanes.H" #include <erepairAccessorHwpFuncs.H> extern "C" { using namespace fapi; -
-
+ + //! Read repair values from VPD into the HW /* This function will perform erepair for one IO type target -- eithe MCS or XBUS or ABUS @@ -69,7 +70,7 @@ ReturnCode io_restore_erepair(const Target& target,std::vector<uint8_t> &tx_lane ecmdDataBufferBase data_two(16); ecmdDataBufferBase mode_reg(16); ecmdDataBufferBase mask(16); - uint8_t lane=0;
+ uint8_t lane=0; bool lane_valid=false; io_interface_t interface=CP_IOMC0_P0; // Since G @@ -107,7 +108,8 @@ ReturnCode io_restore_erepair(const Target& target,std::vector<uint8_t> &tx_lane } else{ FAPI_ERR("Invalid io_restore_erepair HWP invocation"); - FAPI_SET_HWP_ERROR(rc, IO_RUN_TRAINING_INVALID_INVOCATION_RC); + const fapi::Target &TARGET = target; + FAPI_SET_HWP_ERROR(rc, IO_RESTORE_EREPAIR_INVALID_INVOCATION_RC); return(rc); } // Use the accessor to fetch VPD data for this particular target instance @@ -137,67 +139,77 @@ ReturnCode io_restore_erepair(const Target& target,std::vector<uint8_t> &tx_lane { rc.setEcmdError(rc_ecmd); return(rc); - }
-
- // Read in original data
-
- // Read in values for RMW
- rc = GCR_read( target,interface,rx_lane_bad_vec_0_15_pg, clock_group, 0, data_one);
- if(rc){return rc;}
- rc = GCR_read( target,interface,rx_lane_bad_vec_16_31_pg, clock_group, 0, data_two);
- if(rc){return rc;}
+ } + + // Read in original data + + // Read in values for RMW + rc = GCR_read( target,interface,rx_lane_bad_vec_0_15_pg, clock_group, 0, data_one); + if(rc){return rc;} + rc = GCR_read( target,interface,rx_lane_bad_vec_16_31_pg, clock_group, 0, data_two); + if(rc){return rc;} // RX lane records // Set the RX bad lanes in the buffer - for(uint8_t i=0;i<rx_lanes.size();++i){
-
- if(interface==CP_FABRIC_X0){
- if(clock_group==0 && rx_lanes[i]<20){
- lane=rx_lanes[i];
- lane_valid=true;
- }
- else if(clock_group==1 && (rx_lanes[i]>19 && rx_lanes[i]<40)){
- lane=rx_lanes[i]-20;
- lane_valid=true;
- }
- else if(clock_group==2 && (rx_lanes[i]>39 && rx_lanes[i]<60)){
- lane=rx_lanes[i]-40;
- lane_valid=true;
- }
- else if(clock_group==3 && (rx_lanes[i]>59 && rx_lanes[i]<80) ){
- lane=rx_lanes[i]-60;
- lane_valid=true;
- }
- else{
- lane_valid=false;
- }
- }
- else{
- lane=rx_lanes[i];
- lane_valid=true;
+ for(uint8_t i=0;i<rx_lanes.size();++i){ + + if(interface==CP_FABRIC_X0){ + if(clock_group==0 && rx_lanes[i]<20){ + lane=rx_lanes[i]; + lane_valid=true; + } + else if(clock_group==1 && (rx_lanes[i]>19 && rx_lanes[i]<40)){ + lane=rx_lanes[i]-20; + lane_valid=true; + } + else if(clock_group==2 && (rx_lanes[i]>39 && rx_lanes[i]<60)){ + lane=rx_lanes[i]-40; + lane_valid=true; + } + else if(clock_group==3 && (rx_lanes[i]>59 && rx_lanes[i]<80) ){ + lane=rx_lanes[i]-60; + lane_valid=true; + } + else{ + lane_valid=false; + } + } + else{ + lane=rx_lanes[i]; + lane_valid=true; } - if (lane < 16 && lane_valid) {
- data_one.setBit(lane); + if (lane < 16 && lane_valid) { + rc_ecmd = data_one.setBit(lane); + if(rc_ecmd) + { + rc.setEcmdError(rc_ecmd); + return(rc); + } } - else if(lane>=16 && lane_valid) {
- data_two.setBit(lane-16); + else if(lane>=16 && lane_valid) { + rc_ecmd = data_two.setBit(lane-16); + if(rc_ecmd) + { + rc.setEcmdError(rc_ecmd); + return(rc); + } } - }
+ } FAPI_DBG("#2 Corrected RX lane is %d\n",lane); - //Now write the bad lanes in one shot on the slave side RX
- if(!data_one.isBitClear(0,16)){
- rc = GCR_write( target, interface, rx_lane_bad_vec_0_15_pg, clock_group, 0, data_one,mask );
- if(rc){return rc;}
- }
- if(!data_two.isBitClear(0,16)){
- //Now write the bad lanes in one shot on the slave side RX
- rc = GCR_write( target, interface, rx_lane_bad_vec_16_31_pg, clock_group, 0, data_two,mask);
- if(rc){return rc;}
+ //Now write the bad lanes in one shot on the slave side RX + if(!data_one.isBitClear(0,16)){ + rc = GCR_write( target, interface, rx_lane_bad_vec_0_15_pg, clock_group, 0, data_one,mask ); + if(rc){return rc;} + } + if(!data_two.isBitClear(0,16)){ + //Now write the bad lanes in one shot on the slave side RX + rc = GCR_write( target, interface, rx_lane_bad_vec_16_31_pg, clock_group, 0, data_two,mask); + if(rc){return rc;} } - }
+ } FAPI_EXEC_HWP(rc, io_power_down_lanes,target,tx_lanes,rx_lanes); return rc; -}
+} } //end extern C diff --git a/src/usr/hwpf/hwp/bus_training/io_restore_erepair.H b/src/usr/hwpf/hwp/bus_training/io_restore_erepair.H index df3f713d8..cd878dc00 100644 --- a/src/usr/hwpf/hwp/bus_training/io_restore_erepair.H +++ b/src/usr/hwpf/hwp/bus_training/io_restore_erepair.H @@ -5,7 +5,7 @@ /* */ /* IBM CONFIDENTIAL */ /* */ -/* COPYRIGHT International Business Machines Corp. 2012,2013 */ +/* COPYRIGHT International Business Machines Corp. 2013,2014 */ /* */ /* p1 */ /* */ @@ -20,10 +20,11 @@ /* Origin: 30 */ /* */ /* IBM_PROLOG_END_TAG */ -// $Id: io_restore_erepair.H,v 1.8 2012/12/10 17:30:46 varkeykv Exp $ +// $Id: io_restore_erepair.H,v 1.9 2014/03/05 12:01:04 varkeykv Exp $ #ifndef IO_RESTORE_EREPAIR_H_ #define IO_RESTORE_EREPAIR_H_ + #include <fapi.H> /** diff --git a/src/usr/hwpf/hwp/bus_training/io_restore_erepair_errors.xml b/src/usr/hwpf/hwp/bus_training/io_restore_erepair_errors.xml new file mode 100644 index 000000000..53ae65cc7 --- /dev/null +++ b/src/usr/hwpf/hwp/bus_training/io_restore_erepair_errors.xml @@ -0,0 +1,35 @@ +<!-- IBM_PROLOG_BEGIN_TAG --> +<!-- This is an automatically generated prolog. --> +<!-- --> +<!-- $Source: src/usr/hwpf/hwp/bus_training/io_restore_erepair_errors.xml $ --> +<!-- --> +<!-- IBM CONFIDENTIAL --> +<!-- --> +<!-- COPYRIGHT International Business Machines Corp. 2014 --> +<!-- --> +<!-- p1 --> +<!-- --> +<!-- Object Code Only (OCO) source materials --> +<!-- Licensed Internal Code Source Materials --> +<!-- IBM HostBoot Licensed Internal Code --> +<!-- --> +<!-- The source code for this program is not published or otherwise --> +<!-- divested of its trade secrets, irrespective of what has been --> +<!-- deposited with the U.S. Copyright Office. --> +<!-- --> +<!-- Origin: 30 --> +<!-- --> +<!-- IBM_PROLOG_END_TAG --> +<!-- $Id: io_restore_erepair_errors.xml,v 1.2 2014/03/17 18:54:00 dedahle Exp $ --> +<!-- Error definitions for IO_RESTORE_EREPAIR --> +<hwpErrors> + <hwpError> + <rc>IO_RESTORE_EREPAIR_INVALID_INVOCATION_RC</rc> + <description>io_restore_erepair invoked with incorrect target type</description> + <ffdc>TARGET</ffdc> + <callout> + <procedure>CODE</procedure> + <priority>HIGH</priority> + </callout> + </hwpError> +</hwpErrors> diff --git a/src/usr/hwpf/hwp/bus_training/io_run_training.C b/src/usr/hwpf/hwp/bus_training/io_run_training.C index 108847e8d..33ba7ee4e 100644 --- a/src/usr/hwpf/hwp/bus_training/io_run_training.C +++ b/src/usr/hwpf/hwp/bus_training/io_run_training.C @@ -20,7 +20,7 @@ /* Origin: 30 */ /* */ /* IBM_PROLOG_END_TAG */ -// $Id: io_run_training.C,v 1.57 2014/02/10 16:15:52 varkeykv Exp $ +// $Id: io_run_training.C,v 1.59 2014/03/13 15:59:48 varkeykv Exp $ // *!*************************************************************************** // *! (C) Copyright International Business Machines Corp. 1997, 1998 // *! All Rights Reserved -- Property of IBM @@ -52,1353 +52,1394 @@ extern "C" { - using namespace fapi; - - - -ReturnCode io_training_set_pll_post_wiretest(const Target& target){ - ReturnCode rc; - uint8_t pb_bndy_dmipll_data[231]={0},ab_bndy_pll_data[80]={0},tp_bndy_pll_data[80]={0}; - - // For the PLL Partial updation logic we need PFD360 offsets into the Ring now - uint32_t proc_dmi_cupll_pfd360_offset[8]; - uint32_t memb_dmi_cupll_pfd360_offset; - uint32_t proc_abus_cupll_pfd360_offset[3]; - // REFCLK SEL offsets - //uint32_t proc_dmi_cupll_refclksel_offset[8]; - // uint32_t memb_dmi_cupll_refclksel_offset; - //uint32_t proc_abus_cupll_refclksel_offset[3]; - - ecmdDataBufferBase ring_data; - fapi::Target parent_target; - uint32_t ring_length=0; - uint32_t rc_ecmd=0; - uint8_t chip_unit = 0; - - FAPI_DBG("Running PLL updation code"); - - - - // This is a DMI/MC bus - if (target.getType() == fapi::TARGET_TYPE_MCS_CHIPLET) - { - FAPI_DBG("This is a Processor DMI bus using base DMI scom address"); - - // Lets get chip unit pos , used for PLL table lookup - rc = FAPI_ATTR_GET(ATTR_CHIP_UNIT_POS, - &target, - chip_unit); - + using namespace fapi; + + + + ReturnCode io_training_set_pll_post_wiretest(const Target& target){ + ReturnCode rc; + uint8_t pb_bndy_dmipll_data[231]={0},ab_bndy_pll_data[80]={0},tp_bndy_pll_data[80]={0}; + + // For the PLL Partial updation logic we need PFD360 offsets into the Ring now + uint32_t proc_dmi_cupll_pfd360_offset[8]; + uint32_t memb_dmi_cupll_pfd360_offset; + uint32_t proc_abus_cupll_pfd360_offset[3]; + // REFCLK SEL offsets + //uint32_t proc_dmi_cupll_refclksel_offset[8]; + // uint32_t memb_dmi_cupll_refclksel_offset; + //uint32_t proc_abus_cupll_refclksel_offset[3]; + + ecmdDataBufferBase ring_data; + fapi::Target parent_target; + uint32_t ring_length=0; + uint32_t rc_ecmd=0; + uint8_t chip_unit = 0; + + FAPI_DBG("Running PLL updation code"); + + + + // This is a DMI/MC bus + if (target.getType() == fapi::TARGET_TYPE_MCS_CHIPLET) + { + FAPI_DBG("This is a Processor DMI bus using base DMI scom address"); + + // Lets get chip unit pos , used for PLL table lookup + rc = FAPI_ATTR_GET(ATTR_CHIP_UNIT_POS, + &target, + chip_unit); + if (rc) { FAPI_ERR("Error retreiving MCS chiplet number!"); return rc; } - - // obtain parent chip target needed for ring manipulation - rc = fapiGetParentChip(target, parent_target); - if (rc) - { - FAPI_ERR("Error from fapiGetParentChip"); - return(rc); - } - // install PLL config for dccal operation - rc = FAPI_ATTR_GET(ATTR_PROC_PB_BNDY_DMIPLL_LENGTH, &parent_target, ring_length); // -- get length of scan ring - if (rc) - { - FAPI_ERR("Error from FAPI_ATTR_GET (ATTR_PROC_PB_BNDY_DMIPLL_LENGTH)"); - return(rc); - } -// rc = FAPI_ATTR_GET(ATTR_PROC_PB_BNDY_dmipll_FOR_RUNTIME_DATA, &parent_target, pb_bndy_dmipll_data); // -- get scan ring data - rc = FAPI_ATTR_GET(ATTR_PROC_PB_BNDY_DMIPLL_DATA, &parent_target, pb_bndy_dmipll_data); // -- get scan ring data - if (rc) - { - FAPI_ERR("Error from FAPI_ATTR_GET (ATTR_PROC_PB_BNDY_DMIPLL_FOR_DCCAL_DATA)"); - return(rc); - } - - // Now we need the partial offset data also . First let us get PFD360 offsets - rc = FAPI_ATTR_GET(ATTR_PROC_DMI_CUPLL_PFD360_OFFSET, &parent_target, proc_dmi_cupll_pfd360_offset); // -- get length of scan ring - if (rc) - { - FAPI_ERR("Error fetching PFD360 offsets on MCS"); - return(rc); - } - //rc = FAPI_ATTR_GET(ATTR_PROC_DMI_CUPLL_REFCLKSEL_OFFSET, &parent_target, proc_dmi_cupll_refclksel_offset); // -- get length of scan ring - //if (rc) - //{ - // FAPI_ERR("Error fetching REFCLKSEL offsets on MCS"); - // return(rc); - //} - - rc_ecmd |= ring_data.setBitLength(ring_length); - if (rc_ecmd) - { - rc.setEcmdError(rc_ecmd); - return(rc); - } - - rc =fapiGetRing(parent_target,PB_BNDY_DMIPLL_RING_ADDR ,ring_data,RING_MODE_SET_PULSE); - if (rc) - { - FAPI_ERR("Error performing GetRing operation on PB_BNDY_DMIPLL"); - return(rc); - } + // obtain parent chip target needed for ring manipulation + rc = fapiGetParentChip(target, parent_target); + if (rc) + { + FAPI_ERR("Error from fapiGetParentChip"); + return(rc); + } + + // install PLL config for dccal operation + rc = FAPI_ATTR_GET(ATTR_PROC_PB_BNDY_DMIPLL_LENGTH, &parent_target, ring_length); // -- get length of scan ring + if (rc) + { + FAPI_ERR("Error from FAPI_ATTR_GET (ATTR_PROC_PB_BNDY_DMIPLL_LENGTH)"); + return(rc); + } + // rc = FAPI_ATTR_GET(ATTR_PROC_PB_BNDY_dmipll_FOR_RUNTIME_DATA, &parent_target, pb_bndy_dmipll_data); // -- get scan ring data + rc = FAPI_ATTR_GET(ATTR_PROC_PB_BNDY_DMIPLL_DATA, &parent_target, pb_bndy_dmipll_data); // -- get scan ring data + if (rc) + { + FAPI_ERR("Error from FAPI_ATTR_GET (ATTR_PROC_PB_BNDY_DMIPLL_FOR_DCCAL_DATA)"); + return(rc); + } + + // Now we need the partial offset data also . First let us get PFD360 offsets + rc = FAPI_ATTR_GET(ATTR_PROC_DMI_CUPLL_PFD360_OFFSET, &parent_target, proc_dmi_cupll_pfd360_offset); // -- get length of scan ring + if (rc) + { + FAPI_ERR("Error fetching PFD360 offsets on MCS"); + return(rc); + } + //rc = FAPI_ATTR_GET(ATTR_PROC_DMI_CUPLL_REFCLKSEL_OFFSET, &parent_target, proc_dmi_cupll_refclksel_offset); // -- get length of scan ring + //if (rc) + //{ + // FAPI_ERR("Error fetching REFCLKSEL offsets on MCS"); + // return(rc); + //} + + rc_ecmd |= ring_data.setBitLength(ring_length); + if (rc_ecmd) + { + rc.setEcmdError(rc_ecmd); + return(rc); + } + + rc =fapiGetRing(parent_target,PB_BNDY_DMIPLL_RING_ADDR ,ring_data,RING_MODE_SET_PULSE); + if (rc) + { + FAPI_ERR("Error performing GetRing operation on PB_BNDY_DMIPLL"); + return(rc); + } FAPI_DBG("PFD bit to be cleared for DMI unit %d is %d",chip_unit,proc_dmi_cupll_pfd360_offset[chip_unit]); - rc_ecmd |= ring_data.clearBit(proc_dmi_cupll_pfd360_offset[chip_unit]); - // Now - if (rc_ecmd) - { - rc.setEcmdError(rc_ecmd); - return(rc); - } - rc = proc_a_x_pci_dmi_pll_scan_bndy(parent_target, - NEST_CHIPLET_0x02000000, - PB_BNDY_DMIPLL_RING_ADDR, - ring_data, - true); - if (rc) - { - FAPI_ERR("Error from proc_a_x_pci_dmi_pll_scan_bndy"); - return(rc); - } + rc_ecmd |= ring_data.clearBit(proc_dmi_cupll_pfd360_offset[chip_unit]); + // Now + if (rc_ecmd) + { + rc.setEcmdError(rc_ecmd); + return(rc); + } + rc = proc_a_x_pci_dmi_pll_scan_bndy(parent_target, + NEST_CHIPLET_0x02000000, + PB_BNDY_DMIPLL_RING_ADDR, + ring_data, + true); + if (rc) + { + FAPI_ERR("Error from proc_a_x_pci_dmi_pll_scan_bndy"); + return(rc); + } - - } - else if (target.getType() == fapi::TARGET_TYPE_MEMBUF_CHIP) - { - FAPI_DBG("This is a Centaur DMI bus using base DMI scom address"); - // install PLL config for dccal operation - rc = FAPI_ATTR_GET(ATTR_MEMB_TP_BNDY_PLL_LENGTH, &target, ring_length); // -- get length of scan ring - if (rc) - { - FAPI_ERR("Error from FAPI_ATTR_GET (ATTR_MEMB_TP_BNDY_PLL_LENGTH)"); - return(rc); } -// rc = FAPI_ATTR_GET(ATTR_MEMB_TP_BNDY_PLL_FOR_RUNTIME_DATA, &target, tp_bndy_pll_data); // -- get scan ring data - rc = FAPI_ATTR_GET(ATTR_MEMB_TP_BNDY_PLL_DATA, &target, tp_bndy_pll_data); // -- get scan ring data - if (rc) + else if (target.getType() == fapi::TARGET_TYPE_MEMBUF_CHIP) { - FAPI_ERR("Error from FAPI_ATTR_GET (ATTR_MEMB_TP_BNDY_PLL_FOR_DCCAL_DATA)"); - return(rc); - } - - // Now we need the partial offset data also . First let us get PFD360 offsets - rc = FAPI_ATTR_GET(ATTR_MEMB_DMI_CUPLL_PFD360_OFFSET, &target, memb_dmi_cupll_pfd360_offset); // -- get length of scan ring - if (rc) - { - FAPI_ERR("Error fetching PFD360 offsets on Centaur"); - return(rc); - } - //rc = FAPI_ATTR_GET(ATTR_MEMB_DMI_CUPLL_REFCLKSEL_OFFSET, &target, memb_dmi_cupll_refclksel_offset); // -- get length of scan ring - //if (rc) - //{ - // FAPI_ERR("Error fetching REFCLKSEL offsets on Centaur"); - // return(rc); - //} - - FAPI_DBG("Centaur PFD offset = %d",memb_dmi_cupll_pfd360_offset); - // FAPI_DBG("Centaur REFCLKSEL offset = %d",memb_dmi_cupll_refclksel_offset); - - FAPI_DBG("Ring length is %d",ring_length); - rc_ecmd |= ring_data.setBitLength(ring_length); - if (rc_ecmd) - { - rc.setEcmdError(rc_ecmd); - return(rc); - } - - rc=fapiGetRing(target,MEMB_TP_BNDY_PLL_RING_ADDR ,ring_data,RING_MODE_SET_PULSE); - if (rc) - { - FAPI_ERR("Get ring error on MEMB "); - return(rc); - } - // rc_ecmd |= ring_data.insert(pb_bndy_dmipll_data, 0, ring_length, 0); // -- put data into ecmd buffer + FAPI_DBG("This is a Centaur DMI bus using base DMI scom address"); + + // install PLL config for dccal operation + rc = FAPI_ATTR_GET(ATTR_MEMB_TP_BNDY_PLL_LENGTH, &target, ring_length); // -- get length of scan ring + if (rc) + { + FAPI_ERR("Error from FAPI_ATTR_GET (ATTR_MEMB_TP_BNDY_PLL_LENGTH)"); + return(rc); + } + // rc = FAPI_ATTR_GET(ATTR_MEMB_TP_BNDY_PLL_FOR_RUNTIME_DATA, &target, tp_bndy_pll_data); // -- get scan ring data + rc = FAPI_ATTR_GET(ATTR_MEMB_TP_BNDY_PLL_DATA, &target, tp_bndy_pll_data); // -- get scan ring data + if (rc) + { + FAPI_ERR("Error from FAPI_ATTR_GET (ATTR_MEMB_TP_BNDY_PLL_FOR_DCCAL_DATA)"); + return(rc); + } + + // Now we need the partial offset data also . First let us get PFD360 offsets + rc = FAPI_ATTR_GET(ATTR_MEMB_DMI_CUPLL_PFD360_OFFSET, &target, memb_dmi_cupll_pfd360_offset); // -- get length of scan ring + if (rc) + { + FAPI_ERR("Error fetching PFD360 offsets on Centaur"); + return(rc); + } + //rc = FAPI_ATTR_GET(ATTR_MEMB_DMI_CUPLL_REFCLKSEL_OFFSET, &target, memb_dmi_cupll_refclksel_offset); // -- get length of scan ring + //if (rc) + //{ + // FAPI_ERR("Error fetching REFCLKSEL offsets on Centaur"); + // return(rc); + //} + + FAPI_DBG("Centaur PFD offset = %d",memb_dmi_cupll_pfd360_offset); + // FAPI_DBG("Centaur REFCLKSEL offset = %d",memb_dmi_cupll_refclksel_offset); + + FAPI_DBG("Ring length is %d",ring_length); + rc_ecmd |= ring_data.setBitLength(ring_length); + if (rc_ecmd) + { + rc.setEcmdError(rc_ecmd); + return(rc); + } + + rc=fapiGetRing(target,MEMB_TP_BNDY_PLL_RING_ADDR ,ring_data,RING_MODE_SET_PULSE); + if (rc) + { + FAPI_ERR("Get ring error on MEMB "); + return(rc); + } + // rc_ecmd |= ring_data.insert(pb_bndy_dmipll_data, 0, ring_length, 0); // -- put data into ecmd buffer FAPI_DBG("PFD bit to be cleared for centaur is %d",memb_dmi_cupll_pfd360_offset); - rc_ecmd |=ring_data.clearBit(memb_dmi_cupll_pfd360_offset); - - //rc_ecmd |= ring_data.insert(tp_bndy_pll_data, 0, ring_length, 0); // -- put data into ecmd buffer - if (rc_ecmd) - { - rc.setEcmdError(rc_ecmd); - return(rc); - } - rc = proc_a_x_pci_dmi_pll_scan_bndy(target, - TP_CHIPLET_0x01000000, - MEMB_TP_BNDY_PLL_RING_ADDR, - ring_data, - true); - if (rc) - { - FAPI_ERR("Error from proc_a_x_pci_dmi_pll_scan_bndy"); - return(rc); - } + rc_ecmd |=ring_data.clearBit(memb_dmi_cupll_pfd360_offset); + + //rc_ecmd |= ring_data.insert(tp_bndy_pll_data, 0, ring_length, 0); // -- put data into ecmd buffer + if (rc_ecmd) + { + rc.setEcmdError(rc_ecmd); + return(rc); + } + rc = proc_a_x_pci_dmi_pll_scan_bndy(target, + TP_CHIPLET_0x01000000, + MEMB_TP_BNDY_PLL_RING_ADDR, + ring_data, + true); + if (rc) + { + FAPI_ERR("Error from proc_a_x_pci_dmi_pll_scan_bndy"); + return(rc); + } - - } - //This is an X Bus - else if (target.getType() == fapi::TARGET_TYPE_XBUS_ENDPOINT) - { - FAPI_DBG("This is a X Bus training invocation"); - } - //This is an A Bus - else if (target.getType() == fapi::TARGET_TYPE_ABUS_ENDPOINT) - { - FAPI_DBG("This is an A Bus training invocation"); - - // Lets get chip unit pos , used for PLL table lookup - rc = FAPI_ATTR_GET(ATTR_CHIP_UNIT_POS, - &target, - chip_unit); - - if (!rc.ok()) - { - FAPI_ERR("Error retreiving Abus chiplet number!"); - return rc; - } - - // obtain parent chip target needed for ring manipulation - rc = fapiGetParentChip(target, parent_target); - if (rc) - { - FAPI_ERR("Error from fapiGetParentChip"); - return(rc); - } - // install PLL config for dccal operation - rc = FAPI_ATTR_GET(ATTR_PROC_AB_BNDY_PLL_LENGTH, &parent_target, ring_length); // -- get length of scan ring - if (rc) - { - FAPI_ERR("Error from FAPI_ATTR_GET (ATTR_PROC_AB_BNDY_PLL_LENGTH)"); - return(rc); } -// rc = FAPI_ATTR_GET(ATTR_PROC_AB_BNDY_PLL_FOR_RUNTIME_DATA, &parent_target, ab_bndy_pll_data); // -- get scan ring data - rc = FAPI_ATTR_GET(ATTR_PROC_AB_BNDY_PLL_DATA, &parent_target, ab_bndy_pll_data); // -- get scan ring data - if (rc) + //This is an X Bus + else if (target.getType() == fapi::TARGET_TYPE_XBUS_ENDPOINT) { - FAPI_ERR("Error from FAPI_ATTR_GET (ATTR_PROC_AB_BNDY_PLL_FOR_DCCAL_DATA)"); - return(rc); + FAPI_DBG("This is a X Bus training invocation"); } - - - // Now we need the partial offset data also . First let us get PFD360 offsets - rc = FAPI_ATTR_GET(ATTR_PROC_ABUS_CUPLL_PFD360_OFFSET, &parent_target, proc_abus_cupll_pfd360_offset); // -- get length of scan ring - if (rc) + //This is an A Bus + else if (target.getType() == fapi::TARGET_TYPE_ABUS_ENDPOINT) { - FAPI_ERR("Error fetching PFD360 offsets on Abus"); - return(rc); - } - //rc = FAPI_ATTR_GET(ATTR_PROC_ABUS_CUPLL_REFCLKSEL_OFFSET, &parent_target, proc_abus_cupll_refclksel_offset); // -- get length of scan ring - //if (rc) - //{ - // FAPI_ERR("Error fetching REFCLKSEL offsets on Abus"); - // return(rc); - //} + FAPI_DBG("This is an A Bus training invocation"); + + // Lets get chip unit pos , used for PLL table lookup + rc = FAPI_ATTR_GET(ATTR_CHIP_UNIT_POS, + &target, + chip_unit); + + if (!rc.ok()) + { + FAPI_ERR("Error retreiving Abus chiplet number!"); + return rc; + } + + // obtain parent chip target needed for ring manipulation + rc = fapiGetParentChip(target, parent_target); + if (rc) + { + FAPI_ERR("Error from fapiGetParentChip"); + return(rc); + } + + // install PLL config for dccal operation + rc = FAPI_ATTR_GET(ATTR_PROC_AB_BNDY_PLL_LENGTH, &parent_target, ring_length); // -- get length of scan ring + if (rc) + { + FAPI_ERR("Error from FAPI_ATTR_GET (ATTR_PROC_AB_BNDY_PLL_LENGTH)"); + return(rc); + } + // rc = FAPI_ATTR_GET(ATTR_PROC_AB_BNDY_PLL_FOR_RUNTIME_DATA, &parent_target, ab_bndy_pll_data); // -- get scan ring data + rc = FAPI_ATTR_GET(ATTR_PROC_AB_BNDY_PLL_DATA, &parent_target, ab_bndy_pll_data); // -- get scan ring data + if (rc) + { + FAPI_ERR("Error from FAPI_ATTR_GET (ATTR_PROC_AB_BNDY_PLL_FOR_DCCAL_DATA)"); + return(rc); + } + + + // Now we need the partial offset data also . First let us get PFD360 offsets + rc = FAPI_ATTR_GET(ATTR_PROC_ABUS_CUPLL_PFD360_OFFSET, &parent_target, proc_abus_cupll_pfd360_offset); // -- get length of scan ring + if (rc) + { + FAPI_ERR("Error fetching PFD360 offsets on Abus"); + return(rc); + } + //rc = FAPI_ATTR_GET(ATTR_PROC_ABUS_CUPLL_REFCLKSEL_OFFSET, &parent_target, proc_abus_cupll_refclksel_offset); // -- get length of scan ring + //if (rc) + //{ + // FAPI_ERR("Error fetching REFCLKSEL offsets on Abus"); + // return(rc); + //} rc_ecmd |= ring_data.setBitLength(ring_length); - if (rc_ecmd) - { - rc.setEcmdError(rc_ecmd); - return(rc); - } + if (rc_ecmd) + { + rc.setEcmdError(rc_ecmd); + return(rc); + } rc =fapiGetRing(parent_target,AB_BNDY_PLL_RING_ADDR ,ring_data,RING_MODE_SET_PULSE); - if (rc) - { - FAPI_ERR("GetRing error on AB ring"); - return(rc); - } + if (rc) + { + FAPI_ERR("GetRing error on AB ring"); + return(rc); + } FAPI_DBG("PFD bit to be cleared for Abus number %d is %d",chip_unit,proc_abus_cupll_pfd360_offset[chip_unit]); rc_ecmd|=ring_data.clearBit(proc_abus_cupll_pfd360_offset[chip_unit]); - if (rc_ecmd) - { - rc.setEcmdError(rc_ecmd); - return(rc); - } - rc = proc_a_x_pci_dmi_pll_scan_bndy(parent_target, - A_BUS_CHIPLET_0x08000000, - AB_BNDY_PLL_RING_ADDR, - ring_data, - true); - if (rc) + if (rc_ecmd) + { + rc.setEcmdError(rc_ecmd); + return(rc); + } + rc = proc_a_x_pci_dmi_pll_scan_bndy(parent_target, + A_BUS_CHIPLET_0x08000000, + AB_BNDY_PLL_RING_ADDR, + ring_data, + true); + if (rc) + { + FAPI_ERR("Error from proc_a_x_pci_dmi_pll_scan_bndy"); + return(rc); + } + + } + else { - FAPI_ERR("Error from proc_a_x_pci_dmi_pll_scan_bndy"); - return(rc); + FAPI_ERR("Invalid target passed to PLL Update code.. target does not belong to DMI/X/A instances"); + const fapi::Target &TARGET = target; + FAPI_SET_HWP_ERROR(rc, IO_RUN_TRAINING_SET_PLL_INVALID_INVOCATION_RC); } - - } - else - { - FAPI_ERR("Invalid target passed to PLL Update code.. target does not belong to DMI/X/A instances"); - FAPI_SET_HWP_ERROR(rc, IO_DCCAL_INVALID_INVOCATION_RC); + return rc; } - return rc; -} -// For clearing the FIR mask , used by io run training -ReturnCode clear_fir_mask_reg(const Target &i_target,fir_io_interface_t i_chip_interface){ + // For clearing the FIR mask , used by io run training + ReturnCode clear_fir_mask_reg(const Target &i_target,fir_io_interface_t i_chip_interface){ - ReturnCode rc; - uint32_t rc_ecmd = 0; - uint8_t chip_unit = 0; - uint8_t link_fir_unmask_data = 0xFF; - ecmdDataBufferBase data(64); - FAPI_INF("io_run_training:In the Clear FIR MASK register function "); + ReturnCode rc; + uint32_t rc_ecmd = 0; + uint8_t chip_unit = 0; + uint8_t link_fir_unmask_data = 0xFF; + ecmdDataBufferBase data(64); + FAPI_INF("io_run_training:In the Clear FIR MASK register function "); - do - { - // initialize mask to all 1s - rc_ecmd |= data.invert(); - - // set FIR mask appropriately based on interface type / link being trained - if ((i_chip_interface == FIR_CP_FABRIC_A0) || - (i_chip_interface == FIR_CP_IOMC0_P0)) + do { - rc = FAPI_ATTR_GET(ATTR_CHIP_UNIT_POS, - &i_target, - chip_unit); - if (!rc.ok()) + // initialize mask to all 1s + rc_ecmd |= data.invert(); + // check buffer manipulation return codes + if (rc_ecmd) { - FAPI_ERR("Error retreiving chiplet number!"); + FAPI_ERR("Error 0x%X setting up FIR mask data buffer", + rc_ecmd); + rc.setEcmdError(rc_ecmd); break; } - - // adjust for DMI number - if (i_chip_interface == FIR_CP_IOMC0_P0) + // set FIR mask appropriately based on interface type / link being trained + if ((i_chip_interface == FIR_CP_FABRIC_A0) || + (i_chip_interface == FIR_CP_IOMC0_P0)) { - chip_unit = chip_unit % 4; - // BUS ID Remapped to linear by John Rell so commenting this out - link_fir_unmask_data = 0x87; // as per Gary via SW245014 + rc = FAPI_ATTR_GET(ATTR_CHIP_UNIT_POS, + &i_target, + chip_unit); + if (!rc.ok()) + { + FAPI_ERR("Error retreiving chiplet number!"); + break; + } + + // adjust for DMI number + if (i_chip_interface == FIR_CP_IOMC0_P0) + { + chip_unit = chip_unit % 4; + // BUS ID Remapped to linear by John Rell so commenting this out + link_fir_unmask_data = 0x87; // as per Gary via SW245014 + } + // adjust for ABUS number + else + { + chip_unit = chip_unit + 1; + link_fir_unmask_data = 0x87;// as per Gary via SW245014, leave at this value + } } - // adjust for ABUS number - else + + // SW228820 , for Xbus all data goes into BUS0 fields regardless of instance + else if ((i_chip_interface == FIR_CEN_DMI) || + (i_chip_interface == FIR_CP_FABRIC_X0)) { - chip_unit = chip_unit + 1; - link_fir_unmask_data = 0x87;// as per Gary via SW245014, leave at this value + chip_unit = 0; + if (i_chip_interface == FIR_CEN_DMI) + { + //link_fir_unmask_data = 0x8F; + link_fir_unmask_data = 0x87; // as per Gary via SW245014 + } + else + { + //link_fir_unmask_data = 0x87; + link_fir_unmask_data = 0x97; // as per Gary via SW245014 + } } - } - // SW228820 , for Xbus all data goes into BUS0 fields regardless of instance - else if ((i_chip_interface == FIR_CEN_DMI) || - (i_chip_interface == FIR_CP_FABRIC_X0)) - { - chip_unit = 0; - if (i_chip_interface == FIR_CEN_DMI) + rc_ecmd |= data.insert(link_fir_unmask_data, + 8+(8*chip_unit), + 8); + + // check buffer manipulation return codes + if (rc_ecmd) { - //link_fir_unmask_data = 0x8F; - link_fir_unmask_data = 0x87; // as per Gary via SW245014 + FAPI_ERR("Error 0x%X setting up FIR mask data buffer", + rc_ecmd); + rc.setEcmdError(rc_ecmd); + break; } - else + + // use FIR AND mask register to un-mask selected bits + rc = fapiPutScom(i_target, fir_clear_mask_reg_addr[i_chip_interface], data); + if (!rc.ok()) { - //link_fir_unmask_data = 0x87; - link_fir_unmask_data = 0x97; // as per Gary via SW245014 + FAPI_ERR("Error writing FIR mask register (=%08X)!", + fir_clear_mask_reg_addr[i_chip_interface]); + break; } - } - rc_ecmd |= data.insert(link_fir_unmask_data, - 8+(8*chip_unit), - 8); + } while(0); - // check buffer manipulation return codes - if (rc_ecmd) - { - FAPI_ERR("Error 0x%X setting up FIR mask data buffer", - rc_ecmd); - rc.setEcmdError(rc_ecmd); - break; - } + return(rc); + } + + // For clearing out spare deployed summary bit , in case of false HW triggers on known bad lanes + // io_clear_firs only clear out lower level regs, not the summary FIR + ReturnCode clear_fir_summary_reg(const Target &i_target,fir_io_interface_t i_chip_interface){ + + ReturnCode rc; + uint32_t rc_ecmd = 0; + uint8_t chip_unit = 0; + ecmdDataBufferBase data(64); + uint64_t scom_address64=0; + ecmdDataBufferBase temp(64); + + FAPI_INF("io_run_training:In the Clear FIR MASK register function "); - // use FIR AND mask register to un-mask selected bits - rc = fapiPutScom(i_target, fir_clear_mask_reg_addr[i_chip_interface], data); - if (!rc.ok()) + do { - FAPI_ERR("Error writing FIR mask register (=%08X)!", - fir_clear_mask_reg_addr[i_chip_interface]); - break; - } - } while(0); + // set FIR mask appropriately based on interface type / link being trained + if ((i_chip_interface == FIR_CP_FABRIC_A0) || + (i_chip_interface == FIR_CP_IOMC0_P0)) + { + rc = FAPI_ATTR_GET(ATTR_CHIP_UNIT_POS, + &i_target, + chip_unit); + if (!rc.ok()) + { + FAPI_ERR("Error retreiving chiplet number!"); + break; + } - return(rc); -} + // adjust for DMI number + if (i_chip_interface == FIR_CP_IOMC0_P0) + { + chip_unit = chip_unit % 4; + // BUS ID Remapped to linear by John Rell/Joe so removed remap logic + } + // adjust for ABUS number + else + { + chip_unit = chip_unit + 1; + } + } -// For clearing out spare deployed summary bit , in case of false HW triggers on known bad lanes -// io_clear_firs only clear out lower level regs, not the summary FIR -ReturnCode clear_fir_summary_reg(const Target &i_target,fir_io_interface_t i_chip_interface){ + // SW228820 , for Xbus all data goes into BUS0 fields regardless of instance + else if ((i_chip_interface == FIR_CEN_DMI) || + (i_chip_interface == FIR_CP_FABRIC_X0)) + { + chip_unit = 0; + } - ReturnCode rc; - uint32_t rc_ecmd = 0; - uint8_t chip_unit = 0; - ecmdDataBufferBase data(64); - uint64_t scom_address64=0; - ecmdDataBufferBase temp(64); - - FAPI_INF("io_run_training:In the Clear FIR MASK register function "); - do - { - // set FIR mask appropriately based on interface type / link being trained - if ((i_chip_interface == FIR_CP_FABRIC_A0) || - (i_chip_interface == FIR_CP_IOMC0_P0)) - { - rc = FAPI_ATTR_GET(ATTR_CHIP_UNIT_POS, - &i_target, - chip_unit); + + rc_ecmd=temp.setDoubleWord(0,fir_rw_reg_addr[i_chip_interface]); + // check buffer manipulation return codes + if (rc_ecmd) + { + FAPI_ERR("Error 0x%X setting up FIR mask data buffer", + rc_ecmd); + rc.setEcmdError(rc_ecmd); + break; + } + scom_address64=temp.getDoubleWord(0); + + //read the 64 bit fir register + rc=fapiGetScom(i_target,scom_address64,data); + if (!rc.ok()) { - FAPI_ERR("Error retreiving chiplet number!"); + FAPI_ERR("Problem in fapi get scom "); break; } - // adjust for DMI number - if (i_chip_interface == FIR_CP_IOMC0_P0) + FAPI_DBG("Clearing spare deployed bit at %d",(8*(chip_unit+1)+1)); + rc_ecmd |= data.clearBit(8*(chip_unit+1)+1); + + // check buffer manipulation return codes + if (rc_ecmd) { - chip_unit = chip_unit % 4; - // BUS ID Remapped to linear by John Rell/Joe so removed remap logic + FAPI_ERR("ECMD Error 0x%X setting up FIR data Buffer", + rc_ecmd); + rc.setEcmdError(rc_ecmd); + break; } - // adjust for ABUS number - else + // Clear spare deployed bit on appropriate bits + rc = fapiPutScom(i_target, scom_address64, data); + if (!rc.ok()) { - chip_unit = chip_unit + 1; + FAPI_ERR("Problem in put scom "); + break; } + + } while(0); + + return(rc); + } + + // FIR Workaround Code -- Pre Training Section - HW205368 - procedure from Rob /Pete + ReturnCode fir_workaround_pre_training(const Target& master_target, io_interface_t master_interface,uint32_t master_group, const Target& slave_target, io_interface_t slave_interface,uint32_t slave_group, + ecmdDataBufferBase *slave_data_one_old,ecmdDataBufferBase *slave_data_two_old,ecmdDataBufferBase *master_data_one_old,ecmdDataBufferBase *master_data_two_old) + { + ReturnCode rc; + //Start - Workaround Pre Training Section - HW205368 - procedure from Rob /Pete + + uint8_t max_group=1; + + if(master_interface==CP_FABRIC_X0){ + max_group=4; } - // SW228820 , for Xbus all data goes into BUS0 fields regardless of instance - else if ((i_chip_interface == FIR_CEN_DMI) || - (i_chip_interface == FIR_CP_FABRIC_X0)) - { - chip_unit = 0; - } - - - - - rc_ecmd=temp.setDoubleWord(0,fir_rw_reg_addr[i_chip_interface]); - scom_address64=temp.getDoubleWord(0); - - // check buffer manipulation return codes - if (rc_ecmd) - { - FAPI_ERR("Error 0x%X setting up FIR mask data buffer", - rc_ecmd); - rc.setEcmdError(rc_ecmd); - break; - } - //read the 64 bit fir register - rc=fapiGetScom(i_target,scom_address64,data); - - if (!rc.ok()) - { - FAPI_ERR("Problem in fapi get scom "); - break; - } - - FAPI_DBG("Clearing spare deployed bit at %d",(8*(chip_unit+1)+1)); - rc_ecmd |= data.clearBit(8*(chip_unit+1)+1); - - // check buffer manipulation return codes - if (rc_ecmd) - { - FAPI_ERR("ECMD Error 0x%X setting up FIR data Buffer", - rc_ecmd); - rc.setEcmdError(rc_ecmd); - break; - } - // Clear spare deployed bit on appropriate bits - rc = fapiPutScom(i_target, scom_address64, data); - if (!rc.ok()) - { - FAPI_ERR("Problem in put scom "); - break; - } - - } while(0); - - return(rc); -} - -// FIR Workaround Code -- Pre Training Section - HW205368 - procedure from Rob /Pete -ReturnCode fir_workaround_pre_training(const Target& master_target, io_interface_t master_interface,uint32_t master_group, const Target& slave_target, io_interface_t slave_interface,uint32_t slave_group, - ecmdDataBufferBase *slave_data_one_old,ecmdDataBufferBase *slave_data_two_old,ecmdDataBufferBase *master_data_one_old,ecmdDataBufferBase *master_data_two_old) -{ - ReturnCode rc; - //Start - Workaround Pre Training Section - HW205368 - procedure from Rob /Pete - - uint8_t max_group=1; - - if(master_interface==CP_FABRIC_X0){ - max_group=4; - } - - // Take backup of slave bad lane data restored by FW prior to training - FAPI_DBG("io_run_training: Saving Bad lane information for HW workaround "); - if(master_interface==CP_FABRIC_X0){ - for (int current_group = 0 ; current_group < max_group; current_group++){ - rc = GCR_read( slave_target, slave_interface, rx_lane_bad_vec_0_15_pg, current_group, 0, slave_data_one_old[current_group]); - if(rc){return rc;} - rc = GCR_read( slave_target, slave_interface, rx_lane_bad_vec_16_31_pg, current_group, 0, slave_data_two_old[current_group]); - if(rc){return rc;} - } - //Take backup of master bad lane data restored by FW prior to training - for (int current_group = 0 ; current_group < max_group; current_group++){ - rc = GCR_read( master_target, master_interface, rx_lane_bad_vec_0_15_pg, current_group, 0, master_data_one_old[current_group]); - if(rc){return rc;} - rc = GCR_read( master_target, master_interface, rx_lane_bad_vec_16_31_pg, current_group, 0, master_data_two_old[current_group]); - if(rc){return rc;} - } - }else{ - rc = GCR_read( slave_target, slave_interface, rx_lane_bad_vec_0_15_pg, slave_group, 0, slave_data_one_old[0]); - if(rc){return rc;} - rc = GCR_read( slave_target, slave_interface, rx_lane_bad_vec_16_31_pg, slave_group, 0, slave_data_two_old[0]); - if(rc){return rc;} - //Take backup of master bad lane data restored by FW prior to training - rc = GCR_read( master_target, master_interface, rx_lane_bad_vec_0_15_pg, master_group, 0, master_data_one_old[0]); - if(rc){return rc;} - rc = GCR_read( master_target, master_interface, rx_lane_bad_vec_16_31_pg, master_group, 0, master_data_two_old[0]); - if(rc){return rc;} - } - // End - Workaround HW205368 + // Take backup of slave bad lane data restored by FW prior to training + FAPI_DBG("io_run_training: Saving Bad lane information for HW workaround "); + if(master_interface==CP_FABRIC_X0){ + for (int current_group = 0 ; current_group < max_group; current_group++){ + rc = GCR_read( slave_target, slave_interface, rx_lane_bad_vec_0_15_pg, current_group, 0, slave_data_one_old[current_group]); + if(rc){return rc;} + rc = GCR_read( slave_target, slave_interface, rx_lane_bad_vec_16_31_pg, current_group, 0, slave_data_two_old[current_group]); + if(rc){return rc;} + } + //Take backup of master bad lane data restored by FW prior to training + for (int current_group = 0 ; current_group < max_group; current_group++){ + rc = GCR_read( master_target, master_interface, rx_lane_bad_vec_0_15_pg, current_group, 0, master_data_one_old[current_group]); + if(rc){return rc;} + rc = GCR_read( master_target, master_interface, rx_lane_bad_vec_16_31_pg, current_group, 0, master_data_two_old[current_group]); + if(rc){return rc;} + } + }else{ + rc = GCR_read( slave_target, slave_interface, rx_lane_bad_vec_0_15_pg, slave_group, 0, slave_data_one_old[0]); + if(rc){return rc;} + rc = GCR_read( slave_target, slave_interface, rx_lane_bad_vec_16_31_pg, slave_group, 0, slave_data_two_old[0]); + if(rc){return rc;} + //Take backup of master bad lane data restored by FW prior to training + rc = GCR_read( master_target, master_interface, rx_lane_bad_vec_0_15_pg, master_group, 0, master_data_one_old[0]); + if(rc){return rc;} + rc = GCR_read( master_target, master_interface, rx_lane_bad_vec_16_31_pg, master_group, 0, master_data_two_old[0]); + if(rc){return rc;} + } + // End - Workaround HW205368 return(rc); -} - -ReturnCode fir_workaround_post_training(const Target& master_target, io_interface_t master_interface,uint32_t master_group, const Target& slave_target, io_interface_t slave_interface,uint32_t slave_group, - ecmdDataBufferBase *slave_data_one_old,ecmdDataBufferBase *slave_data_two_old,ecmdDataBufferBase *master_data_one_old,ecmdDataBufferBase *master_data_two_old) -{ - ReturnCode rc; - //These buffers will store new bad lane info after training - ecmdDataBufferBase slave_data_one_new[4]; - ecmdDataBufferBase slave_data_two_new[4]; - ecmdDataBufferBase master_data_one_new[4]; - ecmdDataBufferBase master_data_two_new[4]; - fir_io_interface_t fir_master_interface=FIR_CP_IOMC0_P0; - fir_io_interface_t fir_slave_interface=FIR_CEN_DMI; - - uint8_t max_group=1; - - //Translate some enums in training header to fir enums - if(master_interface==CP_FABRIC_X0){ - fir_master_interface=FIR_CP_FABRIC_X0; - } - else if(master_interface==CP_IOMC0_P0){ - fir_master_interface= FIR_CP_IOMC0_P0; - } - else if(master_interface== CEN_DMI){ - fir_master_interface=FIR_CEN_DMI; - } - else if(master_interface== CP_FABRIC_A0){ - fir_master_interface=FIR_CP_FABRIC_A0; - } - if(slave_interface==CP_FABRIC_X0){ - fir_slave_interface=FIR_CP_FABRIC_X0; - } - else if(slave_interface==CP_IOMC0_P0){ - fir_slave_interface= FIR_CP_IOMC0_P0; - } - else if(slave_interface== CEN_DMI){ - fir_slave_interface=FIR_CEN_DMI; - } - else if(slave_interface== CP_FABRIC_A0){ - fir_slave_interface=FIR_CP_FABRIC_A0; - } + } + + ReturnCode fir_workaround_post_training(const Target& master_target, io_interface_t master_interface,uint32_t master_group, const Target& slave_target, io_interface_t slave_interface,uint32_t slave_group, + ecmdDataBufferBase *slave_data_one_old,ecmdDataBufferBase *slave_data_two_old,ecmdDataBufferBase *master_data_one_old,ecmdDataBufferBase *master_data_two_old) + { + ReturnCode rc; + //These buffers will store new bad lane info after training + ecmdDataBufferBase slave_data_one_new[4]; + ecmdDataBufferBase slave_data_two_new[4]; + ecmdDataBufferBase master_data_one_new[4]; + ecmdDataBufferBase master_data_two_new[4]; + fir_io_interface_t fir_master_interface=FIR_CP_IOMC0_P0; + fir_io_interface_t fir_slave_interface=FIR_CEN_DMI; + + uint8_t max_group=1; + + //Translate some enums in training header to fir enums + if(master_interface==CP_FABRIC_X0){ + fir_master_interface=FIR_CP_FABRIC_X0; + } + else if(master_interface==CP_IOMC0_P0){ + fir_master_interface= FIR_CP_IOMC0_P0; + } + else if(master_interface== CEN_DMI){ + fir_master_interface=FIR_CEN_DMI; + } + else if(master_interface== CP_FABRIC_A0){ + fir_master_interface=FIR_CP_FABRIC_A0; + } + if(slave_interface==CP_FABRIC_X0){ + fir_slave_interface=FIR_CP_FABRIC_X0; + } + else if(slave_interface==CP_IOMC0_P0){ + fir_slave_interface= FIR_CP_IOMC0_P0; + } + else if(slave_interface== CEN_DMI){ + fir_slave_interface=FIR_CEN_DMI; + } + else if(slave_interface== CP_FABRIC_A0){ + fir_slave_interface=FIR_CP_FABRIC_A0; + } else{ - FAPI_DBG("This is not a possible state since checking of these parms is done in top layer and error code returned "); - FAPI_SET_HWP_ERROR(rc, IO_RUN_TRAINING_INVALID_INVOCATION_RC); - return(rc); + FAPI_DBG("This is not a possible state since checking of these parms is done in top layer and error code returned "); + const fapi::Target &TARGET = master_target; + FAPI_SET_HWP_ERROR(rc, IO_RUN_TRAINING_POST_TRAINING_INVALID_INVOCATION_RC); + return(rc); } - - - if(master_interface==CP_FABRIC_X0){ - max_group=4; - } - - FAPI_DBG("io_run_training : Starting post training HW workaround "); - // Start post training part of Workaround - HW205368 - procedure from Rob /Pete - // Read slave side bad lane data after training - if(master_interface==CP_FABRIC_X0){ - for (int current_group = 0 ; current_group < max_group; current_group++){ - rc = GCR_read( slave_target, slave_interface, rx_lane_bad_vec_0_15_pg, current_group, 0, slave_data_one_new[current_group]); - if(rc){return rc;} - rc = GCR_read( slave_target, slave_interface, rx_lane_bad_vec_16_31_pg, current_group, 0, slave_data_two_new[current_group]); - if(rc){return rc;} - } - //Take backup of master bad lane data restored by FW prior to training - for (int current_group = 0 ; current_group < max_group; current_group++){ - rc = GCR_read( master_target, master_interface, rx_lane_bad_vec_0_15_pg, current_group, 0, master_data_one_new[current_group]); - if(rc){return rc;} - rc = GCR_read( master_target, master_interface, rx_lane_bad_vec_16_31_pg, current_group, 0, master_data_two_new[current_group]); - if(rc){return rc;} - } - }else{ - rc = GCR_read( slave_target, slave_interface, rx_lane_bad_vec_0_15_pg, slave_group, 0, slave_data_one_new[0]); - if(rc){return rc;} - rc = GCR_read( slave_target, slave_interface, rx_lane_bad_vec_16_31_pg, slave_group, 0, slave_data_two_new[0]); - if(rc){return rc;} - //Take backup of master bad lane data restored by FW prior to training - rc = GCR_read( master_target, master_interface, rx_lane_bad_vec_0_15_pg, master_group, 0, master_data_one_new[0]); - if(rc){return rc;} - rc = GCR_read( master_target, master_interface, rx_lane_bad_vec_16_31_pg, master_group, 0, master_data_two_new[0]); - if(rc){return rc;} - } - // Now we will compare the old and new bad lane data and take appropriate action - if(master_interface==CP_FABRIC_X0) - { - for (int current_group = 0 ; current_group < max_group; current_group++){ - if(slave_data_one_new[current_group]==slave_data_one_old[current_group] && slave_data_two_new[current_group]==slave_data_two_old[current_group] ){ - // If old and new data is same , no need to present FIRs to PRD - if( !( slave_data_one_new[current_group].isBitClear(0,16) && slave_data_two_new[current_group].isBitClear(0,16) )){ - FAPI_DBG("io_run_training : Clear invalid FIRs on the slave side "); - // If all bad lane info is clear in new data then no need to clear ,this is a 0==0 case of both old and new empty vectors - io_clear_firs(slave_target); - clear_fir_summary_reg(slave_target,fir_slave_interface); - if(rc) return rc; - clear_fir_summary_reg(master_target,fir_master_interface); - if(rc) return rc; - } - } - if(master_data_one_new[current_group]==master_data_one_old[current_group] && master_data_two_new[current_group]==master_data_two_old[current_group] ){ - // If old and new data is same , no need to present FIRs to PRD - if( !( master_data_one_new[current_group].isBitClear(0,16) && master_data_two_new[current_group].isBitClear(0,16) )){ - FAPI_DBG("io_run_training : Clear invalid FIRs on the master side "); - // If all bad lane info is clear in new data then no need to clear ,this is a 0==0 case of both old and new empty vectors - io_clear_firs(master_target); - clear_fir_summary_reg(slave_target,fir_slave_interface); - if(rc) return rc; - clear_fir_summary_reg(master_target,fir_master_interface); - if(rc) return rc; - } - } - } - } - else - { - if(slave_data_one_new[0]==slave_data_one_old[0] && slave_data_two_new[0]==slave_data_two_old[0] ){ - // If old and new data is same , no need to present FIRs to PRD - if( !( slave_data_one_new[0].isBitClear(0,16) && slave_data_two_new[0].isBitClear(0,16) )){ - FAPI_DBG("io_run_training : Clear invalid FIRs on the slave side "); - // If all bad lane info is clear in new data then no need to clear ,this is a 0==0 case of both old and new empty vectors - io_clear_firs(slave_target); - clear_fir_summary_reg(slave_target,fir_slave_interface); - if(rc) return rc; - clear_fir_summary_reg(master_target,fir_master_interface); - if(rc) return rc; - } - } - if(master_data_one_new[0]==master_data_one_old[0] && master_data_two_new[0]==master_data_two_old[0] ){ - // If old and new data is same , no need to present FIRs to PRD - if( !( master_data_one_new[0].isBitClear(0,16) && master_data_two_new[0].isBitClear(0,16) )){ - FAPI_DBG("io_run_training : Clear invalid FIRs on the master side "); - // If all bad lane info is clear in new data then no need to clear ,this is a 0==0 case of both old and new empty vectors - io_clear_firs(master_target); - clear_fir_summary_reg(slave_target,fir_slave_interface); - if(rc) return rc; - clear_fir_summary_reg(master_target,fir_master_interface); - if(rc) return rc; - } - } - } - - - FAPI_DBG("io_run_training : Clearing FIR masks now-- REORDER"); - //Finally Unmask the LFIR to let PRD take action post training - rc=clear_fir_mask_reg(slave_target,fir_slave_interface); - if(rc) return rc; - rc=clear_fir_mask_reg(master_target,fir_master_interface); - // END post training part of Workaround - HW205368 - procedure from Rob /Pete - - -return rc; - -} - -// //HW249235 --For DLL workaround -// This function will check DLL status on slave and slave side . If any DLL has failed it will update to the next valid -// DLL value . 3,4,5,6 are valid values that we are given to select. -// This will continue until we run out of valid DLL reg selects or when the DLL cal passes - -ReturnCode check_dll_status_and_modify(const Target &master_target, io_interface_t master_interface,const Target &slave_target, - io_interface_t slave_interface,bool dll_master_array[], - bool dll_slave_array[],bool &dll_workaround_done,bool &dll_workaround_fail) -{ - ReturnCode rc; - uint32_t rc_ecmd=0; - ecmdDataBufferBase dll_reg(16),set_bits(16),clear_bits(16),temp_bits(16); - const uint16_t dll_vals[]={2,3,4,5,6,7}; - uint16_t bits=0; - uint16_t dll_value=0; - bool found_dll_master=false; - bool found_dll_slave=false; - bool found_dll_master_groups=false; - bool found_dll_slave_groups=false; - //bool dump_ffdc=false; - - bits=ei4_rx_dll_vreg_ref_sel_clear; - rc_ecmd=clear_bits.insert(bits,0,16); - - if(rc_ecmd) - { - FAPI_ERR("Failed buffer intialization in DLL workaround function \n"); - rc.setEcmdError(rc_ecmd); - return(rc); - } - - FAPI_INF("DLL WORKAROUND CODE executing"); - // First we will populate current DLL values into std::vector - for (int current_group = 0 ; current_group < 4; current_group++){ + + + if(master_interface==CP_FABRIC_X0){ + max_group=4; + } + + FAPI_DBG("io_run_training : Starting post training HW workaround "); + // Start post training part of Workaround - HW205368 - procedure from Rob /Pete + // Read slave side bad lane data after training + if(master_interface==CP_FABRIC_X0){ + for (int current_group = 0 ; current_group < max_group; current_group++){ + rc = GCR_read( slave_target, slave_interface, rx_lane_bad_vec_0_15_pg, current_group, 0, slave_data_one_new[current_group]); + if(rc){return rc;} + rc = GCR_read( slave_target, slave_interface, rx_lane_bad_vec_16_31_pg, current_group, 0, slave_data_two_new[current_group]); + if(rc){return rc;} + } + //Take backup of master bad lane data restored by FW prior to training + for (int current_group = 0 ; current_group < max_group; current_group++){ + rc = GCR_read( master_target, master_interface, rx_lane_bad_vec_0_15_pg, current_group, 0, master_data_one_new[current_group]); + if(rc){return rc;} + rc = GCR_read( master_target, master_interface, rx_lane_bad_vec_16_31_pg, current_group, 0, master_data_two_new[current_group]); + if(rc){return rc;} + } + }else{ + rc = GCR_read( slave_target, slave_interface, rx_lane_bad_vec_0_15_pg, slave_group, 0, slave_data_one_new[0]); + if(rc){return rc;} + rc = GCR_read( slave_target, slave_interface, rx_lane_bad_vec_16_31_pg, slave_group, 0, slave_data_two_new[0]); + if(rc){return rc;} + //Take backup of master bad lane data restored by FW prior to training + rc = GCR_read( master_target, master_interface, rx_lane_bad_vec_0_15_pg, master_group, 0, master_data_one_new[0]); + if(rc){return rc;} + rc = GCR_read( master_target, master_interface, rx_lane_bad_vec_16_31_pg, master_group, 0, master_data_two_new[0]); + if(rc){return rc;} + } + // Now we will compare the old and new bad lane data and take appropriate action + if(master_interface==CP_FABRIC_X0) + { + for (int current_group = 0 ; current_group < max_group; current_group++){ + if(slave_data_one_new[current_group]==slave_data_one_old[current_group] && slave_data_two_new[current_group]==slave_data_two_old[current_group] ){ + // If old and new data is same , no need to present FIRs to PRD + if( !( slave_data_one_new[current_group].isBitClear(0,16) && slave_data_two_new[current_group].isBitClear(0,16) )){ + FAPI_DBG("io_run_training : Clear invalid FIRs on the slave side "); + // If all bad lane info is clear in new data then no need to clear ,this is a 0==0 case of both old and new empty vectors + rc = io_clear_firs(slave_target); + if(rc) return rc; + rc = clear_fir_summary_reg(slave_target,fir_slave_interface); + if(rc) return rc; + rc = clear_fir_summary_reg(master_target,fir_master_interface); + if(rc) return rc; + } + } + if(master_data_one_new[current_group]==master_data_one_old[current_group] && master_data_two_new[current_group]==master_data_two_old[current_group] ){ + // If old and new data is same , no need to present FIRs to PRD + if( !( master_data_one_new[current_group].isBitClear(0,16) && master_data_two_new[current_group].isBitClear(0,16) )){ + FAPI_DBG("io_run_training : Clear invalid FIRs on the master side "); + // If all bad lane info is clear in new data then no need to clear ,this is a 0==0 case of both old and new empty vectors + rc = io_clear_firs(master_target); + if(rc) return rc; + rc = clear_fir_summary_reg(slave_target,fir_slave_interface); + if(rc) return rc; + rc = clear_fir_summary_reg(master_target,fir_master_interface); + if(rc) return rc; + } + } + } + } + else + { + if(slave_data_one_new[0]==slave_data_one_old[0] && slave_data_two_new[0]==slave_data_two_old[0] ){ + // If old and new data is same , no need to present FIRs to PRD + if( !( slave_data_one_new[0].isBitClear(0,16) && slave_data_two_new[0].isBitClear(0,16) )){ + FAPI_DBG("io_run_training : Clear invalid FIRs on the slave side "); + // If all bad lane info is clear in new data then no need to clear ,this is a 0==0 case of both old and new empty vectors + rc = io_clear_firs(slave_target); + if(rc) return rc; + rc = clear_fir_summary_reg(slave_target,fir_slave_interface); + if(rc) return rc; + rc = clear_fir_summary_reg(master_target,fir_master_interface); + if(rc) return rc; + } + } + if(master_data_one_new[0]==master_data_one_old[0] && master_data_two_new[0]==master_data_two_old[0] ){ + // If old and new data is same , no need to present FIRs to PRD + if( !( master_data_one_new[0].isBitClear(0,16) && master_data_two_new[0].isBitClear(0,16) )){ + FAPI_DBG("io_run_training : Clear invalid FIRs on the master side "); + // If all bad lane info is clear in new data then no need to clear ,this is a 0==0 case of both old and new empty vectors + rc = io_clear_firs(master_target); + if(rc) return rc; + rc = clear_fir_summary_reg(slave_target,fir_slave_interface); + if(rc) return rc; + rc = clear_fir_summary_reg(master_target,fir_master_interface); + if(rc) return rc; + } + } + } + + + FAPI_DBG("io_run_training : Clearing FIR masks now-- REORDER"); + //Finally Unmask the LFIR to let PRD take action post training + rc=clear_fir_mask_reg(slave_target,fir_slave_interface); + if(rc) return rc; + rc=clear_fir_mask_reg(master_target,fir_master_interface); + // END post training part of Workaround - HW205368 - procedure from Rob /Pete + + + return rc; + + } + + // //HW249235 --For DLL workaround + // This function will check DLL status on slave and slave side . If any DLL has failed it will update to the next valid + // DLL value . 3,4,5,6 are valid values that we are given to select. + // This will continue until we run out of valid DLL reg selects or when the DLL cal passes + + ReturnCode check_dll_status_and_modify(const Target &master_target, io_interface_t master_interface,const Target &slave_target, + io_interface_t slave_interface,bool dll_master_array[], + bool dll_slave_array[],bool &dll_workaround_done,bool &dll_workaround_fail) + { + ReturnCode rc; + uint32_t rc_ecmd=0; + ecmdDataBufferBase dll_reg(16),set_bits(16),clear_bits(16),temp_bits(16); + const uint16_t dll_vals[]={2,3,4,5,6,7}; + uint16_t bits=0; + uint16_t dll_value=0; + bool found_dll_master=false; + bool found_dll_slave=false; + bool found_dll_master_groups=false; + bool found_dll_slave_groups=false; + //bool dump_ffdc=false; + + bits=ei4_rx_dll_vreg_ref_sel_clear; + rc_ecmd=clear_bits.insert(bits,0,16); + + if(rc_ecmd) + { + FAPI_ERR("Failed buffer intialization in DLL workaround function \n"); + rc.setEcmdError(rc_ecmd); + return(rc); + } + + FAPI_INF("DLL WORKAROUND CODE executing"); + // First we will populate current DLL values into std::vector + for (int current_group = 0 ; current_group < 4; current_group++){ // slave side operations - rc = GCR_read( slave_target, slave_interface, ei4_rx_dll_analog_tweaks_pg, current_group, 0, dll_reg); - if(rc){return rc;} - rc_ecmd|=dll_reg.extract( &dll_value, 4, 3 ); - if(rc_ecmd) - { + rc = GCR_read( slave_target, slave_interface, ei4_rx_dll_analog_tweaks_pg, current_group, 0, dll_reg); + if(rc){return rc;} + rc_ecmd|=dll_reg.extract( &dll_value, 4, 3 ); + if(rc_ecmd) + { FAPI_ERR("Failed buffer intialization in DLL workaround function \n"); rc.setEcmdError(rc_ecmd); return(rc); - } - - FAPI_DBG("Extracted DLL value is %d",dll_value); - dll_value=dll_value>>13; - FAPI_DBG("DLL value for %d clock group is %d on slave side",current_group,dll_value); - if(rc){return rc;} - - if(dll_value>=dll_vals[0] && dll_value<=dll_vals[5]){ + } + + FAPI_DBG("Extracted DLL value is %d",dll_value); + dll_value=dll_value>>13; + FAPI_DBG("DLL value for %d clock group is %d on slave side",current_group,dll_value); + if(rc){return rc;} + + if(dll_value>=dll_vals[0] && dll_value<=dll_vals[5]){ dll_slave_array[current_group*6+(dll_value-dll_vals[0])]=true; - } - else{ - FAPI_ERR("DLL Vreg Cal sel value out of bounds for workaround !!"); - FAPI_SET_HWP_ERROR(rc, IO_RUN_TRAINING_DLL_VAL_OUT_OF_BOUND_RC); - return rc; - } - - rc = GCR_read( slave_target, slave_interface, ei4_rx_dll_cal_cntl_pg, current_group, 0, dll_reg); - if(rc){return rc;} - if(dll_reg.isBitSet(1) || dll_reg.isBitSet(2) || dll_reg.isBitSet(9) || dll_reg.isBitSet(10)){ - // Some DLL error is present , lets push this Clock group ref cal value to the next untried value - FAPI_DBG("DLL error detected on clock group %d on slave target",current_group); - - rc=GCR_write(slave_target, slave_interface, ei4_rx_dll_cal_cntl_pg, current_group,0, temp_bits, temp_bits,1,1); - if(rc){return rc;} - rc=GCR_write(master_target, master_interface, ei4_rx_dll_cal_cntl_pg, current_group,0, temp_bits, temp_bits,1,1); - if(rc){return rc;} - for(int dll_valid=0;dll_valid<6;++dll_valid){ + } + else{ + FAPI_ERR("DLL Vreg Cal sel value out of bounds for workaround !!"); + const fapi::Target &TARGET = slave_target; + ecmdDataBufferBase &DLL_REG=dll_reg; + FAPI_SET_HWP_ERROR(rc, IO_RUN_TRAINING_CHECK_DLL_VAL_OUT_OF_BOUND_RC); + return rc; + } + + rc = GCR_read( slave_target, slave_interface, ei4_rx_dll_cal_cntl_pg, current_group, 0, dll_reg); + if(rc){return rc;} + if(dll_reg.isBitSet(1) || dll_reg.isBitSet(2) || dll_reg.isBitSet(9) || dll_reg.isBitSet(10)){ + // Some DLL error is present , lets push this Clock group ref cal value to the next untried value + FAPI_DBG("DLL error detected on clock group %d on slave target",current_group); + + rc=GCR_write(slave_target, slave_interface, ei4_rx_dll_cal_cntl_pg, current_group,0, temp_bits, temp_bits,1,1); + if(rc){return rc;} + rc=GCR_write(master_target, master_interface, ei4_rx_dll_cal_cntl_pg, current_group,0, temp_bits, temp_bits,1,1); + if(rc){return rc;} + for(int dll_valid=0;dll_valid<6;++dll_valid){ if(dll_slave_array[current_group*6 + dll_valid]==false){ - // Now set the DLL vref cal sel reg value to the next valid untried value - dll_value=dll_vals[dll_valid]; - FAPI_DBG("DLL value to be written is %d dll_valid=%d current_group=%d",dll_value,dll_valid,current_group); - rc=GCR_read(slave_target , slave_interface, ei4_rx_dll_analog_tweaks_pg, current_group,0, set_bits); - if(rc){return rc;} - rc_ecmd=set_bits.insert(dll_value,4,3,13); - if(rc_ecmd) - { - FAPI_ERR("Failed buffer insertion in DLL workaround function \n"); - rc.setEcmdError(rc_ecmd); - return rc; - } - rc=GCR_write(slave_target, slave_interface, ei4_rx_dll_analog_tweaks_pg, current_group,0, set_bits, clear_bits); - if(rc){return rc;} - found_dll_slave=true; - dll_slave_array[current_group*6 + dll_valid]=true; - break; + // Now set the DLL vref cal sel reg value to the next valid untried value + dll_value=dll_vals[dll_valid]; + FAPI_DBG("DLL value to be written is %d dll_valid=%d current_group=%d",dll_value,dll_valid,current_group); + rc=GCR_read(slave_target , slave_interface, ei4_rx_dll_analog_tweaks_pg, current_group,0, set_bits); + if(rc){return rc;} + rc_ecmd=set_bits.insert(dll_value,4,3,13); + if(rc_ecmd) + { + FAPI_ERR("Failed buffer insertion in DLL workaround function \n"); + rc.setEcmdError(rc_ecmd); + return rc; + } + rc=GCR_write(slave_target, slave_interface, ei4_rx_dll_analog_tweaks_pg, current_group,0, set_bits, clear_bits); + if(rc){return rc;} + found_dll_slave=true; + dll_slave_array[current_group*6 + dll_valid]=true; + break; } - } - if(found_dll_slave==false){ + } + if(found_dll_slave==false){ FAPI_ERR("No valid DLL reg value left to search.. DLL cal on slave of this channel has failed "); // Now do FFDC call outs //dump_ffdc=true; dll_workaround_fail=true; - FAPI_SET_HWP_ERROR(rc,IO_RUN_TRAINING_DLL_WORKAROUND_FAIL); + const fapi::Target &TARGET = slave_target; + ecmdDataBufferBase &DLL_REG=dll_reg; + FAPI_SET_HWP_ERROR(rc,IO_RUN_TRAINING_CHECK_DLL_WORKAROUND_FAIL); return rc; - } - } - else{ - FAPI_DBG("NO DLL error detected on clock group %d on slave target",current_group); - } - - if(!found_dll_slave){ // If slave has DLL failure , Master status is invalid - John G - // master SIDE operations - // Push current DLL value into the std::vector - dll_reg.flushTo0(); - rc = GCR_read( master_target, master_interface, ei4_rx_dll_analog_tweaks_pg, current_group, 0, dll_reg); - if(rc){return rc;} - rc_ecmd|=dll_reg.extract( &dll_value, 4, 3 ); - if(rc_ecmd) - { - FAPI_ERR("Failed buffer intialization in DLL workaround function \n"); + } + } + else{ + FAPI_DBG("NO DLL error detected on clock group %d on slave target",current_group); + } + + if(!found_dll_slave){ // If slave has DLL failure , Master status is invalid - John G + // master SIDE operations + // Push current DLL value into the std::vector + rc_ecmd |= dll_reg.flushTo0(); + if(rc_ecmd) + { + FAPI_ERR("Failed buffer intialization in DLL workaround function \n"); + rc.setEcmdError(rc_ecmd); + return rc; + } + rc = GCR_read( master_target, master_interface, ei4_rx_dll_analog_tweaks_pg, current_group, 0, dll_reg); + if(rc){return rc;} + rc_ecmd|=dll_reg.extract( &dll_value, 4, 3 ); + if(rc_ecmd) + { + FAPI_ERR("Failed buffer intialization in DLL workaround function \n"); + rc.setEcmdError(rc_ecmd); + return rc; + } + + FAPI_DBG("Extracted DLL value is %d",dll_value); + dll_value=dll_value>>13; + FAPI_DBG("DLL value for %d clock group is %d on master side",current_group,dll_value); + if(rc){return rc;} + if(dll_value>=dll_vals[0] && dll_value<=dll_vals[5]){ + dll_master_array[current_group*6+(dll_value-dll_vals[0])]=true; + } + else{ + FAPI_ERR("DLL Vreg Cal sel value out of bounds for workaround !!"); + const fapi::Target &TARGET = slave_target; + ecmdDataBufferBase &DLL_REG=dll_reg; + FAPI_SET_HWP_ERROR(rc, IO_RUN_TRAINING_CHECK_DLL_VAL_OUT_OF_BOUND_RC); + return rc; + } + rc = GCR_read( master_target, master_interface, ei4_rx_dll_cal_cntl_pg, current_group, 0, dll_reg); + if(rc){return rc;} + if(dll_reg.isBitSet(1) || dll_reg.isBitSet(2) || dll_reg.isBitSet(9) || dll_reg.isBitSet(10)){ + // Some DLL error is present , lets push this Clock group to the next untried value + FAPI_DBG("DLL error detected on clock group %d on master target",current_group); + rc=GCR_write(slave_target, slave_interface, ei4_rx_dll_cal_cntl_pg, current_group,0, temp_bits, temp_bits,1,1); + if(rc){return rc;} + rc=GCR_write(master_target, master_interface, ei4_rx_dll_cal_cntl_pg, current_group,0, temp_bits, temp_bits,1,1); + if(rc){return rc;} + + for(int dll_valid=0;dll_valid<6;++dll_valid){ + if(dll_master_array[current_group*6 + dll_valid]==false){ + // Now set the DLL vref cal sel reg value to the next valid untried value + dll_value=dll_vals[dll_valid]; + FAPI_DBG("DLL value to be written is %d",dll_value); + rc=GCR_read(master_target , master_interface, ei4_rx_dll_analog_tweaks_pg, current_group,0, set_bits); + if(rc){return rc;} + rc_ecmd=set_bits.insert(dll_value,4,3,13); + if(rc_ecmd) + { + FAPI_ERR("Failed buffer insertion in DLL workaround function \n"); + rc.setEcmdError(rc_ecmd); + return rc; + } + rc=GCR_write(master_target, master_interface, ei4_rx_dll_analog_tweaks_pg, current_group,0, set_bits, clear_bits); + if(rc){return rc;} + found_dll_master=true; + dll_master_array[current_group*6 + dll_valid]=true; + break; + } + } + if(found_dll_master==false){ + FAPI_ERR("No valid DLL reg value left to search.. DLL cal on master of this channel has failed "); + //dump_ffdc=true; + } + } + else{ + FAPI_DBG("NO DLL error detected on clock group %d on master target",current_group); + } + + } + if(found_dll_master){ + found_dll_master_groups=true; + } + if(found_dll_slave){ + found_dll_slave_groups=true; + } + } + + if(found_dll_master_groups || found_dll_slave_groups ) { + // at least one clock group on a slave or slave had a DLL fail and valid values to try so we will ask wrapper to continue the + // workaround invocations + FAPI_DBG("One setting failed on master or slave "); + dll_workaround_done=false; + } + else{ + // No DLL fail or no Vreg sel values left to try out so we are done + dll_workaround_done=true; + FAPI_DBG("DLL Workaround done in checker function"); + //if(dump_ffdc){ + // rc=edi_training::dump_dll_ffdc(master_target,master_interface,slave_target,slave_interface); + //} + } + + + return rc; + } + + ReturnCode set_tx_drv_pattern(const Target &master_target, io_interface_t master_interface,uint32_t master_group,const Target &slave_target, + io_interface_t slave_interface,uint32_t slave_group) + { + ReturnCode rc; + uint32_t rc_ecmd=0; + // For DLL shmoo workaround + ecmdDataBufferBase set_bits(16),clear_bits(16),clear_train_bits(16); + uint16_t bits=0; + + FAPI_DBG("DLL workaround : Setting TX DRV pattern back to 0000 before restarting training on X bus "); + // Clear Clk pattern + bits=ei4_tx_drv_data_pattern_gcrmsg_clear; + rc_ecmd=clear_bits.insert(bits,0,16); + if(rc_ecmd) + { + FAPI_ERR("Failed buffer intialization in DLL workaround function \n"); + rc.setEcmdError(rc_ecmd); + return rc; + } + rc=GCR_write(slave_target, slave_interface,ei4_tx_data_cntl_gcrmsg_pl , 15,31, set_bits, clear_bits,1,1); + if(rc){return rc;} + rc=GCR_write(master_target, master_interface,ei4_tx_data_cntl_gcrmsg_pl , 15,31, set_bits, clear_bits,1,1); + if(rc){return rc;} + //Clear Data pattern + bits=ei4_tx_drv_clk_pattern_gcrmsg_clear; + rc_ecmd=clear_bits.insert(bits,0,16); + if(rc_ecmd) + { + FAPI_ERR("Failed buffer intialization in DLL workaround function \n"); + rc.setEcmdError(rc_ecmd); + return rc; + } + rc=GCR_write(slave_target, slave_interface, ei4_tx_clk_cntl_gcrmsg_pg , 15,0, set_bits, clear_bits,1,1); + if(rc){return rc;} + rc=GCR_write(master_target, master_interface, ei4_tx_clk_cntl_gcrmsg_pg , 15,0, set_bits, clear_bits,1,1); + if(rc){return rc;} + + // According to John G , This reset is required as well + bits= ei4_rx_wt_cu_pll_reset_clear ; + rc_ecmd = clear_bits.insert(bits,0,16); + rc_ecmd |= set_bits.flushTo0(); + if(rc_ecmd) + { + FAPI_ERR("Failed buffer intialization in DLL workaround function \n"); + rc.setEcmdError(rc_ecmd); + return rc; + } + //Reset wt_cu_pll & Wiretest status & Start bits + for (int current_group = 0 ; current_group < 4; current_group++){ + //Reset training start and status bits - as per Rob + rc=GCR_write(slave_target , slave_interface, ei4_rx_training_start_pg,current_group,0, set_bits, clear_train_bits,1,1); + if(rc){return rc;} + rc=GCR_write(slave_target , slave_interface, ei4_rx_training_status_pg, current_group,0, set_bits,clear_train_bits,1,1); + if(rc){return rc;} + //Reset Wt PLL as per John G + rc=GCR_write(slave_target, slave_interface, ei4_rx_wiretest_pll_cntl_pg , current_group,0, set_bits, clear_bits,1,1); + if(rc){return rc;} + + //Reset training start and status bits - as per Rob + rc=GCR_write(master_target , master_interface, ei4_rx_training_start_pg,current_group,0, set_bits, clear_train_bits,1,1); + if(rc){return rc;} + rc=GCR_write(master_target , master_interface, ei4_rx_training_status_pg, current_group,0, set_bits,clear_train_bits,1,1); + if(rc){return rc;} + // Reset Wt PLL as per John G + rc=GCR_write(master_target, master_interface, ei4_rx_wiretest_pll_cntl_pg , current_group,0, set_bits, clear_bits,1,1); + if(rc){return rc;} + } + + + FAPI_DBG("Done Setting TX Drv pattern to 0000 and wt_cu_pll_reset to 0 for DLL workaround "); + return rc; + } + + //HW Defect HW220449 , HW HW247831 + // Set rx_sls_extend_sel=001 on slave side of X bus post training + ReturnCode do_sls_fix(const Target &slave_target, io_interface_t slave_interface) + { + ReturnCode rc; + uint32_t rc_ecmd=0; + ecmdDataBufferBase set_bits(16),clear_bits(16); + uint16_t bits=1; + + FAPI_DBG("Setting rx_extend_sel to 001 for all Xbus slaves for HW220449"); + for (int current_group = 0 ; current_group < 4; current_group++){ + rc = GCR_read( slave_target, slave_interface,ei4_rx_spare_mode_pg, current_group, 0, set_bits); + if(rc){return rc;} + rc_ecmd = set_bits.insert(bits,5,3,13); // insert rx_sls_extend_sel + if(rc_ecmd) + { + FAPI_ERR("Failed buffer manipulation in do_sls_fix \n"); rc.setEcmdError(rc_ecmd); return rc; - } - - FAPI_DBG("Extracted DLL value is %d",dll_value); - dll_value=dll_value>>13; - FAPI_DBG("DLL value for %d clock group is %d on master side",current_group,dll_value); - if(rc){return rc;} - if(dll_value>=dll_vals[0] && dll_value<=dll_vals[5]){ - dll_master_array[current_group*6+(dll_value-dll_vals[0])]=true; - } - else{ - FAPI_ERR("DLL Vreg Cal sel value out of bounds for workaround !!"); - FAPI_SET_HWP_ERROR(rc, IO_RUN_TRAINING_DLL_VAL_OUT_OF_BOUND_RC); - return rc; - } - rc = GCR_read( master_target, master_interface, ei4_rx_dll_cal_cntl_pg, current_group, 0, dll_reg); - if(rc){return rc;} - if(dll_reg.isBitSet(1) || dll_reg.isBitSet(2) || dll_reg.isBitSet(9) || dll_reg.isBitSet(10)){ - // Some DLL error is present , lets push this Clock group to the next untried value - FAPI_DBG("DLL error detected on clock group %d on master target",current_group); - rc=GCR_write(slave_target, slave_interface, ei4_rx_dll_cal_cntl_pg, current_group,0, temp_bits, temp_bits,1,1); - if(rc){return rc;} - rc=GCR_write(master_target, master_interface, ei4_rx_dll_cal_cntl_pg, current_group,0, temp_bits, temp_bits,1,1); - if(rc){return rc;} - - for(int dll_valid=0;dll_valid<6;++dll_valid){ - if(dll_master_array[current_group*6 + dll_valid]==false){ - // Now set the DLL vref cal sel reg value to the next valid untried value - dll_value=dll_vals[dll_valid]; - FAPI_DBG("DLL value to be written is %d",dll_value); - rc=GCR_read(master_target , master_interface, ei4_rx_dll_analog_tweaks_pg, current_group,0, set_bits); - if(rc){return rc;} - rc_ecmd=set_bits.insert(dll_value,4,3,13); - if(rc_ecmd) - { - FAPI_ERR("Failed buffer insertion in DLL workaround function \n"); - rc.setEcmdError(rc_ecmd); - return rc; - } - rc=GCR_write(master_target, master_interface, ei4_rx_dll_analog_tweaks_pg, current_group,0, set_bits, clear_bits); - if(rc){return rc;} - found_dll_master=true; - dll_master_array[current_group*6 + dll_valid]=true; - break; - } - } - if(found_dll_master==false){ - FAPI_ERR("No valid DLL reg value left to search.. DLL cal on master of this channel has failed "); - //dump_ffdc=true; - } - } - else{ - FAPI_DBG("NO DLL error detected on clock group %d on master target",current_group); - } - - } - if(found_dll_master){ - found_dll_master_groups=true; - } - if(found_dll_slave){ - found_dll_slave_groups=true; - } - } - - if(found_dll_master_groups || found_dll_slave_groups ) { - // at least one clock group on a slave or slave had a DLL fail and valid values to try so we will ask wrapper to continue the - // workaround invocations - FAPI_DBG("One setting failed on master or slave "); - dll_workaround_done=false; - } - else{ - // No DLL fail or no Vreg sel values left to try out so we are done - dll_workaround_done=true; - FAPI_DBG("DLL Workaround done in checker function"); - //if(dump_ffdc){ - // rc=edi_training::dump_dll_ffdc(master_target,master_interface,slave_target,slave_interface); - //} - } - - - return rc; -} - -ReturnCode set_tx_drv_pattern(const Target &master_target, io_interface_t master_interface,uint32_t master_group,const Target &slave_target, - io_interface_t slave_interface,uint32_t slave_group) -{ - ReturnCode rc; - uint32_t rc_ecmd=0; - // For DLL shmoo workaround - ecmdDataBufferBase set_bits(16),clear_bits(16),clear_train_bits(16); - uint16_t bits=0; - - FAPI_DBG("DLL workaround : Setting TX DRV pattern back to 0000 before restarting training on X bus "); - // Clear Clk pattern - bits=ei4_tx_drv_data_pattern_gcrmsg_clear; - rc_ecmd=clear_bits.insert(bits,0,16); - if(rc_ecmd) - { - FAPI_ERR("Failed buffer intialization in DLL workaround function \n"); - rc.setEcmdError(rc_ecmd); - return rc; - } - rc=GCR_write(slave_target, slave_interface,ei4_tx_data_cntl_gcrmsg_pl , 15,31, set_bits, clear_bits,1,1); - if(rc){return rc;} - rc=GCR_write(master_target, master_interface,ei4_tx_data_cntl_gcrmsg_pl , 15,31, set_bits, clear_bits,1,1); - if(rc){return rc;} - //Clear Data pattern - bits=ei4_tx_drv_clk_pattern_gcrmsg_clear; - rc_ecmd=clear_bits.insert(bits,0,16); - if(rc_ecmd) - { - FAPI_ERR("Failed buffer intialization in DLL workaround function \n"); - rc.setEcmdError(rc_ecmd); - return rc; - } - rc=GCR_write(slave_target, slave_interface, ei4_tx_clk_cntl_gcrmsg_pg , 15,0, set_bits, clear_bits,1,1); - if(rc){return rc;} - rc=GCR_write(master_target, master_interface, ei4_tx_clk_cntl_gcrmsg_pg , 15,0, set_bits, clear_bits,1,1); - if(rc){return rc;} - - // According to John G , This reset is required as well - bits= ei4_rx_wt_cu_pll_reset_clear ; - rc_ecmd=clear_bits.insert(bits,0,16); - if(rc_ecmd) - { - FAPI_ERR("Failed buffer intialization in DLL workaround function \n"); - rc.setEcmdError(rc_ecmd); - return rc; - } - set_bits.flushTo0(); - //Reset wt_cu_pll & Wiretest status & Start bits - for (int current_group = 0 ; current_group < 4; current_group++){ - //Reset training start and status bits - as per Rob - rc=GCR_write(slave_target , slave_interface, ei4_rx_training_start_pg,current_group,0, set_bits, clear_train_bits,1,1); - if(rc){return rc;} - rc=GCR_write(slave_target , slave_interface, ei4_rx_training_status_pg, current_group,0, set_bits,clear_train_bits,1,1); - if(rc){return rc;} - //Reset Wt PLL as per John G - rc=GCR_write(slave_target, slave_interface, ei4_rx_wiretest_pll_cntl_pg , current_group,0, set_bits, clear_bits,1,1); - if(rc){return rc;} - - //Reset training start and status bits - as per Rob - rc=GCR_write(master_target , master_interface, ei4_rx_training_start_pg,current_group,0, set_bits, clear_train_bits,1,1); - if(rc){return rc;} - rc=GCR_write(master_target , master_interface, ei4_rx_training_status_pg, current_group,0, set_bits,clear_train_bits,1,1); - if(rc){return rc;} - // Reset Wt PLL as per John G - rc=GCR_write(master_target, master_interface, ei4_rx_wiretest_pll_cntl_pg , current_group,0, set_bits, clear_bits,1,1); - if(rc){return rc;} - } - - - FAPI_DBG("Done Setting TX Drv pattern to 0000 and wt_cu_pll_reset to 0 for DLL workaround "); - return rc; -} - -//HW Defect HW220449 , HW HW247831 -// Set rx_sls_extend_sel=001 on slave side of X bus post training -ReturnCode do_sls_fix(const Target &slave_target, io_interface_t slave_interface) -{ - ReturnCode rc; - ecmdDataBufferBase set_bits(16),clear_bits(16); - uint16_t bits=1; - - FAPI_DBG("Setting rx_extend_sel to 001 for all Xbus slaves for HW220449"); - for (int current_group = 0 ; current_group < 4; current_group++){ - rc = GCR_read( slave_target, slave_interface,ei4_rx_spare_mode_pg, current_group, 0, set_bits); - set_bits.insert(bits,5,3,13); // insert rx_sls_extend_sel - rc=GCR_write(slave_target, slave_interface, ei4_rx_spare_mode_pg , current_group,0, set_bits, clear_bits); - } - return rc; -} - -// To handle the MAX_SPARE_EXCEEDED FIR case which we have to handle here in our HWP instead of waiting for PRD. -ReturnCode handle_max_spare(const Target &target,io_interface_t interface,uint8_t current_group){ - ReturnCode o_rc; - ecmdDataBufferBase error_data(16); - uint32_t bitPos=0x2680; - - if(interface==CP_FABRIC_X0){ - o_rc=GCR_read(target , interface, ei4_rx_fir_training_pg, current_group,0, error_data); - } - else{ - o_rc=GCR_read(target , interface, rx_fir_training_pg, current_group,0, error_data); - } - if(o_rc) - return o_rc; - if(error_data.isBitSet(2,1)){ // can be caused by a static (pre training - bit 2) or dynamic (post training - bit 5) or recal(bit 8) - FAPI_ERR("MAX_SPARE_EXCEEDED ON THIS BUS clock group %d",current_group); - error_data.setAnd(bitPos,0,16); - ecmdDataBufferBase & SPARE_ERROR_REG = error_data; //bit2 /bit 5 /bit 8of the register represents the max spare exceeded bit.To determine what caused the max spares exceeded error - const fapi::Target & CHIP_TARGET= target; - FAPI_SET_HWP_ERROR(o_rc,IO_FIR_MAX_SPARES_EXCEEDED_FIR_RC); - } - return(o_rc); -} - -// These functions work on a pair of targets. One is the master side of the bus interface, the other the slave side. For eg; in EDI(DMI2)PU is the master and Centaur is the slave -// In EI4 both sides have pu targets . After the talk with Dean , my understanding is that targets are configured down upto the endpoints of a particular bus. eg; pu 0 A0 --> pu 1 A3 could be a combination on EI4 -// In a EDI(DMI) bus the targets are considered to be one pu and one centaur pair . The overall code is same for EDI and EI4 and the run_training function handles both bus types ( X ,A or MC ) . -ReturnCode io_run_training(const Target &master_target,const Target &slave_target){ - ReturnCode rc; - io_interface_t master_interface,slave_interface; - uint32_t master_group=0; - uint32_t slave_group=0; - const uint32_t max_group=4; // Num of X bus groups in one bus - edi_training init; - - // Workaround - HW 220654 -- Need to split WDERF into WDE + RF - edi_training init1(SELECTED,SELECTED,SELECTED, NOT_RUNNING, NOT_RUNNING); // Run WDE first - - // For Xbus DLL Workaround , we need Wiretest alone , then DE and RF - - // For Xbus DLL Workaround , we need Wiretest alone , then DE and RF - edi_training init_w(SELECTED,NOT_RUNNING, NOT_RUNNING, NOT_RUNNING, NOT_RUNNING); // Run W for Xbus - edi_training init_wde(SELECTED,SELECTED,SELECTED, NOT_RUNNING, NOT_RUNNING); // Run DE next for X bus - - // For the PLL workaround we need a DE Object since DE + RF should be separate as per original guidelines - edi_training init_de(NOT_RUNNING,SELECTED,SELECTED, NOT_RUNNING, NOT_RUNNING); - - // Need an object to restore object state after one wiretest run. - edi_training copy_w=init_w; - // DE & RF needs to be split due to HW 220654 - edi_training init2( NOT_RUNNING, NOT_RUNNING, NOT_RUNNING,SELECTED,SELECTED); // Run RF next - bool is_master=false; - //FIR workaround buffers - //These buffers will store old bad lane info that was restored prior to training - ecmdDataBufferBase slave_data_one_old[4]; - ecmdDataBufferBase slave_data_two_old[4]; - ecmdDataBufferBase master_data_one_old[4]; - ecmdDataBufferBase master_data_two_old[4]; - - - // This is a DMI/MC bus - if( (master_target.getType() == fapi::TARGET_TYPE_MCS_CHIPLET )&& - (slave_target.getType() == fapi::TARGET_TYPE_MEMBUF_CHIP)) - { - FAPI_DBG("This is a DMI bus using base DMI scom address"); - master_interface=CP_IOMC0_P0; // base scom for MC bus - slave_interface=CEN_DMI; // Centaur scom base - master_group=3; // Design requires us to do this as per scom map and layout - slave_group=0; - rc=fir_workaround_pre_training(master_target,master_interface,master_group, - slave_target,slave_interface,slave_group, - slave_data_one_old,slave_data_two_old, - master_data_one_old,master_data_two_old); - if(rc) return rc; - // Workaround - HW 220654 -- Need to split WDERF into WDE + RF due to sync problem - // For PLL workaround now we run W alone , followed by DE then RF - rc=init_w.run_training(master_target,master_interface,master_group, - slave_target,slave_interface,slave_group); - if(!rc.ok()){ - return rc; - } - - // Now Set PLL to runtime setting and continue with training - // Call Janani's PLL ring set function from DCCAL module. It in turn uses Joe's funcs - - rc=io_training_set_pll_post_wiretest(slave_target); - //FAPI_DBG("Waiting for 1s after PLL Update on slave"); - //rc=fapiDelay(1000000,1000); - - if(!rc.ok()){ - FAPI_DBG("PLL SETTING FAILED ON SLAVE SIDE "); - return rc; - } - rc=io_training_set_pll_post_wiretest(master_target); - if(!rc.ok()){ - FAPI_DBG("PLL SETTING FAILED ON MASTER SIDE "); - return rc; - } - // FAPI_DBG("Waiting for 1s after PLL Update on master"); - // rc=fapiDelay(1000000,1000); - // Run DE Now - as per Gary - rc=init_de.run_training(master_target,master_interface,master_group, - slave_target,slave_interface,slave_group); - if(!rc.ok()){ - return rc; - } - //Now Run RF - rc=init2.run_training(master_target,master_interface,master_group, - slave_target,slave_interface,slave_group); - if(rc) return rc; - rc=fir_workaround_post_training(master_target,master_interface, - master_group,slave_target, - slave_interface,slave_group, - slave_data_one_old,slave_data_two_old, - master_data_one_old,master_data_two_old); - if(rc) return rc; - rc=handle_max_spare(master_target,master_interface,master_group); - if(rc) return rc; - rc=handle_max_spare(slave_target,slave_interface,slave_group); - if(rc) return rc; - - - } - //This is an X Bus - else if( (master_target.getType() == fapi::TARGET_TYPE_XBUS_ENDPOINT )&& - (slave_target.getType() == fapi::TARGET_TYPE_XBUS_ENDPOINT )) - { - FAPI_DBG("This is a X Bus training invocation"); - master_interface=CP_FABRIC_X0; // base scom for X bus - slave_interface=CP_FABRIC_X0; // base scom for X bus - slave_group=0; // Design requires us to do this as per scom map and layout - master_group=0; - uint8_t trial_count=0; - //HW249235 --For DLL workaround - bool dll_master_array[24],dll_slave_array[24]; // DLL array for each clock group - bool dll_workaround_done=false; - bool dll_workaround_fail=false; - - //init Bool array - for(int i=0;i<24;++i){ - dll_master_array[i]=false; - dll_slave_array[i]=false; - } - - rc=init.isChipMaster(master_target,master_interface,master_group,is_master); - if(rc.ok()){ - if(!is_master) - { - //Swap slave and slave targets !! - FAPI_DBG("X Bus ..target swap performed"); - rc=fir_workaround_pre_training(slave_target,slave_interface, - slave_group,slave_target, - slave_interface,slave_group, - slave_data_one_old,slave_data_two_old, - master_data_one_old,master_data_two_old); - if(rc) return rc; + } + rc=GCR_write(slave_target, slave_interface, ei4_rx_spare_mode_pg , current_group,0, set_bits, clear_bits); + if(rc){return rc;} + } + return rc; + } + + // To handle the MAX_SPARE_EXCEEDED FIR case which we have to handle here in our HWP instead of waiting for PRD. + ReturnCode handle_max_spare(const Target &target,io_interface_t interface,uint8_t current_group){ + ReturnCode o_rc; + uint32_t rc_ecmd=0; + ecmdDataBufferBase error_data(16); + uint32_t bitPos=0x2680; + + if(interface==CP_FABRIC_X0){ + o_rc=GCR_read(target , interface, ei4_rx_fir_training_pg, current_group,0, error_data); + } + else{ + o_rc=GCR_read(target , interface, rx_fir_training_pg, current_group,0, error_data); + } + if(o_rc) + return o_rc; + if(error_data.isBitSet(2,1)){ // can be caused by a static (pre training - bit 2) or dynamic (post training - bit 5) or recal(bit 8) + FAPI_ERR("MAX_SPARE_EXCEEDED ON THIS BUS clock group %d",current_group); + rc_ecmd = error_data.setAnd(bitPos,0,16); + if(rc_ecmd) + { + FAPI_ERR("Failed buffer manipulation in handle_max_spare \n"); + o_rc.setEcmdError(rc_ecmd); + return o_rc; + } + ecmdDataBufferBase & SPARE_ERROR_REG = error_data; //bit2 /bit 5 /bit 8of the register represents the max spare exceeded bit.To determine what caused the max spares exceeded error + const fapi::Target & CHIP_TARGET= target; + FAPI_SET_HWP_ERROR(o_rc,IO_RUN_TRAINING_FIR_MAX_SPARES_EXCEEDED_RC); + } + return(o_rc); + } + + // These functions work on a pair of targets. One is the master side of the bus interface, the other the slave side. For eg; in EDI(DMI2)PU is the master and Centaur is the slave + // In EI4 both sides have pu targets . After the talk with Dean , my understanding is that targets are configured down upto the endpoints of a particular bus. eg; pu 0 A0 --> pu 1 A3 could be a combination on EI4 + // In a EDI(DMI) bus the targets are considered to be one pu and one centaur pair . The overall code is same for EDI and EI4 and the run_training function handles both bus types ( X ,A or MC ) . + ReturnCode io_run_training(const Target &master_target,const Target &slave_target){ + ReturnCode rc; + io_interface_t master_interface,slave_interface; + uint32_t master_group=0; + uint32_t slave_group=0; + const uint32_t max_group=4; // Num of X bus groups in one bus + edi_training init; + + // Workaround - HW 220654 -- Need to split WDERF into WDE + RF + edi_training init1(SELECTED,SELECTED,SELECTED, NOT_RUNNING, NOT_RUNNING); // Run WDE first + + // For Xbus DLL Workaround , we need Wiretest alone , then DE and RF + + // For Xbus DLL Workaround , we need Wiretest alone , then DE and RF + edi_training init_w(SELECTED,NOT_RUNNING, NOT_RUNNING, NOT_RUNNING, NOT_RUNNING); // Run W for Xbus + edi_training init_wde(SELECTED,SELECTED,SELECTED, NOT_RUNNING, NOT_RUNNING); // Run DE next for X bus + + // For the PLL workaround we need a DE Object since DE + RF should be separate as per original guidelines + edi_training init_de(NOT_RUNNING,SELECTED,SELECTED, NOT_RUNNING, NOT_RUNNING); + + // Need an object to restore object state after one wiretest run. + edi_training copy_w=init_w; + // DE & RF needs to be split due to HW 220654 + edi_training init2( NOT_RUNNING, NOT_RUNNING, NOT_RUNNING,SELECTED,SELECTED); // Run RF next + bool is_master=false; + //FIR workaround buffers + //These buffers will store old bad lane info that was restored prior to training + ecmdDataBufferBase slave_data_one_old[4]; + ecmdDataBufferBase slave_data_two_old[4]; + ecmdDataBufferBase master_data_one_old[4]; + ecmdDataBufferBase master_data_two_old[4]; + + + // This is a DMI/MC bus + if( (master_target.getType() == fapi::TARGET_TYPE_MCS_CHIPLET )&& + (slave_target.getType() == fapi::TARGET_TYPE_MEMBUF_CHIP)) + { + FAPI_DBG("This is a DMI bus using base DMI scom address"); + master_interface=CP_IOMC0_P0; // base scom for MC bus + slave_interface=CEN_DMI; // Centaur scom base + master_group=3; // Design requires us to do this as per scom map and layout + slave_group=0; + rc=fir_workaround_pre_training(master_target,master_interface,master_group, + slave_target,slave_interface,slave_group, + slave_data_one_old,slave_data_two_old, + master_data_one_old,master_data_two_old); + if(rc) return rc; + // Workaround - HW 220654 -- Need to split WDERF into WDE + RF due to sync problem + // For PLL workaround now we run W alone , followed by DE then RF + rc=init_w.run_training(master_target,master_interface,master_group, + slave_target,slave_interface,slave_group); + if(!rc.ok()){ + return rc; + } + + // Now Set PLL to runtime setting and continue with training + // Call Janani's PLL ring set function from DCCAL module. It in turn uses Joe's funcs + + rc=io_training_set_pll_post_wiretest(slave_target); + //FAPI_DBG("Waiting for 1s after PLL Update on slave"); + //rc=fapiDelay(1000000,1000); + + if(!rc.ok()){ + FAPI_DBG("PLL SETTING FAILED ON SLAVE SIDE "); + return rc; + } + rc=io_training_set_pll_post_wiretest(master_target); + if(!rc.ok()){ + FAPI_DBG("PLL SETTING FAILED ON MASTER SIDE "); + return rc; + } + // FAPI_DBG("Waiting for 1s after PLL Update on master"); + // rc=fapiDelay(1000000,1000); + // Run DE Now - as per Gary + rc=init_de.run_training(master_target,master_interface,master_group, + slave_target,slave_interface,slave_group); + if(!rc.ok()){ + return rc; + } + //Now Run RF + rc=init2.run_training(master_target,master_interface,master_group, + slave_target,slave_interface,slave_group); + if(rc) return rc; + rc=fir_workaround_post_training(master_target,master_interface, + master_group,slave_target, + slave_interface,slave_group, + slave_data_one_old,slave_data_two_old, + master_data_one_old,master_data_two_old); + if(rc) return rc; + rc=handle_max_spare(master_target,master_interface,master_group); + if(rc) return rc; + rc=handle_max_spare(slave_target,slave_interface,slave_group); + if(rc) return rc; + + + } + //This is an X Bus + else if( (master_target.getType() == fapi::TARGET_TYPE_XBUS_ENDPOINT )&& + (slave_target.getType() == fapi::TARGET_TYPE_XBUS_ENDPOINT )) + { + FAPI_DBG("This is a X Bus training invocation"); + master_interface=CP_FABRIC_X0; // base scom for X bus + slave_interface=CP_FABRIC_X0; // base scom for X bus + slave_group=0; // Design requires us to do this as per scom map and layout + master_group=0; + uint8_t trial_count=0; + //HW249235 --For DLL workaround + bool dll_master_array[24],dll_slave_array[24]; // DLL array for each clock group + bool dll_workaround_done=false; + bool dll_workaround_fail=false; + + //init Bool array + for(int i=0;i<24;++i){ + dll_master_array[i]=false; + dll_slave_array[i]=false; + } + + rc=init.isChipMaster(master_target,master_interface,master_group,is_master); + if(rc.ok()){ + if(!is_master) + { + //Swap slave and slave targets !! + FAPI_DBG("X Bus ..target swap performed"); + rc=fir_workaround_pre_training(slave_target,slave_interface, + slave_group,slave_target, + slave_interface,slave_group, + slave_data_one_old,slave_data_two_old, + master_data_one_old,master_data_two_old); + if(rc) return rc; do { - trial_count++; - FAPI_DBG("TRAINING TRIAL count=%d",trial_count); - rc=init_w.run_training(slave_target,slave_interface, - slave_group,master_target, - master_interface,master_group); - if(rc) { - //HW249235 --For DLL workaround - FAPI_DBG("Starting DLL Workaround"); - rc=check_dll_status_and_modify(slave_target, - slave_interface, - master_target, - master_interface, - dll_slave_array, - dll_master_array, - dll_workaround_done, - dll_workaround_fail); - if(rc) return rc; - // Reset tx drive pattern to 0000 before starting Wiretest again -- As per Rob /Pete - //Prep the targets for next round of WDE training -- Steps by Rob & Pete - if(!dll_workaround_done) - { - rc=set_tx_drv_pattern(slave_target, - slave_interface, - slave_group, - master_target, - master_interface, - master_group); - } - if(rc) return rc; - } - else{ - if(trial_count>1){ - FAPI_DBG("DLL workaround was successfull"); - } - dll_workaround_done=true; - } - init_w=copy_w; + trial_count++; + FAPI_DBG("TRAINING TRIAL count=%d",trial_count); + rc=init_w.run_training(slave_target,slave_interface, + slave_group,master_target, + master_interface,master_group); + if(rc) { + //HW249235 --For DLL workaround + FAPI_DBG("Starting DLL Workaround"); + rc=check_dll_status_and_modify(slave_target, + slave_interface, + master_target, + master_interface, + dll_slave_array, + dll_master_array, + dll_workaround_done, + dll_workaround_fail); + if(rc) return rc; + // Reset tx drive pattern to 0000 before starting Wiretest again -- As per Rob /Pete + //Prep the targets for next round of WDE training -- Steps by Rob & Pete + if(!dll_workaround_done) + { + rc=set_tx_drv_pattern(slave_target, + slave_interface, + slave_group, + master_target, + master_interface, + master_group); + if(rc) return rc; + } + + } + else{ + if(trial_count>1){ + FAPI_DBG("DLL workaround was successfull"); + } + dll_workaround_done=true; + } + init_w=copy_w; }while(!dll_workaround_done); if(!dll_workaround_fail){ - // We need to reset Wirtest machine so that we can do WDE again - rc=set_tx_drv_pattern(slave_target,slave_interface, - slave_group,master_target, - master_interface,master_group); - if(rc) return rc; - rc=init_wde.run_training(slave_target,slave_interface, - slave_group,master_target, - master_interface,master_group); - if(rc) return rc; - rc=init2.run_training(slave_target,slave_interface, - slave_group,master_target, - master_interface,master_group); - if(rc) return rc; - rc=fir_workaround_post_training(slave_target, - slave_interface, - slave_group, - slave_target, - slave_interface, - slave_group, - slave_data_one_old, - slave_data_two_old, - master_data_one_old, - master_data_two_old); - if(rc) return rc; - //HW Defect HW220449 , HW HW247831 - // Set rx_sls_extend_sel=001 on slave side of X bus post training - rc=do_sls_fix(master_target,master_interface); - if(rc) return rc; + // We need to reset Wirtest machine so that we can do WDE again + rc=set_tx_drv_pattern(slave_target,slave_interface, + slave_group,master_target, + master_interface,master_group); + if(rc) return rc; + rc=init_wde.run_training(slave_target,slave_interface, + slave_group,master_target, + master_interface,master_group); + if(rc) return rc; + rc=init2.run_training(slave_target,slave_interface, + slave_group,master_target, + master_interface,master_group); + if(rc) return rc; + rc=fir_workaround_post_training(slave_target, + slave_interface, + slave_group, + slave_target, + slave_interface, + slave_group, + slave_data_one_old, + slave_data_two_old, + master_data_one_old, + master_data_two_old); + if(rc) return rc; + //HW Defect HW220449 , HW HW247831 + // Set rx_sls_extend_sel=001 on slave side of X bus post training + rc=do_sls_fix(master_target,master_interface); + if(rc) return rc; } - } - else{ + } + else{ rc=fir_workaround_pre_training(master_target, - master_interface, - master_group, - slave_target, - slave_interface, - slave_group, - master_data_one_old, - master_data_two_old, - slave_data_one_old, - slave_data_two_old); + master_interface, + master_group, + slave_target, + slave_interface, + slave_group, + master_data_one_old, + master_data_two_old, + slave_data_one_old, + slave_data_two_old); if(rc) return rc; - do{ - trial_count++; - FAPI_DBG("TRAINING TRIAL count=%d",trial_count); - rc=init_w.run_training(master_target,master_interface,master_group,slave_target,slave_interface,slave_group); - if(rc) { - //HW249235 --For DLL workaround - FAPI_DBG("Starting DLL Workaround"); - rc=check_dll_status_and_modify(master_target,master_interface,slave_target,slave_interface, - dll_master_array,dll_slave_array,dll_workaround_done,dll_workaround_fail); - if(rc) return rc; - // Reset tx drive pattern to 0000 before starting Wiretest again -- As per Rob /Pete - //Prep the targets for next round of WDE training -- Steps by Rob & Pete - if(!dll_workaround_done){ - rc=set_tx_drv_pattern(master_target,master_interface,master_group,slave_target,slave_interface, - slave_group); - } - if(rc) return rc; - } - else{ - if(trial_count>1){ - FAPI_DBG("DLL workaround was successfull"); - } - dll_workaround_done=true; - } - init_w=copy_w;// Reset training object state to default + do{ + trial_count++; + FAPI_DBG("TRAINING TRIAL count=%d",trial_count); + rc=init_w.run_training(master_target,master_interface,master_group,slave_target,slave_interface,slave_group); + if(rc) { + //HW249235 --For DLL workaround + FAPI_DBG("Starting DLL Workaround"); + rc=check_dll_status_and_modify(master_target,master_interface,slave_target,slave_interface, + dll_master_array,dll_slave_array,dll_workaround_done,dll_workaround_fail); + if(rc) return rc; + // Reset tx drive pattern to 0000 before starting Wiretest again -- As per Rob /Pete + //Prep the targets for next round of WDE training -- Steps by Rob & Pete + if(!dll_workaround_done){ + rc=set_tx_drv_pattern(master_target,master_interface,master_group,slave_target,slave_interface, + slave_group); + if(rc) return rc; + } + } + else{ + if(trial_count>1){ + FAPI_DBG("DLL workaround was successfull"); + } + dll_workaround_done=true; + } + init_w=copy_w;// Reset training object state to default }while(!dll_workaround_done); if(!dll_workaround_fail){ - // We need to reset Wirtest machine so that we can do WDE again - rc=set_tx_drv_pattern(master_target,master_interface,master_group,slave_target,slave_interface, - slave_group); - if(rc) return rc; - rc=init_wde.run_training(master_target,master_interface,master_group,slave_target,slave_interface,slave_group); - if(rc) { - - return rc;} - - rc=init2.run_training(master_target,master_interface,master_group,slave_target,slave_interface,slave_group); - if(rc) return rc; - rc=fir_workaround_post_training(master_target,master_interface,master_group,slave_target,slave_interface,slave_group, - master_data_one_old,master_data_two_old,slave_data_one_old,slave_data_two_old); - if(rc) return rc; - - //HW Defect HW220449 , HW HW247831 - // Set rx_sls_extend_sel=001 on slave side of X bus post training + // We need to reset Wirtest machine so that we can do WDE again + rc=set_tx_drv_pattern(master_target,master_interface,master_group,slave_target,slave_interface, + slave_group); + if(rc) return rc; + rc=init_wde.run_training(master_target,master_interface,master_group,slave_target,slave_interface,slave_group); + if(rc) return rc; + rc=init2.run_training(master_target,master_interface,master_group,slave_target,slave_interface,slave_group); + if(rc) return rc; + rc=fir_workaround_post_training(master_target,master_interface,master_group,slave_target,slave_interface,slave_group, + master_data_one_old,master_data_two_old,slave_data_one_old,slave_data_two_old); + if(rc) return rc; + + //HW Defect HW220449 , HW HW247831 + // Set rx_sls_extend_sel=001 on slave side of X bus post training rc=do_sls_fix(slave_target,slave_interface); if(rc) return rc; } - } - for(uint32_t current_group=0;current_group<max_group;++current_group){ + } + for(uint32_t current_group=0;current_group<max_group;++current_group){ rc=handle_max_spare(master_target,master_interface,current_group); if(rc) return rc; rc=handle_max_spare(slave_target,slave_interface,current_group); if(rc) return rc; - } - } - } - //This is an A Bus - else if( (master_target.getType() == fapi::TARGET_TYPE_ABUS_ENDPOINT )&& (slave_target.getType() == fapi::TARGET_TYPE_ABUS_ENDPOINT)){ - FAPI_DBG("This is an A Bus training invocation"); - master_interface=CP_FABRIC_A0; // base scom for A bus , assume translation to A1 by PLAT - slave_interface=CP_FABRIC_A0; //base scom for A bus - master_group=0; // Design requires us to do this as per scom map and layout - slave_group=0; - rc=init.isChipMaster(master_target,master_interface,master_group,is_master); - if(rc.ok()){ - if(!is_master) - { + } + } + } + //This is an A Bus + else if( (master_target.getType() == fapi::TARGET_TYPE_ABUS_ENDPOINT )&& (slave_target.getType() == fapi::TARGET_TYPE_ABUS_ENDPOINT)){ + FAPI_DBG("This is an A Bus training invocation"); + master_interface=CP_FABRIC_A0; // base scom for A bus , assume translation to A1 by PLAT + slave_interface=CP_FABRIC_A0; //base scom for A bus + master_group=0; // Design requires us to do this as per scom map and layout + slave_group=0; + rc=init.isChipMaster(master_target,master_interface,master_group,is_master); + if(rc.ok()){ + if(!is_master) + { FAPI_DBG("A Bus ..target swap performed"); - + rc=fir_workaround_pre_training(slave_target,slave_interface, - slave_group,slave_target, - slave_interface,slave_group, - slave_data_one_old,slave_data_two_old, - master_data_one_old,master_data_two_old); - + slave_group,slave_target, + slave_interface,slave_group, + slave_data_one_old,slave_data_two_old, + master_data_one_old,master_data_two_old); + if(rc) return rc; rc=init_w.run_training(slave_target,slave_interface,slave_group,master_target,master_interface,master_group); - + if(!rc.ok()){ - return rc; + return rc; } - + // Now Set PLL to runtime setting and continue with training // Call Janani's PLL ring set function from DCCAL module. It in turn uses Joe's funcs - + rc=io_training_set_pll_post_wiretest(slave_target); - + if(!rc.ok()){ - FAPI_DBG("PLL SETTING FAILED ON SLAVE SIDE "); - return rc; + FAPI_DBG("PLL SETTING FAILED ON SLAVE SIDE "); + return rc; } rc=io_training_set_pll_post_wiretest(master_target); if(!rc.ok()){ - FAPI_DBG("PLL SETTING FAILED ON MASTER SIDE "); - return rc; + FAPI_DBG("PLL SETTING FAILED ON MASTER SIDE "); + return rc; } rc=init_de.run_training(slave_target,slave_interface,slave_group,master_target,master_interface,master_group); if(rc) return rc; - + // Now do RF rc=init2.run_training(slave_target,slave_interface,slave_group, - master_target,master_interface,master_group); + master_target,master_interface,master_group); if(rc) return rc; rc=fir_workaround_post_training(slave_target, - slave_interface, - slave_group, - slave_target, - slave_interface, - slave_group, - slave_data_one_old, - slave_data_two_old, - master_data_one_old, - master_data_two_old); + slave_interface, + slave_group, + slave_target, + slave_interface, + slave_group, + slave_data_one_old, + slave_data_two_old, + master_data_one_old, + master_data_two_old); if(rc) return rc; - } - else - { - + } + else + { + rc=fir_workaround_pre_training(master_target,master_interface,master_group,slave_target,slave_interface,slave_group, - slave_data_one_old,slave_data_two_old,master_data_one_old,master_data_two_old); + slave_data_one_old,slave_data_two_old,master_data_one_old,master_data_two_old); if(rc) return rc; rc=init_w.run_training(master_target,master_interface,master_group,slave_target,slave_interface,slave_group); - + if(!rc.ok()){ - return rc; + return rc; } - + // Now Set PLL to runtime setting and continue with training // Call Janani's PLL ring set function from DCCAL module. It in turn uses Joe's funcs - + rc=io_training_set_pll_post_wiretest(slave_target); - + if(!rc.ok()){ - FAPI_DBG("PLL SETTING FAILED ON SLAVE SIDE "); - return rc; + FAPI_DBG("PLL SETTING FAILED ON SLAVE SIDE "); + return rc; } rc=io_training_set_pll_post_wiretest(master_target); if(!rc.ok()){ - FAPI_DBG("PLL SETTING FAILED ON MASTER SIDE "); - return(rc); + FAPI_DBG("PLL SETTING FAILED ON MASTER SIDE "); + return(rc); } rc=init_de.run_training(master_target,master_interface,master_group,slave_target,slave_interface,slave_group); if(rc) return rc; - + // Now do RF rc=init2.run_training(master_target,master_interface,master_group, - slave_target,slave_interface,slave_group); + slave_target,slave_interface,slave_group); if(rc) return rc; rc=fir_workaround_post_training(master_target,master_interface,master_group,slave_target,slave_interface,slave_group, - slave_data_one_old,slave_data_two_old,master_data_one_old,master_data_two_old); + slave_data_one_old,slave_data_two_old,master_data_one_old,master_data_two_old); if(rc) return rc; - } - } - } - else{ - FAPI_ERR("Invalid io_run_training HWP invocation . Pair of targets dont belong to DMI/X/A instances"); - FAPI_SET_HWP_ERROR(rc, IO_RUN_TRAINING_INVALID_INVOCATION_RC); - } - return rc; -} + } + } + } + else{ + FAPI_ERR("Invalid io_run_training HWP invocation . Pair of targets dont belong to DMI/X/A instances"); + const fapi::Target &MASTER_TARGET = master_target; + const fapi::Target &SLAVE_TARGET = slave_target; + FAPI_SET_HWP_ERROR(rc, IO_RUN_TRAINING_INVALID_TARGET_PAIR_RC); + } + return rc; + } } // extern diff --git a/src/usr/hwpf/hwp/bus_training/io_run_training.H b/src/usr/hwpf/hwp/bus_training/io_run_training.H index a0581aada..95fcdf50a 100644 --- a/src/usr/hwpf/hwp/bus_training/io_run_training.H +++ b/src/usr/hwpf/hwp/bus_training/io_run_training.H @@ -5,7 +5,7 @@ /* */ /* IBM CONFIDENTIAL */ /* */ -/* COPYRIGHT International Business Machines Corp. 2012,2013 */ +/* COPYRIGHT International Business Machines Corp. 2012,2014 */ /* */ /* p1 */ /* */ @@ -20,35 +20,36 @@ /* Origin: 30 */ /* */ /* IBM_PROLOG_END_TAG */ -// $Id: io_run_training.H,v 1.8 2012/12/04 08:29:20 varkeykv Exp $
-#ifndef IO_RUN_TRAINING_H_
-#define IO_RUN_TRAINING_H_
-
-#include <fapi.H>
-
-using namespace fapi;
-
-/**
- * io_run_training func pointer Typedef for hostboot
- *
- */
-typedef fapi::ReturnCode (*io_run_training_FP_t)(const fapi::Target &,const fapi::Target &);
-
-extern "C"
-{
-
-/**
- * io_run_training
- *
- * master_target is the master side of a bus ..p8.mcs in a DMI .. or a p8.abus/p8.xbus in fabric
- * slave_target - slave side of the bus .. Centaur in DMI , p8.xbus or p8.abus for fabric
- * while these are called master or slave... I actually do a check in the code to see
- * whether these are actually master chips by reading a GCR master_mode bit
- * and accordingly will perform a target swap if required
- * @return ReturnCode
- */
-fapi::ReturnCode io_run_training(const fapi::Target &master_target,const fapi::Target & slave_target);
-
-} // extern "C"
-
-#endif // IO_RUN_TRAINING_H
+// $Id: io_run_training.H,v 1.9 2014/03/05 11:56:29 varkeykv Exp $ +#ifndef IO_RUN_TRAINING_H_ +#define IO_RUN_TRAINING_H_ + + +#include <fapi.H> + +using namespace fapi; + +/** + * io_run_training func pointer Typedef for hostboot + * + */ +typedef fapi::ReturnCode (*io_run_training_FP_t)(const fapi::Target &,const fapi::Target &); + +extern "C" +{ + +/** + * io_run_training + * + * master_target is the master side of a bus ..p8.mcs in a DMI .. or a p8.abus/p8.xbus in fabric + * slave_target - slave side of the bus .. Centaur in DMI , p8.xbus or p8.abus for fabric + * while these are called master or slave... I actually do a check in the code to see + * whether these are actually master chips by reading a GCR master_mode bit + * and accordingly will perform a target swap if required + * @return ReturnCode + */ +fapi::ReturnCode io_run_training(const fapi::Target &master_target,const fapi::Target & slave_target); + +} // extern "C" + +#endif // IO_RUN_TRAINING_H diff --git a/src/usr/hwpf/hwp/bus_training/io_run_training_errors.xml b/src/usr/hwpf/hwp/bus_training/io_run_training_errors.xml new file mode 100644 index 000000000..469fa7359 --- /dev/null +++ b/src/usr/hwpf/hwp/bus_training/io_run_training_errors.xml @@ -0,0 +1,105 @@ +<!-- IBM_PROLOG_BEGIN_TAG --> +<!-- This is an automatically generated prolog. --> +<!-- --> +<!-- $Source: src/usr/hwpf/hwp/bus_training/io_run_training_errors.xml $ --> +<!-- --> +<!-- IBM CONFIDENTIAL --> +<!-- --> +<!-- COPYRIGHT International Business Machines Corp. 2012,2014 --> +<!-- --> +<!-- p1 --> +<!-- --> +<!-- Object Code Only (OCO) source materials --> +<!-- Licensed Internal Code Source Materials --> +<!-- IBM HostBoot Licensed Internal Code --> +<!-- --> +<!-- The source code for this program is not published or otherwise --> +<!-- divested of its trade secrets, irrespective of what has been --> +<!-- deposited with the U.S. Copyright Office. --> +<!-- --> +<!-- Origin: 30 --> +<!-- --> +<!-- IBM_PROLOG_END_TAG --> +<!-- $Id: io_run_training_errors.xml,v 1.8 2014/03/17 18:54:00 dedahle Exp $ --> +<!-- Error definitions for IO_RUN_TRAINING --> +<hwpErrors> + <hwpError> + <rc>IO_RUN_TRAINING_SET_PLL_INVALID_INVOCATION_RC</rc> + <description>io_training_set_pll_post_wiretest invoked with incorrect target type</description> + <ffdc>TARGET</ffdc> + <callout> + <procedure>CODE</procedure> + <priority>HIGH</priority> + </callout> + </hwpError> + <!-- *********************************************************************** --> + <hwpError> + <rc>IO_RUN_TRAINING_POST_TRAINING_INVALID_INVOCATION_RC</rc> + <description>io_training_set_pll_post_wiretest invoked with incorrect target type</description> + <ffdc>TARGET</ffdc> + <callout> + <procedure>CODE</procedure> + <priority>HIGH</priority> + </callout> + </hwpError> + <!-- *********************************************************************** --> + <hwpError> + <rc>IO_RUN_TRAINING_CHECK_DLL_VAL_OUT_OF_BOUND_RC</rc> + <description>DLL Workaround encountered unexpected start value</description> + <ffdc>DLL_REG</ffdc> + <callout> + <target>TARGET</target> + <priority>HIGH</priority> + </callout> + <deconfigure> + <target>TARGET</target> + </deconfigure> + <gard> + <target>TARGET</target> + </gard> + </hwpError> + <!-- *********************************************************************** --> + <hwpError> + <rc>IO_RUN_TRAINING_CHECK_DLL_WORKAROUND_FAIL</rc> + <description>DLL Workaround failed to arrive at a solution</description> + <ffdc>DLL_REG</ffdc> + <callout> + <target>TARGET</target> + <priority>HIGH</priority> + </callout> + <deconfigure> + <target>TARGET</target> + </deconfigure> + <gard> + <target>TARGET</target> + </gard> + </hwpError> + <!-- *********************************************************************** --> + <hwpError> + <rc>IO_RUN_TRAINING_FIR_MAX_SPARES_EXCEEDED_RC</rc> + <description>maximum spares possible to deploy exceeded</description> + <ffdc>CHIP_TARGET</ffdc> + <ffdc>SPARE_ERROR_REG</ffdc> + <callout> + <target>CHIP_TARGET</target> + <priority>HIGH</priority> + </callout> + <deconfigure> + <target>CHIP_TARGET</target> + </deconfigure> + <gard> + <target>CHIP_TARGET</target> + </gard> + </hwpError> + <!-- *********************************************************************** --> + <hwpError> + <rc>IO_RUN_TRAINING_INVALID_TARGET_PAIR_RC</rc> + <description>io_run_training invoked with wrong pair of targets</description> + <ffdc>MASTER_TARGET</ffdc> + <ffdc>SLAVE_TARGET</ffdc> + <callout> + <procedure>CODE</procedure> + <priority>HIGH</priority> + </callout> + </hwpError> +</hwpErrors> diff --git a/src/usr/hwpf/hwp/bus_training/makefile b/src/usr/hwpf/hwp/bus_training/makefile index 75af4954a..dcfc2552a 100644 --- a/src/usr/hwpf/hwp/bus_training/makefile +++ b/src/usr/hwpf/hwp/bus_training/makefile @@ -31,6 +31,7 @@ EXTRAINCDIR += ${ROOTPATH}/src/include/usr/hwpf/fapi EXTRAINCDIR += ${ROOTPATH}/src/include/usr/hwpf/plat EXTRAINCDIR += ${ROOTPATH}/src/include/usr/hwpf/hwp EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/nest_chiplets/proc_a_x_pci_dmi_pll_setup +EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/bus_training ## pointer to common HWP files EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/include diff --git a/src/usr/hwpf/makefile b/src/usr/hwpf/makefile index f393eee62..9acf90e55 100644 --- a/src/usr/hwpf/makefile +++ b/src/usr/hwpf/makefile @@ -32,7 +32,6 @@ SUBDIRS = fapi.d hwp.d plat.d test.d #------------------------------------------------------------------------------ HWP_ERROR_XML_FILES = hwp/fapiHwpErrorInfo.xml \ hwp/dmi_training/proc_cen_framelock/proc_cen_framelock_errors.xml \ - hwp/bus_training/io_errors.xml \ hwp/dimm_errors.xml \ hwp/chip_accessors/chip_errors.xml \ hwp/dram_training/memory_errors.xml \ @@ -138,7 +137,16 @@ HWP_ERROR_XML_FILES = hwp/fapiHwpErrorInfo.xml \ hwp/runtime_errors/p8_pstate_registers.xml \ hwp/mc_config/mss_eff_mb_interleave/memory_mss_eff_mb_interleave.xml \ hwp/nest_chiplets/proc_a_x_pci_dmi_pll_registers.xml \ - hwp/dram_training/mss_lrdimm_funcs/memory_mss_lrdimm_funcs.xml + hwp/dram_training/mss_lrdimm_funcs/memory_mss_lrdimm_funcs.xml \ + hwp/bus_training/gcr_funcs_errors.xml \ + hwp/bus_training/io_run_training_errors.xml \ + hwp/bus_training/io_funcs_errors.xml \ + hwp/bus_training/io_dccal_errors.xml \ + hwp/bus_training/io_power_down_lanes_errors.xml \ + hwp/bus_training/io_read_erepair_errors.xml \ + hwp/bus_training/io_fir_isolation_errors.xml \ + hwp/bus_training/io_restore_erepair_errors.xml \ + hwp/bus_training/io_cleanup_errors.xml ## these get generated into obj/genfiles/AttributeIds.H HWP_ATTR_XML_FILES = hwp/memory_attributes.xml \ |
